JP2005277108A - Method of manufacturing silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method capable of making an impurity ion implantation region and an electrode connected thereto formed in a self-aligning manner. <P>SOLUTION: An oxide film is formed on an n-type silicon carbide semiconductor layer. The oxide film on which a source region and a drain region are formed is etched to be eliminated. An impurity ion is implanted into the exposed semiconductor layer. Thermal treatment is carried out for activation. A source electrode and a drain electrode are formed by forming a metal film for an ohmic electrode on the entire surface, and making the oxide film etched to be eliminated. If a portion of the oxide film of a region is left on which the source region and the drain electrode are formed, the deformation of the oxide film can be suppressed at the time of the thermal treatment for activation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for injecting impurity ions into a silicon carbide semiconductor layer and forming an ohmic electrode in a self-aligned region.

Silicon carbide (SiC), which is one of the wide gap semiconductors, has a band gap of 3.26 eV (4H—SiC), which is about three times larger than silicon. Further, the electric field breakdown electric field is about 10 times that of silicon, the electron saturation speed is 2 × 10 ⁷ cm / s, about twice that of silicon, and the thermal conductivity is 4.9 W / cm. It has a feature that k is about 3 times larger than silicon. Therefore, semiconductor devices using silicon carbide are expected to have high breakdown voltage, low loss, high output, and high efficiency, and have attracted attention in recent years.

  When forming a semiconductor device made of silicon carbide, an epitaxial layer is generally used. This is because, since the impurity diffusion coefficient of silicon carbide is small, it is not possible to employ a method of performing impurity diffusion from the vapor phase that is generally used in the manufacturing process of a semiconductor device made of silicon. In addition, the ion implantation method is also under study on impurities to be added and heat treatment temperature.

  As an example of a conventional semiconductor device made of silicon carbide, a method of manufacturing a field effect transistor using an epitaxial layer will be described. As shown in FIG. 5, first, a semiconductor substrate is prepared in which an n-type channel layer 2 and an n-type high-concentration layer 3 doped with impurities at a high concentration are epitaxially grown on a semi-insulating substrate 1 made of silicon carbide. FIG. 5a). In order to electrically isolate the adjacent field effect transistors from each other, the n-type high concentration layer 3 and the n-type channel layer 2 other than the field effect transistor formation region are removed by dry etching to expose the substrate 1 (FIG. 5b). ). Next, the n-type high concentration layer 3 is removed by a dry etching method except for the source electrode and drain electrode formation scheduled regions (FIG. 5c). A metal film that forms ohmic contact is deposited on the source electrode and drain electrode formation planned region by a normal photolithographic method, and heat treatment is performed as necessary to form the source electrode 4 and the drain electrode 5. Finally, a gate electrode 6 in Schottky contact with the n-type channel layer 2 is formed to complete a field effect transistor made of silicon carbide (FIG. 5d).

Further, the n-type high concentration layer 3 may be formed by implanting impurity ions instead of the epitaxial growth layer (see Patent Document 1). When impurity ions are implanted into a silicon carbide semiconductor to form a high concentration region, a high temperature heat treatment called activation annealing is required to activate the implanted impurity ions. For example, when activating nitrogen ions implanted into silicon carbide, it is necessary to perform heat treatment at 1200 ° C. (see Patent Document 2).
JP-A-5-175239 JP 2000-164525 A

  In the normal epitaxial growth method, the growth thickness and impurity concentration of the n-type high concentration layer 3 and the n-type channel layer 2 vary in the substrate plane. In the manufacturing method described above, since the gate electrode cannot be directly formed on the n-type high concentration layer 3, it is necessary to completely remove the n-type high concentration layer 3. In that case, the surface of the n-type channel layer 2 on which the gate electrode is formed is also etched at the same time. Therefore, in the substrate surface, in addition to the film thickness variation during epitaxial growth, the etching amount variation during etching occurs. Due to the variation in the thickness of the n-type channel layer 2 remaining directly under the gate electrode 6, there is a problem that the variation in the current value of the field effect transistor becomes large.

  On the other hand, when a high concentration region is formed by an ion implantation method, it is necessary to perform a heat treatment at about 1200 ° C. to activate the implanted impurity ions, and an oxide film or a photo film used as a mask film when the impurity ions are implanted. It was necessary to remove the resist once. Therefore, when forming the source electrode and the drain electrode that are in contact with the high concentration region, a technique for performing alignment with high accuracy is required, and a problem due to misalignment often occurs.

  In particular, in order to improve the high-frequency characteristics of the field effect transistor, it is necessary to form the source electrode and the gate electrode as close as possible, and the misalignment not only increases the variation in electrical characteristics, but also This has caused the problem of a short circuit of the gate electrode.

  In order to solve these problems, an object of the present invention is to provide a manufacturing method in which an impurity ion implantation region and an electrode connected to the impurity ion implantation region can be formed in a self-aligned manner.

  In order to achieve the above object, an invention according to claim 1 includes a step of preparing a semiconductor layer of one conductivity type made of a silicon carbide semiconductor, a step of forming an oxide film on the semiconductor layer of one conductivity type, Removing a part of the oxide film and exposing the one-conductivity-type semiconductor layer; implanting impurity ions into the exposed semiconductor layer; and performing a heat treatment to activate the impurity ions; A step of forming a semiconductor region of one conductivity type with a high impurity concentration, a step of covering the oxide film and the surface of the semiconductor region with a metal film that forms an ohmic contact with the semiconductor region, and etching away the oxide film And removing the metal film on the oxide film, selectively forming the metal film on the semiconductor region, and forming an electrode in ohmic contact with the semiconductor region. Than it is.

  According to a second aspect of the present invention, there is provided an ohmic method in which a step of preparing a semiconductor layer of one conductivity type made of a silicon carbide semiconductor layer, a step of forming an oxide film on the semiconductor layer of one conductivity type, and an ohmic separation at a predetermined interval Removing a part of the oxide film in the electrode formation scheduled region to form a recess, and implanting impurity ions into the semiconductor layer of one conductivity type through the oxide film in the recess to activate the impurity ions Forming a one-conductivity-type semiconductor region having a higher impurity concentration than the semiconductor layer, removing the oxide film remaining in the recess, and exposing the semiconductor region; and Coating the film and the surface of the semiconductor region with a metal film that forms an ohmic contact with the semiconductor region; and removing the oxide film by etching to remove the metal film on the oxide film; Selectively forming the metal film on a region to form the ohmic electrode, and forming a Schottky electrode to form a Schottky contact with the semiconductor layer on the semiconductor layer between the ohmic electrodes. It is characterized by including these.

  According to the present invention, since an impurity ion implantation region and an electrode connected to the impurity ion implantation region can be formed in a self-aligned manner, a semiconductor device that does not cause misalignment and has little variation in electrical characteristics is manufactured. Can do.

  In particular, when a field effect transistor for high frequency is formed according to the present invention, the interval between the source electrode and the drain electrode can be narrowed, and the high frequency characteristics can be improved. In addition, since the source region and the source electrode connected to the source region can be formed in a self-aligned manner, when the gate electrode is formed close to the source electrode, the gate electrode is not short-circuited to the source region and can be manufactured with high yield. There is an advantage that you can.

  Hereinafter, the present invention will be described in detail by taking a method of manufacturing a field effect transistor as an example.

1 and 2 show a first embodiment of the present invention. First, a photoresist 7 is patterned on the surface of the semi-insulating silicon carbide substrate 1 so as to open a field effect transistor formation scheduled region. Next, in order to form an n-type channel layer, an acceleration voltage and a dose amount of nitrogen ions in the opening are 170 eV · 2.8 × 10 ¹² atoms / cm ² and 125 eV · 1.8 × 10 ¹² atoms / cm, respectively. cm ² , 90 eV · 1.5 × 10 ¹² atoms / cm ² , 60 eV · 1.2 × 10 ¹² atoms / cm ² , 40 eV · 9.0 × 10 ¹¹ atoms / cm ² , 25 eV · 6.0 × 10 ¹¹ The injection is repeated 6 times under the condition of atom / cm ² . As a result, a channel region 8 having a depth of 300 nm and an impurity concentration of 3 × 10 ¹⁷ atoms / cm ³ is formed (FIG. 1a).

  After removing the photoresist 7, a silicon oxide film 9 is formed on the entire surface. The silicon oxide film 9 can be formed by chemical vapor deposition or sputtering. Further, the thickness is made thicker than the thickness of a metal film for forming an ohmic electrode described later. Next, in order to form a source region and a drain region, another photoresist 10 is patterned so as to open a source region and a drain region formation scheduled region on the surface of the silicon oxide film 9. Using the photoresist 10 as an etching mask, the silicon oxide film 9 is removed by etching to expose the channel layer 8 in the source region and drain region formation planned region (FIG. 1b).

After removing the photoresist 10, in order to form a high-concentration n-type source region and drain region, the silicon oxide film 9 is used as an implantation mask, and phosphorus ions are accelerating in the exposed channel layer 8 with an acceleration voltage and a dose. Are repeated three times under the conditions of 120 eV · 2.0 × 10 ¹⁵ atoms / cm ² , 70 eV · 1.0 × 10 ¹⁵ atoms / cm ² , and 40 eV · 5.0 × 10 ¹⁴ atoms / cm ^2. . Thereafter, a heat treatment for activating the implanted impurity ions is performed. In the present invention, the heat treatment is performed without removing the silicon oxide film 9. The heat treatment was performed at 1350 ° C. for 30 minutes under an inert gas atmosphere (for example, an argon gas atmosphere) and atmospheric pressure. By this heat treatment, the crystallinity of the ion-implanted layer can be restored and impurity ions can be activated, and the source region 11 and the drain region 12 are formed (FIG. 1c). In addition, it is necessary to perform the heat processing for activation in the temperature range of 1250 degreeC-1350 degreeC. In the temperature range that does not reach 1250 ° C., sufficient activation cannot be performed, and if it exceeds 1350 ° C., silicon is sublimated from the silicon carbide surface, the surface becomes rough, or the cross-sectional shape of the silicon oxide film 9 is deformed. This is because the metal film described later cannot be formed.

  Next, the entire surface is covered with a metal film 13 that forms ohmic contact with the high concentration n-type source region 11 and drain region 12 (FIG. 1d). As an example of the metal film, a nickel film is used. Since the silicon oxide film 9 is thicker than the metal film 13, the metal film 13 on the silicon oxide film 9 is separated from the metal film 13 on the source region 11 and the drain region 12. In this state, the silicon oxide film 9 is etched, and the silicon oxide film 9 is removed using a hydrofluoric acid solution that is an etching solution that does not etch the nickel film. As a result, the metal film 13 on the silicon oxide film 9 is removed, and the metal film 13 is selectively left on the source region 11 and the drain electrode 12. Thereafter, heat treatment is performed at 1000 ° C. for 2 minutes under an inert gas atmosphere and atmospheric pressure to form a source electrode 14 and a drain electrode 15 that are in ohmic contact with the source region 11 and the drain region 12, respectively (FIG. 1e).

  Thus, the silicon oxide film 9 is used as an implantation mask film for forming the source region and the drain region, and also used as a so-called lift-off mask film for forming the source electrode 14 and the drain electrode 15. The source region 11 and the source electrode 14, the drain region 12 and the drain electrode 15 can be formed in a self-aligned manner, and no positional deviation occurs. In addition, since impurity ions implanted into silicon carbide have a small diffusion coefficient, the source region and the source electrode, and the drain region and the drain electrode can be formed to substantially coincide with each other.

  Finally, a gate electrode 16 for controlling the current flowing through the channel layer 8 is formed between the source electrode 14 and the drain electrode 15 (FIG. 2). In the following, a field effect transistor can be completed by forming a surface protective film or the like in accordance with a normal field effect transistor manufacturing process.

  Next, a second embodiment will be described. In order to improve the high frequency characteristics of the field effect transistor described in the first embodiment, if the distance between the source electrode and the drain electrode is reduced to about 2 μm, the silicon oxide film 9 is deformed during the heat treatment for activation. May end up. Therefore, an embodiment suitable for a method of manufacturing a semiconductor device that is required to be miniaturized, such as a high-frequency field effect transistor, will be described.

First, as in the first embodiment, the photoresist 7 is patterned on the surface of the semi-insulating silicon carbide substrate 1 so as to open a field effect transistor formation region. Next, in order to form an n-type channel layer, an acceleration voltage and a dose amount of nitrogen ions in the opening are 170 eV · 2.8 × 10 ¹² atoms / cm ² and 125 eV · 1.8 × 10 ¹² atoms / cm, respectively. cm ² , 90 eV · 1.5 × 10 ¹² atoms / cm ² , 60 eV · 1.2 × 10 ¹² atoms / cm ² , 40 eV · 9.0 × 10 ¹¹ atoms / cm ² , 25 eV · 6.0 × 10 ¹¹ The injection is repeated 6 times under the condition of atom / cm ² . As a result, a channel region 8 having a depth of 300 nm and an impurity concentration of 3 × 10 ¹⁷ atoms / cm ³ is formed (FIG. 1a).

  After removing the photoresist 7, a silicon oxide film 9 is formed on the entire surface. The silicon oxide film 9 can be formed by chemical vapor deposition or sputtering. Next, in order to form a source region and a drain region, another photoresist 10 is patterned so as to open a source region and a drain region formation scheduled region on the surface of the silicon oxide film 9. Using the photoresist 10 as an etching mask, a part of the silicon oxide film 9 is removed by etching to form a recess 17 in which the silicon oxide film 9 is slightly left in the source region and drain region formation region (FIG. 3a). By leaving the silicon oxide film 9 on the bottom surface of the recess 17 in this way, the cross-sectional shape of the silicon oxide film 9 is not easily deformed even when a high-temperature heat treatment is performed. Therefore, in this embodiment, the silicon oxide film 9 is not deformed so that the cross-sectional shape of the silicon oxide film 9 is not deformed during the heat treatment for activating impurity ions implanted to form the source region and the drain region which will be described later. The recess 17 is formed while leaving a part. The thickness of the silicon oxide film 9 left on the bottom surface of the recess 17 may be set as appropriate. However, when the interval between the recesses 17 is about 2 μm, the silicon oxide film 9 having a thickness of about 50 nm is left at 1350 ° C. It has been confirmed that there is no problem even if heat treatment is performed for about 30 minutes.

After removing the photoresist 10, through the silicon oxide film 9 remaining in the recess 17, high-concentration n-type source and drain regions are formed, so that phosphorus ions are accelerated into the channel layer 8 at an acceleration voltage and a dose of 120 eV, respectively. The injection is repeated three times under the conditions of 2.0 × 10 ¹⁵ atoms / cm ² , 70 eV · 1.0 × 10 ¹⁵ atoms / cm ² , 40 eV · 5.0 × 10 ¹⁴ atoms / cm ² . Thereafter, heat treatment for activating the implanted impurity ions is performed. The heat treatment was performed at 1350 ° C. for 30 minutes under an inert gas atmosphere (for example, an argon gas atmosphere) and atmospheric pressure. By this heat treatment, the crystallinity of the ion-implanted layer can be restored and impurity ions can be activated, and the source region 11 and the drain region 12 are formed (FIG. 3b). In addition, it is necessary to perform the heat processing for activation in the temperature range of 1250 degreeC-1350 degreeC. Implanting impurity ions through the slightly remaining silicon oxide film 9 in this way has an advantage that the impurity concentration on the surface can be increased as compared with the case where impurity ions are implanted while exposing the surface of the channel layer 8.

  The silicon oxide film 9 remaining on the bottom surface of the recess 17 is removed to expose the source region 11 and the drain region 12 (FIG. 3c). Hereinafter, as described in the first embodiment, the entire surface is covered with the metal film 13 that forms ohmic contact with the high concentration n-type source region 11 and drain region 12 (FIG. 1d). As an example of the metal film, a nickel film is used. The silicon oxide film 9 is etched, and the silicon oxide film 9 is removed using a hydrofluoric acid solution which is an etchant that does not etch the nickel film. As a result, the metal film 13 on the silicon oxide film 9 is removed, and the metal film 13 is selectively left on the source region 11 and the drain electrode 12. Thereafter, heat treatment is performed at 1000 ° C. for 2 minutes under an inert gas atmosphere and atmospheric pressure to form a source electrode 14 and a drain electrode 15 that are in ohmic contact with the source region 11 and the drain region 12, respectively (FIG. 1e). In this embodiment, the impurity concentration on the surface of the source region 11 and the drain region 12 is formed high, and a good ohmic electrode having a low contact resistance can be formed.

  Thus, also in this embodiment, since the silicon oxide film 9 is used as an implantation mask film and also used as a mask film for forming the source electrode 14 and the drain electrode 15, the source region 11 and the source electrode 14, The drain region 12 and the drain electrode 15 can be formed in a self-aligned manner, and no positional deviation occurs. In addition, since impurity ions implanted into silicon carbide have a small diffusion coefficient, the source region and the source electrode, and the drain region and the drain electrode can be formed to substantially coincide with each other.

  Finally, a gate electrode 16 for controlling the current flowing through the channel layer 8 is formed between the source electrode 14 and the drain electrode 15 (FIG. 2). In the following, a field effect transistor can be completed by forming a surface protective film or the like in accordance with a normal field effect transistor manufacturing process.

  The field effect transistor formed in this manner has the advantage that the contact resistance between the source electrode and the drain electrode can be reduced, the current driving capability is increased, and the operation speed is higher in the high-frequency device characteristics.

  As mentioned above, although the Example of this invention was described, it cannot be overemphasized that this invention is not limited to this. For example, a p-type layer 18 can be formed under the channel layer 8 as shown in FIG. The p-type layer 18 can be formed by implanting aluminum ions or boron ions before implanting impurity ions for forming the channel layer 8.

  Further, an n-type or p-type substrate can be used in place of the semi-insulating substrate 1. In that case, needless to say, it is necessary to form a conductive region necessary for insulating the channel layer. Further, an epitaxial growth layer may be formed on the silicon carbide substrate, and the above-described channel layer or the like may be formed on this epitaxial growth layer.

It is a figure for demonstrating the 1st Example of this invention. It is a figure for demonstrating the Example of this invention. It is a figure for demonstrating the 2nd Example of this invention. It is a figure for demonstrating another Example of this invention. It is a figure for demonstrating the manufacturing method of this kind of conventional semiconductor device.

Explanation of symbols

1: substrate, 8: channel layer, 9: silicon oxide film, 11: source region, 12: drain region, 14: source electrode, 15: drain electrode, 16: gate electrode

Claims (2)

Preparing a semiconductor layer of one conductivity type made of a silicon carbide semiconductor;
Forming an oxide film on the semiconductor layer of one conductivity type;
Removing a part of the oxide film to expose the semiconductor layer of one conductivity type;
Implanting impurity ions into the exposed semiconductor layer, performing a heat treatment to activate the impurity ions, and forming a semiconductor region of one conductivity type having a higher impurity concentration than the semiconductor layer;
Covering the surface of the oxide film and the semiconductor region with a metal film that forms ohmic contact with the semiconductor region;
Etching the oxide film to remove the metal film on the oxide film, selectively forming the metal film on the semiconductor region, and forming an electrode in ohmic contact with the semiconductor region; The manufacturing method of the silicon carbide semiconductor device characterized by the above-mentioned. Preparing a semiconductor layer of one conductivity type composed of a silicon carbide semiconductor layer;
Forming an oxide film on the semiconductor layer of one conductivity type;
Removing a part of the oxide film in the ohmic electrode formation scheduled region spaced apart at a predetermined interval, and forming a recess;
Impurity ions are implanted into the one-conductivity-type semiconductor layer through the oxide film in the recess, and heat treatment is performed to activate the impurity ions, so that a one-conductivity-type semiconductor region having a higher impurity concentration than the semiconductor layer Forming, and
Removing the oxide film remaining in the recess and exposing the semiconductor region;
Covering the surface of the oxide film and the semiconductor region with a metal film that forms ohmic contact with the semiconductor region;
Etching the oxide film to remove the metal film on the oxide film, selectively forming the metal film on the semiconductor region, and forming the ohmic electrode;
Forming a Schottky electrode for forming a Schottky contact with the semiconductor layer on the semiconductor layer between the ohmic electrodes.

Images