JP2005268768A5 - - Google Patents

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JP2005268768A5
JP2005268768A5 JP2005039662A JP2005039662A JP2005268768A5 JP 2005268768 A5 JP2005268768 A5 JP 2005268768A5 JP 2005039662 A JP2005039662 A JP 2005039662A JP 2005039662 A JP2005039662 A JP 2005039662A JP 2005268768 A5 JP2005268768 A5 JP 2005268768A5
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circuit
central processing
memory
processing circuit
signal
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JP4776940B2 (en
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Claims (21)

イベント信号を生成する中央処理回路と、
前記イベント信号に基づき、前記中央処理回路に供給する電源電位とクロック周波数とを変更する情報を含む命令信号を生成する制御回路と、
アンテナを接続する接続端子と、を有することを特徴とする集積回路。 A central processing circuit for generating event signals;
And a control circuit based on said event signal, and generates a command signal that contains the information for changing the power supply potential and the clock frequency supplied to the central processing circuit,
An integrated circuit comprising a connection terminal for connecting an antenna. 請求項１において、前記イベント信号は、前記中央処理回路が含む整数演算ユニット、浮動小数点演算ユニット、ロード・ストアユニット若しくは分岐ユニットの動作状況の情報を含む信号、又は前記中央処理回路が含む複数のユニットに対する整数演算命令、浮動小数点演算命令、ロード命令、ストア命令、分岐命令若しくはＮＯＰ命令の実行状況の情報を含む信号、又は前記複数のユニットから選択された複数を含む組み合わせ回路が生成する信号、から選択された一つ若しくは複数であることを特徴とする集積回路。 2. The event signal according to claim 1, wherein the event signal includes a signal including information on an operation state of an integer arithmetic unit, a floating-point arithmetic unit, a load / store unit, or a branch unit included in the central processing circuit, or a plurality of the central processing circuit includes A signal including information on the execution status of an integer operation instruction, floating point operation instruction, load instruction, store instruction, branch instruction or NOP instruction for a unit, or a signal generated by a combinational circuit including a plurality selected from the plurality of units, An integrated circuit characterized by being one or more selected from: 中央処理回路と、
電源情報信号を生成する電源供給判定回路と、
前記電源情報信号に基づき、前記中央処理回路に供給する電源電位とクロック周波数とを変更する情報を含む命令信号を生成する制御回路と、
アンテナを接続する接続端子と、を有することを特徴とする集積回路。 A central processing circuit;
A power supply determination circuit for generating a power information signal;
Based on the power information signal, a control circuit for generating a command signal including information for changing the power supply potential and the clock frequency supplied to the central processing circuit,
An integrated circuit comprising a connection terminal for connecting an antenna. 請求項３において、前記電源供給判定回路は、負荷抵抗を含む電源回路と、参照電圧発生回路と、前記電源回路の出力電位と前記参照電圧発生回路の出力電位とを比較する比較回路と、を有することを特徴とする集積回路。 According to claim 3, wherein the power supply determination circuit includes a power supply circuit including a load resistor, a reference voltage generating circuit, a comparator circuit for comparing the output voltage of the output potential and the reference voltage generating circuit of the power supply circuit, the An integrated circuit comprising: メモリと、
メモリアクセス信号を生成する中央処理回路と、
前記メモリアクセス信号に基づき、前記メモリに供給する電源電位とクロック周波数とを変更する情報を含む命令信号を生成する制御回路と、
アンテナを接続する接続端子と、を有することを特徴とする集積回路。 Memory,
A central processing circuit for generating a memory access signal;
Based on the memory access signal, a control circuit for generating a command signal including information for changing the power supply potential and the clock frequency to be supplied to said memory,
An integrated circuit comprising a connection terminal for connecting an antenna. 請求項５において、前記メモリアクセス信号は、前記中央処理回路が含むメモリ制御ユニットの動作状況の情報を含む信号、又は前記中央処理回路のロード・ストア命令の実行状況の情報を含む信号、又は前記中央処理回路が含む複数のユニットから選択された複数を含む組み合わせ回路が生成する信号、から選択された一つ若しくは複数であることを特徴とする集積回路。 6. The memory access signal according to claim 5, wherein the memory access signal includes a signal including information on an operation status of a memory control unit included in the central processing circuit, a signal including information on an execution status of a load / store instruction of the central processing circuit, or the An integrated circuit comprising one or a plurality of signals selected from signals generated by a combinational circuit including a plurality selected from a plurality of units included in a central processing circuit. 請求項１乃至請求項４のいずれか１項において、前記制御回路は、前記中央処理回路の内部に設けられることを特徴とする集積回路。 5. The integrated circuit according to claim 1, wherein the control circuit is provided inside the central processing circuit. 6. 請求項５又は請求項６において、前記制御回路は、前記中央処理回路の内部又は前記メモリの内部に設けられることを特徴とする集積回路。 7. The integrated circuit according to claim 5, wherein the control circuit is provided in the central processing circuit or in the memory. 請求項５又は請求項６において、前記メモリは、ＳＲＡＭ（Ｓｔａｔｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）、ＤＲＡＭ（Ｄｙｎａｍｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）、ＥＥＰＲＯＭ（Ｅｌｅｃｔｒｉｃａｌｌｙ Ｅｒａｓａｂｌｅ Ｐｒｏｇｒａｍｍａｂｌｅ Ｒｅａｄ Ｏｎｌｙ Ｍｅｍｏｒｙ）及びフラッシュメモリから選択された一つ又は複数であることを特徴とする集積回路。 7. The memory according to claim 5, wherein the memory is an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), or a plurality of EEPROMs. An integrated circuit characterized by being. 請求項１乃至請求項９のいずれか１項に記載の前記集積回路は、ガラス基板上又はフレキシブル基板上に設けられることを特徴とする集積回路。 The integrated circuit according to any one of claims 1 to 9, wherein the integrated circuit is provided on a glass substrate or a flexible substrate. イベント信号を生成する中央処理回路と、
前記イベント信号に基づき、前記中央処理回路に供給する電源電位とクロック周波数とを変更する情報を含む命令信号を生成する制御回路と、
前記中央処理回路と前記制御回路とに電源供給を行うアンテナと、を有することを特徴とする半導体装置。 A central processing circuit for generating event signals;
And a control circuit based on said event signal, and generates a command signal that contains the information for changing the power supply potential and the clock frequency supplied to the central processing circuit,
Wherein a having an antenna for supplying power to said central processing circuit and the control circuit. 請求項１１において、前記イベント信号は、前記中央処理回路が含む整数演算ユニット、浮動小数点演算ユニット、ロード・ストアユニット若しくは分岐ユニットの動作状況の情報を含む信号、又は前記中央処理回路が含む複数のユニットに対する整数演算命令、浮動小数点演算命令、ロード命令、ストア命令、分岐命令若しくはＮＯＰ命令の実行状況の情報を含む信号、又は前記複数のユニットから選択された複数を含む組み合わせ回路が生成する信号、から選択された一つ若しくは複数であることを特徴とする半導体装置。 12. The event signal according to claim 11, wherein the event signal includes a signal including information on an operating state of an integer arithmetic unit, a floating point arithmetic unit, a load / store unit, or a branch unit included in the central processing circuit, or a plurality of the central processing circuit includes A signal including information on the execution status of an integer operation instruction, floating point operation instruction, load instruction, store instruction, branch instruction or NOP instruction for a unit, or a signal generated by a combinational circuit including a plurality selected from the plurality of units, One or a plurality of semiconductor devices selected from the above. 中央処理回路と、
電源情報信号を生成する電源供給判定回路と、
前記電源情報信号に基づき、前記中央処理回路に供給する電源電位とクロック周波数とを変更する情報を含む命令信号を生成する制御回路と、
前記中央処理回路と前記制御回路とに電源供給を行うアンテナと、を有することを特徴とする半導体装置。 A central processing circuit;
A power supply determination circuit for generating a power information signal;
Based on the power information signal, a control circuit for generating a command signal including information for changing the power supply potential and the clock frequency supplied to the central processing circuit,
Wherein a having an antenna for supplying power to said central processing circuit and the control circuit. 請求項１３において、前記電源供給判定回路は、負荷抵抗を含む電源回路と、参照電圧発生回路と、前記電源回路の出力電位と前記参照電圧発生回路の出力電位とを比較する比較回路と、を有することを特徴とする半導体装置。 According to claim 13, wherein the power supply determination circuit includes a power supply circuit including a load resistor, a reference voltage generating circuit, a comparator circuit for comparing the output voltage of the output potential and the reference voltage generating circuit of the power supply circuit, the A semiconductor device comprising: メモリと、
メモリアクセス信号を生成する中央処理回路と、
前記メモリアクセス信号に基づき、前記メモリに供給する電源電位とクロック周波数とを変更する情報を含む命令信号を生成する制御回路と、
前記メモリと前記中央処理回路と前記制御回路とに電源供給を行うアンテナと、を有することを特徴とする半導体装置。 Memory,
A central processing circuit for generating a memory access signal;
Based on the memory access signal, a control circuit for generating a command signal including information for changing the power supply potential and the clock frequency to be supplied to said memory,
Wherein a having an antenna for supplying power to said memory and said central processing circuit and the control circuit. 請求項１５において、前記メモリアクセス信号は、前記中央処理回路が含むメモリ制御ユニットの動作状況の情報を含む信号、又は前記中央処理回路のロード・ストア命令の実行状況の情報を含む信号、又は前記中央処理回路が含む複数のユニットから選択された複数を含む組み合わせ回路が生成する信号、から選択された一つ若しくは複数であることを特徴とする半導体装置。 16. The memory access signal according to claim 15, wherein the memory access signal includes a signal including information on an operation status of a memory control unit included in the central processing circuit, a signal including information on an execution status of a load / store instruction of the central processing circuit, or the A semiconductor device comprising one or a plurality of signals selected from signals generated by a combinational circuit including a plurality selected from a plurality of units included in a central processing circuit. 請求項１１乃至請求項１４のいずれか１項において、前記制御回路は、前記中央処理回路の内部に設けられることを特徴とする半導体装置。 15. The semiconductor device according to claim 11, wherein the control circuit is provided inside the central processing circuit. 請求項１５又は請求項１６において、前記制御回路は、前記中央処理回路の内部又は前記メモリの内部に設けられることを特徴とする半導体装置。 17. The semiconductor device according to claim 15, wherein the control circuit is provided in the central processing circuit or in the memory. 請求項１５又は請求項１６において、前記メモリは、ＳＲＡＭ（Ｓｔａｔｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）、ＤＲＡＭ（Ｄｙｎａｍｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）、ＥＥＰＲＯＭ（Ｅｌｅｃｔｒｉｃａｌｌｙ Ｅｒａｓａｂｌｅ Ｐｒｏｇｒａｍｍａｂｌｅ Ｒｅａｄ Ｏｎｌｙ Ｍｅｍｏｒｙ）及びフラッシュメモリから選択された一つ又は複数であることを特徴とする半導体装置。 17. The memory according to claim 15 or 16, wherein the memory is an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory) or a plurality of EEPROMs. There is a semiconductor device. 請求項１１乃至請求項１９のいずれか１項に記載の前記半導体装置は、ガラス基板上又はフレキシブル基板上に設けられることを特徴とする半導体装置。 The semiconductor device according to claim 11, wherein the semiconductor device is provided on a glass substrate or a flexible substrate. 請求項１乃至請求項１０のいずれか１項に記載の前記集積回路、又は請求項１１乃至請求項２０のいずれか一項に記載の前記半導体装置が組み込まれることを特徴とする無線チップ。
A wireless chip in which the integrated circuit according to any one of claims 1 to 10 or the semiconductor device according to any one of claims 11 to 20 is incorporated.
JP2005039662A 2004-02-20 2005-02-16 Integrated circuit, semiconductor device, and wireless chip Expired - Fee Related JP4776940B2 (en)

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JP2007199895A (en) * 2006-01-25 2007-08-09 Sony Corp Data processor for proximity communication
JP4945224B2 (en) * 2006-11-30 2012-06-06 株式会社東芝 Controller, information processing apparatus, and supply voltage control method
KR100853190B1 (en) 2006-12-08 2008-08-20 한국전자통신연구원 Apparatus for managing power of passive tag and method thereof
KR100853189B1 (en) 2006-12-08 2008-08-20 한국전자통신연구원 Low-powered Radio Frequency Identification Tag and the method for long tag life
JP2011197870A (en) * 2010-03-18 2011-10-06 Mitsubishi Electric Corp Programmable device mounting apparatus
KR101685389B1 (en) 2010-10-08 2016-12-20 삼성전자주식회사 Smart Card

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JP3878431B2 (en) * 2000-06-16 2007-02-07 株式会社ルネサステクノロジ Semiconductor integrated circuit device
JP3877518B2 (en) * 2000-12-13 2007-02-07 松下電器産業株式会社 Processor power control device
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