JP2005244212A5 - - Google Patents

Claims (9)

Threshold control signal for one or both of the logic unit and the memory unit based on the detection result of the logic unit, the memory unit, the detection unit for detecting the operation frequency of one or both of the logic unit and the memory unit A threshold control unit and an antenna for supplying
Each of the logic unit and the memory unit includes a plurality of transistors,
Each of the plurality of transistors includes a first gate electrode to which a logic signal is input and a second gate electrode to which the threshold control signal is input. Threshold control signal for one or both of the logic unit and the memory unit based on the detection result of the logic unit, the memory unit, the detection unit for detecting the operation frequency of one or both of the logic unit and the memory unit A threshold control unit and an antenna for supplying
Each of the logic unit and the memory unit includes a plurality of transistors,
Each of the plurality of transistors includes a first gate electrode to which a logic signal is input, a second gate electrode to which the threshold control signal is input, and a semiconductor film,
The semiconductor film is provided on the second gate electrode;
The semiconductor device, wherein the first gate electrode is provided on the semiconductor film. In claim 1 or claim 2,
2. The semiconductor device according to claim 1, wherein the logic unit includes a plurality selected from a control circuit, an arithmetic circuit, an input / output circuit, a power supply circuit, a clock generation circuit, a data demodulation / modulation circuit, and an interface circuit. In claim 1 or claim 2,
The logic unit includes a timing control, an instruction decoder, a register array, an address logic and buffer, a data bus interface, an ALU (Arthematic Logic Unit), and an instruction register. In any one of Claims 1 thru | or 4 ,
The memory unit, DRAM (DynamicRandomAccessMemory), SRAM (StaticRandomAccessMemory), FeRAM (FerroelectricRandomAccessMemory), mask ROM (Read Only), the fuse-type PROM (ProgrammableReadOnlyMemory), anti-fuse type PROM, EPROM (ElectricallyProgrammableReadOnlyMemory), EEPROM (ElectricallyErasableProgrammableReadOnlyMemory) and flash memory A semiconductor device comprising one or more selected from the above. In any one of Claims 1 thru | or 5 ,
The semiconductor device, wherein the detection unit is a program or a storage medium that stores the program. In any one of Claims 1 thru | or 6 ,
The plurality of transistors are provided on a substrate;
The semiconductor device is characterized in that the substrate is a glass substrate or a flexible substrate. In any one of Claims 1 thru | or 6 ,
The plurality of transistors and the antenna are provided on the same substrate,
The semiconductor device is characterized in that the substrate is a glass substrate or a flexible substrate. In any one of Claims 1 thru | or 6 ,
The plurality of transistors are provided on a first substrate;
The antenna is provided on a second substrate;
Wherein the first substrate and the second substrate, wherein a said plurality of transistors and said antenna so as to be electrically connected, are fixed.