JP2005268768A - Integrated circuit, semiconductor device, and radio chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a noncontact type semiconductor device which realizes a low power consumption and stably conducts radio communications. <P>SOLUTION: The semiconductor device monitors the power feed condition and the operating condition of blocks in an ID chip from a reader/writer, to select and feed clock signals of an adequate frequency and power voltages, according to these conditions. This realizes an operation mode, suited to the power feed condition or a low power consumption mode fit to the operating condition of each block, thereby cutting down on the power consumption of the ID chip and stabilizing radio communication. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to an integrated circuit, a semiconductor device, and an ID chip formed on a glass substrate or a flexible substrate. Further, the present invention relates to an integrated circuit, a semiconductor device, and an ID chip that perform contactless communication.

In recent years, for purposes such as ID management of securities and payment processing using electronic money, contactless IC cards, ID tags, RFIDs, etc. having high security functions (hereinafter collectively referred to as ID chips) ) Is growing. Such an ID chip incorporates an integrated circuit having a high function such as a central processing circuit (in many cases, a central processing unit, which may be abbreviated as a CPU hereinafter) and dedicated hardware for performing cryptographic processing. ing.

The ID chip supplies power mainly by an induced electromotive current generated by electromagnetic induction between an electromagnetic wave transmitted from a reader / writer and an antenna in the ID chip. However, in such a system, when the positional relationship between the operating ID chip and the reader / writer changes, the amount of power supplied to the ID chip changes, and it is difficult to stabilize the power supply.

In addition, since the CPU and the logic circuit for cryptographic processing have a large circuit area, they consume a large amount of power. If the power supply is unstable and the power consumption is large, the operation margin is reduced, so that stable operation cannot be performed. In addition, if the circuit area is large, the impact resistance of the semiconductor device is inferior, and the number of chips on the silicon wafer is reduced, leading to high prices.

Accordingly, it is an object of the present invention to provide an integrated circuit, a semiconductor device, and an ID chip that can operate stably by suppressing power consumption as much as possible, and that are inexpensive and excellent in impact resistance even when the circuit area is large. To do.

The present invention provides a central processing circuit, an integrated circuit having a control circuit, and a semiconductor device. The power supply circuit generates a plurality of power supply potentials, and the clock generation circuit generates clock signals having different frequencies. The control circuit determines the operation status of the central processing circuit and memory and the status of the amount of power supplied from the outside, and supplies a power supply with an appropriate potential and a clock with an appropriate frequency to the central processing circuit. And control the clock generation circuit.
The present invention also provides an integrated circuit including a central processing circuit, a control circuit, and a connection terminal for connecting an antenna. Furthermore, the present invention provides a semiconductor device including a central processing circuit, a control circuit, and an antenna. The present invention also provides an ID chip (also referred to as a wireless chip) in which an integrated circuit or a semiconductor device is incorporated.

The control circuit judges the operation status of the central processing circuit, and reduces the clock frequency and the power supply voltage if the load on the central processing circuit is small, and increases the clock frequency and the power supply voltage if the load on the central processing circuit is large. Thus, the power supply circuit and the clock generation circuit are controlled. Thus, by performing control according to the operation status of the central processing circuit, it is possible to reduce power consumption as much as possible.
More specifically, the control circuit controls the power supply circuit and the clock generation circuit based on the event signal generated by the central processing circuit. The event signal is an integer arithmetic unit included in the central processing circuit, a floating point arithmetic unit, a signal including information on the operation status of the load / store unit or the branch unit, or an integer arithmetic instruction for a plurality of units included in the central processing circuit, floating One or more selected from a signal including information on the execution status of a decimal point operation instruction, a load instruction, a store instruction, a branch instruction or a NOP instruction, or a signal generated by a combinational circuit including a plurality selected from a plurality of units It corresponds to.

Also, the control circuit judges the power supply status from the reader / writer to the semiconductor device. If the power supply amount is small, the clock frequency and the power supply voltage are reduced, and if the power supply amount is large, the clock frequency and the power supply voltage are increased. The power supply circuit and the clock generation circuit are controlled so that As described above, by performing control in accordance with the power supply amount from the reader / writer to the semiconductor device, stable operation can be performed even with unstable power supply. Of course, the power supply voltage and clock frequency to be controlled are set within a range where the central processing circuit can operate.
More specifically, the integrated circuit and the semiconductor device of the present invention have a power supply determination circuit that generates a power supply information signal. The control circuit controls the power supply circuit and the clock generation circuit based on the power supply information signal. The power supply determination circuit includes a power supply circuit including a load resistor, a reference potential generation circuit, and a comparison circuit that compares the output potential of the power supply circuit with the output potential of the reference potential generation circuit.

Further, the control circuit may switch not only the central processing circuit but also the power supply potential and clock signal supplied to other integrated circuits. For example, a memory incorporated in a semiconductor device (for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), an electrically erasable programmable memory (EEPROM), or a plurality of EEPROMs) However, it is possible to adopt a configuration capable of supplying a clock signal having a multi-stage frequency and a power supply voltage.
More specifically, the control circuit controls the power supply circuit and the clock generation circuit based on the memory access signal generated by the central processing circuit. The memory access signal is a signal including information on the operation status of the memory control unit included in the central processing circuit, a signal including information on the execution status of the load / store instruction of the central processing circuit, or a plurality of units included in the central processing circuit. It corresponds to one or a plurality of signals selected from signals generated by a combinational circuit including a plurality of selected ones.

The present invention also provides an integrated circuit and a semiconductor device that are formed in large quantities on a glass substrate that is larger and less expensive than a silicon wafer, and that suppresses a high price. Furthermore, a semiconductor device is provided in which impact resistance is improved by peeling an element group on a glass substrate and attaching the element group to a flexible substrate. Here, since the element group peeled from the glass substrate has a thickness of 5 μm or less (preferably 0.1 to 3 μm), it is directly attached to a product container or a tag, or the periphery is made of an organic resin material or the like. Can be filled.

A flexible substrate refers to a substrate having flexibility, and typically includes a plastic substrate, paper, and the like in its category. Examples of plastics include polynorbornene with a polar group, polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), polysulfone ( PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide and the like.

According to the present invention, a semiconductor device that is inexpensive and excellent in impact resistance can be provided. If it is excellent in impact resistance, it can be used for various purposes, and if it is inexpensive, it can be used for many products and articles.

Furthermore, according to the present invention, power consumption can be reduced, and a semiconductor device that operates stably with a wide operation margin can be provided. Therefore, the reliability of the semiconductor device can be improved, and the reliability of many products and articles using the semiconductor device of the present invention can be improved.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in common in different drawings, and description thereof is not repeated.
(Embodiment 1)

The structure of the semiconductor device 101 of the present invention will be described with reference to FIG. The semiconductor device 101 includes an integrated circuit 111 and an antenna 102. The integrated circuit 111 includes a power supply circuit 103, a clock generation circuit 104, a data demodulation modulation circuit 105 including a function for demodulating / modulating data, a control circuit 106, and a circuit for determining a power supply level (abbreviated as a power supply determination circuit). 114, a CPU 107, an interface (indicated as IF in the drawing) 108, a nonvolatile memory (indicated in the drawing as NVM) 109, and an SRAM 110. Instead of the SRAM 110, a volatile memory such as a DRAM may be used.

The integrated circuit 111 is formed on a glass substrate or a flexible substrate. The antenna 102 may be formed on the same substrate as the integrated circuit 111 in the semiconductor device 101, or may be formed in a protective layer disposed on the upper or lower portion of the integrated circuit 111. As described above, when the antenna 102 is formed over the same substrate as the integrated circuit 111, a method of forming a composition using nanoparticles by a printing method (a droplet ejection method or a screen printing method) can also be used.

In the semiconductor device 101, the integrated circuit 111 provided with a connection terminal to the antenna 102 and the antenna 102 made of copper, aluminum, or the like may be electrically connected using an anisotropic conductive film or the like. Here, a device that includes the antenna 102 and the integrated circuit 111 and can communicate with a reader / writer is referred to as a semiconductor device 101. A circuit that has a connection terminal with the antenna 102 but does not have the antenna 102 is referred to as an integrated circuit 111.

The size of the integrated circuit 111 is 5 mm square or less, and preferably has an area of 0.3 mm to 4 mm square, and the protective layer disposed above or below the integrated circuit 111 is larger than the size of the semiconductor device 101. .

The control circuit 106 receives the power information signal 112 generated by the circuit 114 for determining the power supply level and the event signal 113 generated by the CPU 107. Then, it generates a command signal for changing the power supply Vddc and clock signal CLKc supplied to the CPU 107, and the power supply Vdds and clock signal CLKs supplied to the system other than the CPU 107 to ones suitable for the power supply level. Transmit to circuit 104. The power supply circuit 103 and the clock generation circuit 104 receive a signal from the control circuit 106 and change Vddc and CLKc supplied to the CPU 107 and Vdds and CLKs supplied to a system other than the CPU 107.
That is, the control circuit 106 generates a command signal including information for changing the power supply potential and the clock frequency supplied to the CPU 107 based on the event signal 113 generated by the CPU 107, and outputs the command signal to the power supply circuit 103 and the clock generation circuit 104. To supply.

The power supply circuit 103 can generate 2 to 100 steps of power supply potential according to a signal from the control circuit 106, and the clock generation circuit 104 can similarly generate a clock frequency of 2 to 100 steps according to a signal from the control circuit 106. The configuration.

The circuit 114 for determining the power supply level can generate the power supply information signal 112 by providing a small-scale power supply circuit separately from the power supply circuit 103 and monitoring the stability of the power supply.
Specifically, when the amount of power supplied from the outside is large and the internal power supply is stable, the power supply potential and the clock frequency supplied to the CPU 107 and the system other than the CPU 107 are increased to improve the processing speed of the semiconductor device 101. . On the other hand, when the amount of power supplied from the outside is small or the internal power supply is unstable, the power supply potential and the clock frequency supplied to the system other than the CPU 107 and the CPU 107 are decreased to suppress the power consumption of the semiconductor device 101.

The control circuit 106 receives from the CPU 107 an event signal 113 indicating an internal operating state of the CPU 107. Then, every certain period (typically 10 μs to 100 ms), a signal for changing the power supply voltage and the clock frequency is generated so that the load on the CPU 107 becomes almost the same as the operation of the other system. The data is transmitted to the circuit 103 and the clock generation circuit 104. The power supply circuit 103 and the clock generation circuit 104 receive a signal from the control circuit 106 and change Vddc and CLKc supplied to the CPU 107 and Vdds and CLKs supplied to a system other than the CPU 107.
In other words, the control circuit 106 generates a command signal including information for changing the power supply potential and the clock frequency supplied to the CPU 107 based on the power supply information signal 112 generated by the circuit 114 for determining the power supply level. The power is supplied to the power supply circuit 103 and the clock generation circuit 104.

The event signal 113 is a signal representing various events inside the CPU 107. The CPU 107 has a plurality of units. The units constituting the plurality of units are pipeline units such as an integer arithmetic unit, a floating point arithmetic unit, a load / store unit, and a branch unit. The event signal is a signal indicating an event in which each of the plurality of units included in the CPU 107 is operated, a signal indicating an event in which each instruction such as a NOP instruction, a load / store instruction, an arithmetic instruction is executed, Alternatively, a signal generated by a combinational circuit including a plurality selected from a plurality of units included in the CPU 107 can be used.
For example, if the number of operations of the CPU 107 and the number of hits to the cache are large, the power supply potential supplied to the CPU 107 and the clock frequency are increased. Conversely, when the CPU 107 has a large number of NOP instructions, when the wait time is long, or when the number of operations is small, power consumption is reduced by reducing the power supply potential and the clock frequency supplied to the CPU 107.

Note that when changing the power supply potential and the clock frequency, it is preferable to change the values stepwise. By changing the power supply voltage and the clock frequency in stages, it is possible to reduce the time required for restarting the operation and to reduce the possibility of hindering the operation.

Further, the relationship between the power supply potential and the clock frequency is preferably selected so as to be the highest clock frequency that operates at the selected power supply potential. Further, the power supply potential and the clock frequency are changed within a range in which the operation of the integrated circuit 111 is guaranteed. In particular, when the power supply level is very low, a method of stopping the power supply can be adopted.

In this embodiment, the CPU 107 and the system other than the CPU 107 are configured to control the two power supply potentials and the clock frequency. However, only the CPU 107 may control the power supply potential and the clock frequency. In particular, when the power consumed by the CPU 107 occupies most of the system, it is effective because the scale of the control circuit 106 can be reduced.

With the function of the control circuit 106 as described above, the semiconductor device 101 can always perform processing according to the amount of power supplied from the outside. Furthermore, it is possible to suppress the waste of power consumption as much as possible when the CPU 107 wastes processing power. As a result, the power consumption of the semiconductor device 101 can be suppressed and a stable operation can be performed even if the amount of power supply is small, so that the communicable distance with the reader / writer and the operation margin can be improved.
(Embodiment 2)

The structure of the semiconductor device 101 of the present invention will be described with reference to FIG. In this embodiment mode, the control circuit 106 controls a memory such as SRAM or NVM in addition to the CPU 107.

Although the semiconductor device 101 is partially different in control signal, power supply, and clock signal, the components are the same as those of the semiconductor device 101 shown in FIG. The main difference from the semiconductor device 101 shown in FIG. 1 is that the power and clock signal supplied to each memory (NVM 109 and SRAM 110) are controlled by the control circuit 106, and the control circuit 106 has a power information signal 112 and an event signal 113. In addition, the memory access signal 115 is received.

The semiconductor device 101 of this embodiment sets the operation mode of the power supply and the clock signal corresponding to the operation state of the memory. And by controlling the operation mode according to the operation state for each memory, the power consumption can be reduced without reducing the processing capacity of the system.

When the non-volatile memory (NVM 109) is mounted on the semiconductor device 101, for example, three modes of a read mode, a write mode, and a standby mode are set. Non-volatile memories include EPROM, EEPROM, flash memory, ferroelectric memory (FRAM, FeRAM), magnetic memory (Magnetic RAM, MRAM), phase change memory (PRAM, OUM), and the like. In general, the NVM 109 has many read operations, requires a relatively large current at the time of writing, and does not lose data even when the power of the memory cell or the decoder is turned off during standby, so such a form is preferable. .

Specifically, the control circuit 106 determines which mode the NVM 109 is to be set for every predetermined period based on the memory access signal 115 from the CPU 107. Then, a signal for changing the power supply potential and the clock frequency is generated and transmitted to the power supply circuit 103 and the clock generation circuit 104. The power supply circuit 103 and the clock generation circuit 104 receive the signal from the control circuit 106, change the power supply and clock signal supplied to the NVM 109, and shift to each operation mode.
In other words, the control circuit 106 generates a command signal including information for changing the power supply potential and the clock frequency supplied to the NVM 109 based on the memory access signal 115 generated by the CPU 107 and supplies the command signal to the NVM 109.

When the SRAM 110 is mounted in the semiconductor device 101, for example, two operation modes, a normal mode and a standby mode, are set. Since the SRAM 110 is volatile, the power supply cannot be stopped even in the standby mode. However, power consumption can be reduced by reducing the power supply potential within a range in which information of the memory cell can be held. A DRAM may be used instead of the SRAM.
Specifically, the control circuit 106 determines which mode the SRAM 110 is to be set for every predetermined period based on the memory access signal 115 from the CPU 107. Then, a signal for changing the power supply potential and the clock frequency is generated and transmitted to the power supply circuit 103 and the clock generation circuit 104. The power supply circuit 103 and the clock generation circuit 104 receive a signal from the control circuit 106, change the power supply and clock signal supplied to the SRAM 110, and shift to each operation mode.

Next, the memory access signal 115 and operation mode selection will be described. The memory access signal 115 is generated by the CPU 107 that controls access to the memory. As the memory access signal 115, for example, a signal indicating that a load / store instruction to the NVM 109 or the SRAM 110 is executed, an interface setting of the NVM 109 or the SRAM 110, or a signal generated by a combination circuit thereof is used. Can do.

The control circuit 106 preferably does not change the operation mode every time the CPU 107 accesses the memory, but typically changes the operation mode in a period of several hundred to several tens of thousands of cycles.

For example, the control circuit 106 counts the number of accesses to each memory for a certain period. If the number of accesses is small, it is determined that there is no access to the memory for the time being, and the memory can be shifted to the standby mode. Alternatively, if it is determined programmatically that a certain memory is not used, the memory can be shifted to the standby mode.

When the memory in the standby mode is accessed unintentionally, for example, the CPU 107 is informed that the memory is in the standby mode. Specifically, when there is an access to the memory in the standby mode, the CPU 107 is interrupted to stop the memory access and wait. In parallel, the memory is returned to a desired mode, and access is resumed after the return. Alternatively, the CPU 107 grasps whether or not the memory to be accessed is in the standby mode. If the memory is in the standby mode, the access instruction is stopped, and the processing is performed by first returning the memory to the desired mode. May be.

As described above, the power consumption can be reduced without lowering the processing capability of the system by individually setting the unused memory to the standby mode. As for the control of the power supply voltage and the clock signal supplied to the CPU 107 described in Embodiment Mode 1, the operation mode can be set and switched by the control circuit 106 as in the case of the memory control.

In this example, a structure different from that of the above embodiment of a power supply circuit, a clock generation circuit, and a control circuit for generating a power supply voltage will be described with reference to FIGS. 3 to 5, the same symbols are assigned to the same circuits and signals as those in FIG. 1.

First, an example in which a control circuit is provided inside each block of the CPU, NVM, and SRAM will be described with reference to FIG.

When there are control circuits in the CPU 107, NVM 109, and SRAM 110, each control circuit receives the power supply information signal 112. Then, the control circuit generates a command signal for changing the power supply voltage and the clock frequency to values matching the power supply level within a range in which the total power consumption of each block does not exceed the power supply amount. The data is transmitted to the circuit 103 and the clock generation circuit 104. The power supply circuit 103 and the clock generation circuit 104 receive signals from the control circuit and change the power supply voltage and clock signal supplied to each block.

Note that the power supply circuit 103 generates multistage power supply voltages, and the clock generation circuit 104 generates multistage frequency clock signals.

When the control circuit in the CPU 107 receives the event signal 113 from the CPU core and determines that the load on the CPU 107 is large at regular intervals, the power supply potential and the clock frequency supplied to the CPU 107 are increased step by step. If it is determined that the load on the CPU 107 is small, a command signal is transmitted to the power supply circuit 103 and the clock generation circuit 104 so that the power supply potential and the clock frequency are decreased stepwise.

A control circuit in the NVM 109 or the SRAM 110 receives the memory access signal 115 from the CPU 107. Then, as described in the embodiment, an optimum operation mode for each memory is determined every fixed period, and a command signal is transmitted to the power supply circuit 103 and the clock generation circuit 104.

Next, the provision of a power supply circuit and a clock circuit inside the CPU and the memory will be described with reference to FIG.

When the CPU 107, the NVM 109, and the SRAM 110 have a power supply circuit and a clock circuit, the power supply circuit 103 and the clock generation circuit 104 generate several basic power supplies and clock signals, and the power supply circuit and clock generation circuit in each block Generate multi-stage power and clock signals.

The control circuit 106 receives the power supply information signal 112, determines the operation mode of each block so that the total power consumption amount of each block does not exceed the power supply amount, and sends a command signal to the power supply circuit 103 and the clock generation circuit 104. Send. Alternatively, the event signal 113 and the memory access signal 115 are received from the CPU, the operation mode of each block is determined, and a command signal is transmitted to the power supply circuit 103 and the clock generation circuit 104.

Next, an example in which the control circuit, the power generation circuit, and the clock circuit are provided in the CPU and the memory will be described with reference to FIG.

When there are a control circuit, a power supply circuit, and a clock circuit in the CPU 107, NVM 109, and SRAM 110, the power supply circuit 103 and the clock generation circuit 104 generate several basic types of power supply and clock signals, and the power supply circuit 103 in each block. The clock generation circuit 104 generates multistage power supplies and clock signals.

A control circuit inside the CPU receives a power information signal 112 indicating the power supply status from the antenna 102 and an event signal 113 from the CPU core. Then, a command signal is transmitted to the power supply circuit and the clock generation circuit so as to change the operation mode according to the power supply level and the operation status of the CPU. The control circuits in the NVM 109 and the SRAM 110 receive the power information signal 112 and the memory access signal 115 from the CPU core, and change the operation mode of each memory.

By providing the control circuit in the CPU or the memory as in this embodiment, the distance to the controlled object is reduced, and the operating frequency margin can be improved in controlling the operation mode. Further, by providing the power generation circuit and the clock circuit inside the CPU and the memory, it becomes possible to generate a power supply voltage and a clock frequency that are optimal for the operation of each part.

In this embodiment, an example of a circuit for determining a power supply level will be described with reference to FIG.

The circuit shown in FIG. 6 is an example, and a signal from an antenna is input. A medium-scale power supply circuit 601 that generates a power supply for operating this circuit, a plurality of small-scale power supply circuits 602 (1) to 602 (n), a plurality of resistors 603 (1) to 603 (n), A reference potential generation circuit 604 and a comparison circuit 605 are provided.

In the figure, C is a capacitor, D is a diode, B is an analog buffer, and SA is a differential amplifier.

The power generation circuit is composed of a diode and a capacitor. The reference potential generation circuit 604 has a configuration in which Vref is generated by resistance division, amplified by an analog buffer, and output. The comparison circuit 605 is a circuit that compares two analog potentials using a differential amplifier.

In this circuit, first, a plurality of potentials V with a voltage drop are generated by connecting a power supply generated in a small-scale power supply circuit 602 and GND via a resistor 603. Then, the potential V is compared with the common reference potential Vref by the comparison circuit 605. The result is output as a digital signal that conveys information on the power supply level.

The plurality of potentials V1 to Vn are analog potentials determined by the power supply capability of the power supply circuit and the current consumption by the resistor. For example, when n = 3 and the parameters of each circuit are appropriately selected so that V1> V2> V3, the power supply levels are (1, 1, 1), (1, 1, 0), (1 , 0, 0) and (0, 0, 0). That is, when the power supply level is high, the voltage drop due to the resistance is small, and V1 to V3 are all higher than Vref and (1, 1, 1) is output. On the other hand, when the power supply level is low, the voltage drop due to the resistance is large, and V1 to V3 are all at a potential lower than Vref, and (0, 0, 0) is output.

Note that the medium-scale power supply circuit 601 has a power supply capability that can stably operate the circuit even when the power supply level is low.

The power supply information signal generation circuit is not limited to the circuit shown in FIG. 6, and may be configured using a known power supply generation circuit, potential generation circuit, or comparison circuit. Alternatively, the power supply level may be determined by generating a plurality of reference potentials and comparing them with a single potential V that has been dropped.

In this embodiment, a usage example of the semiconductor device of the present invention will be described. As the semiconductor device shown in this embodiment, a semiconductor device manufactured on a glass substrate may be used, or a semiconductor device transferred onto a flexible substrate may be used in consideration of impact resistance and the like.

Since the semiconductor device of the present invention incorporates an integrated circuit having a high function such as a CPU and dedicated hardware for performing cryptographic processing, and can stably communicate over a wide range with low power consumption, For the purpose of ensuring security, semiconductor devices can be mounted on various articles. Specifically, security means prevention of theft or counterfeiting.

As an example of theft prevention, a case where an ID chip is mounted on a product will be described. For example, as shown in FIG. 7A, an ID chip 702 is mounted on a part of the bottom or side surface of the bag 701 or the like.

Since the ID chip 702 is very thin and small, it can be mounted without degrading the design of the bag 701. In addition, since the ID chip 702 has translucency and it is difficult to determine the presence / absence of the ID chip 702 and the mounting location, the ID chip 702 is not likely to be removed by a thief. In addition to bags, ID chips can be mounted on various products such as vehicles such as automobiles and bicycles, watches and accessories.

Furthermore, when a product on which such an ID chip is mounted is stolen, information on the current position of the product can be obtained using, for example, GPS (Global Positioning System). Further, in addition to the stolen article, information on the current position can be obtained using GPS for forgotten items and lost items. Note that GPS is a system that captures a signal sent from a GPS satellite, obtains a time difference thereof, and estimates a position based on the time difference.

Next, as an example of forgery prevention, a case where an ID chip is mounted on a passport or a driver's license will be described.

FIG. 7B illustrates an example in which an ID chip 704 is mounted on the passport 703. In FIG. 7B, the ID chip 704 is mounted on the cover of the passport 703; however, the ID chip 704 may be mounted on another page. The ID chip 704 may be mounted on the surface because it has translucency. Further, the ID chip 704 may be sandwiched between materials such as a cover and mounted inside the cover.

FIG. 7C shows an example in which an ID chip 706 is mounted on the license 705. In FIG. 7C, the ID chip 706 is mounted inside the license 705, but the ID chip 706 may be provided on the printing surface of the license 705 because it has a light-transmitting property. For example, the ID chip 706 can be mounted on the printing surface of the license 705 and covered with a laminate. In addition, the ID chip 706 can be sandwiched between the materials of the license 705 and mounted inside. Since the ID chip is very small and thin, the design of the passport, license, product, etc. is not impaired.

Forgery can be prevented by mounting the ID chip on the article as described above. In addition, a rare and expensive ID chip such as the above-described bag can be mounted to prevent forgery.

Further, by incorporating an ID chip, it is possible to easily manage passports, licenses, products, and the like. In particular, since input items such as a passport and a license can be saved in a memory in the ID chip, privacy can be protected.

In this embodiment, a specific method for manufacturing a thin film integrated circuit device including a TFT will be described with reference to FIGS. TFT is an abbreviation for Thin Film Transistor and refers to a thin film transistor formed on glass or the like. Here, for the sake of simplicity, a manufacturing method thereof will be described by showing cross-sectional structures of an n-type TFT and a p-type TFT.

First, the separation layer 802 is formed over the substrate 801 (FIG. 8A). Here, an a-Si film (amorphous silicon film) having a thickness of 50 nm (500 mm) was formed on a glass substrate (for example, a 1737 substrate manufactured by Corning) by a low pressure CVD method. As the substrate, in addition to a glass substrate, a quartz substrate, a substrate formed of an insulating material such as alumina, a silicon wafer substrate, a plastic substrate having heat resistance that can withstand a processing temperature in a later process, or the like can be used. .

In addition to the amorphous silicon, the release layer may be a film containing silicon as a main component, such as polycrystalline silicon, single crystal silicon, or SAS (semi-amorphous silicon (also referred to as microcrystalline silicon or microcrystalline silicon)). Although it is desirable to use, it is not limited to these. The peeling layer may be formed by a plasma CVD method, a sputtering method, or the like in addition to the low pressure CVD method. Alternatively, a film doped with an impurity such as phosphorus may be used. Further, the thickness of the release layer is desirably 50 to 60 nm. Regarding SAS, it is good also as 30-50 nm.

Next, a protective film 803 (also referred to as a base film or a base insulating film) is formed over the separation layer 802 (FIG. 8A). Here, a three-layer structure of a SiON film with a thickness of 100 nm / a SiNO film with a thickness of 50 nm / a SiON film with a thickness of 100 nm is used. However, the material, the film thickness, and the number of stacked layers are not limited thereto. For example, instead of the lower SiON film, a heat-resistant resin such as siloxane having a film thickness of 0.5 to 3 μm may be formed by a spin coat method, a slit coater method, a droplet discharge method, or the like. Further, a silicon nitride film (SiN, Si ₃ N ₄ or the like) may be used. Siloxane refers to a substance having a skeletal structure composed of a bond of silicon (Si) and oxygen (O) and having at least one of hydrogen, fluorine, an alkyl group, and aromatic hydrocarbon as a substituent. . Each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

Like the protective film 803, the protective film in contact with the lower portion of the TFT and the protective film in contact with the upper portion of the TFT are preferably formed of a substance such as silicon oxide or silicon nitride that blocks alkali metal.

Here, the silicon oxide film may be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, or bias ECRCVD using a mixed gas such as SiH ₄ / O ₂ , TEOS (tetraethoxysilane) / O _2, or the like. it can. The silicon nitride film can be typically formed by plasma CVD using a mixed gas of SiH ₄ / NH ₃ . The SiON film or the SiNO film can be typically formed by plasma CVD using a mixed gas of SiH ₄ / N ₂ O.

Note that in the case where a material mainly containing silicon such as a-Si is used for the peeling layer 802 and the island-shaped semiconductor film 804, SiOxNy is used as a protective film in contact therewith from the viewpoint of ensuring adhesion. Also good.

Next, a thin film transistor (TFT) that forms a CPU and a memory of the thin film integrated circuit device is formed over the protective film 803. In addition to TFTs, thin film active elements such as organic TFTs and thin film diodes can also be formed. Note that the TFT, the organic TFT, and the like on the protective film 803 may be collectively referred to as an element group.

As a method for manufacturing a TFT, first, an island-shaped semiconductor film 804 is formed over the protective film 803 (FIG. 8B). The island-shaped semiconductor film 804 is formed using an amorphous semiconductor, a crystalline semiconductor, or a semi-amorphous semiconductor. In any case, a semiconductor film containing silicon, silicon germanium (SiGe), or the like as a main component can be used.

Here, amorphous silicon having a thickness of 70 nm was formed, and the surface thereof was further treated with a solution containing nickel. Further, a crystalline silicon semiconductor film was obtained by a thermal crystallization process at 500 to 750 ° C., and crystallinity was improved by laser crystallization. Further, as a film formation method, a plasma CVD method, a sputtering method, an LPCVD method, or the like may be used. As the crystallization method, laser crystallization method, thermal crystallization method, thermal crystallization using other catalysts (Fe, Ru, Rh, Pd, Pd, Os, Ir, Pt, Cu, Au, etc.), or those May be performed a plurality of times alternately.

In addition, a continuous wave laser may be used for the crystallization treatment of the semiconductor film having an amorphous structure, and a solid laser capable of continuous oscillation is used in order to obtain a crystal having a large particle size upon crystallization. It is preferable to apply the second to fourth harmonics of the fundamental wave (the crystallization in this case is referred to as CWLC). Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. In the case of using a continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method in which a YVO ₄ crystal or GdVO ₄ crystal and a non-linear optical element are placed in a resonator to emit harmonics. Preferably, the laser beam is shaped into a rectangular or elliptical shape on the irradiation surface by an optical system, and the object to be processed is irradiated. At this time, the energy density of approximately 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

In the case of using a pulsed laser, a frequency band of several tens Hz to several hundreds Hz is usually used, but a pulsed laser having an oscillation frequency of 10 MHz or higher that is significantly higher than that may be used (in this case) Crystallization is referred to as MHzLC). It is said that the time from when the semiconductor film is irradiated with laser light by pulse oscillation until the semiconductor film is completely solidified is said to be several tens of nanoseconds to several hundreds of nanoseconds. The laser light of the next pulse can be irradiated from the time of melting by the laser light until solidification. Therefore, unlike the case of using a conventional pulsed laser, the solid-liquid interface can be moved continuously in the semiconductor film, so that a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Is done. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction of the included crystal grains and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, it is possible to form a semiconductor film having almost no crystal grain boundaries in at least the channel direction of the TFT.

Note that in the case where siloxane which is a heat-resistant organic resin is used for part of the protective film 803, heat can be prevented from leaking from the semiconductor film during the crystallization, and crystallization can be efficiently performed. It can be carried out.

A crystalline silicon semiconductor film is obtained by the above method. Note that the crystals are preferably aligned in the source, channel, and drain directions. The thickness of the crystal layer is preferably 20 to 200 nm (typically 40 to 170 nm, more preferably 50 to 150 nm). Thereafter, an amorphous silicon film for gettering the metal catalyst was formed on the semiconductor film via an oxide film, and gettering treatment was performed by heat treatment at 500 to 750 ° C. Furthermore, in order to control the threshold value as the TFT element, boron ions having a dose of the order of 10 ¹³ / cm ² were implanted into the crystalline silicon semiconductor film. Then, an island-shaped semiconductor film 804 was formed by etching using a resist as a mask.

In forming a crystalline semiconductor film, a polycrystalline semiconductor film is directly formed by LPCVD (low pressure CVD) as a source gas of disilane (Si ₂ H ₆ ) and germanium fluoride (GeF ₄ ). Also, a crystalline semiconductor film can be obtained. The gas flow ratio is Si ₂ H ₆ / GeF ₄ = 20 / 0.9, the film forming temperature is 400 to 500 ° C., and He or Ar is used as the carrier gas, but the present invention is not limited to this.

Note that hydrogen or halogen of 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ , preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ is preferably added to the channel region in the TFT. . Regarding SAS, it is desirable to set it as 1 * 10 < ¹⁹ > -2 * 10 < ²¹ > cm < ^-3 >. In any case, it is desirable to contain more than the content of hydrogen or halogen contained in the single crystal used for the IC chip. Thereby, even if a local crack occurs in the TFT portion, it can be terminated (terminated) by hydrogen or halogen.

The crystalline semiconductor film thus manufactured preferably has an electron mobility of 10 cm ² V / second or more.

Next, a gate insulating film 805 is formed over the island-shaped semiconductor film 804 (FIG. 8B). The gate insulating film is preferably formed using a thin film formation method such as a plasma CVD method or a sputtering method, and a film containing silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride is formed as a single layer or a stacked layer. In the case of stacking, for example, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film is preferable from the substrate side.

Next, the gate electrode 806 is formed (FIG. 8C). Here, after the Si and W (tungsten) layers are formed by sputtering, the gate electrode 806 is formed by etching using the resist 807 as a mask. Needless to say, the material, structure, and manufacturing method of the gate electrode 806 are not limited thereto, and can be selected as appropriate. For example, a stacked structure of Si and NiSi (nickel silicide) doped with an n-type impurity or a stacked structure of TaN (tantalum nitride) and W (tungsten) may be used. Alternatively, a single layer may be formed using various conductive materials.

In place of the resist mask, a mask such as SiOx may be used. In this case, a patterning process is added to a mask (referred to as a hard mask) made of SiOx, SiON, or the like. However, since the film thickness of the mask during etching is less than that of the resist, a gate electrode layer having a desired width may be formed. it can. Alternatively, the gate electrode 806 may be selectively formed by a droplet discharge method without using the resist 807.

As the conductive material, various materials can be selected depending on the function of the conductive film. In the case where the gate electrode and the antenna are formed at the same time, materials may be selected in consideration of their functions.

Note that although a mixed gas of CF ₄ , Cl ₂ , and O ₂ or Cl ₂ gas is used as an etching gas for forming the gate electrode by etching, it is not limited to this.

Next, a portion to become the p-type TFTs 809 and 811 is covered with a resist 812, and an impurity element 813 (typically P-type) is given to the island-shaped semiconductor film of the n-type TFTs 808 and 810 using the gate electrode as a mask. (Phosphorus) or As (arsenic)) is doped at a low concentration (first doping step, FIG. 8D). The conditions of the first doping step are a dose of 1 × 10 ^{13 to} 6 × 10 ¹³ / cm ² and an acceleration voltage of 50 to 70 keV, but are not limited thereto. Through this first doping step, through doping is performed through the gate insulating film 805, and a pair of low-concentration impurity regions 814 are formed. The first doping step may be performed on the entire surface without covering the p-type TFT region with the resist.

Next, after removing the resist 812 by ashing or the like, a resist 815 that covers the n-type TFT region is newly formed, and p-type is imparted to the island-shaped semiconductor films of the p-type TFTs 809 and 811 using the gate electrode as a mask. An impurity element 816 (typically B (boron)) to be doped is doped at a high concentration (second doping step, FIG. 8E). The conditions of the second doping step are a dose amount: 1 × 10 ^{16 to} 3 × 10 ¹⁶ / cm ² and an acceleration voltage: 20 to 40 keV. Through this second doping step, through doping is performed through the gate insulating film 805, and a pair of p-type high concentration impurity regions 817 are formed.

Next, after removing the resist 815 by ashing or the like, an insulating film 901 was formed on the surface of the substrate (FIG. 9F). Here, a SiO ₂ film having a thickness of 100 nm was formed by a plasma CVD method. After that, the insulating film 901 and the gate insulating film 805 were etched away by an etch back method, and sidewalls (sidewalls) 903 were formed in a self-aligned manner (FIG. 9G). As the etching gas, a mixed gas of CHF ₃ and He was used. Note that the step of forming the sidewall is not limited to these.

Note that the method for forming the sidewall 903 is not limited to the above. For example, the method shown in FIG. 10 can be used. FIG. 10A illustrates an example in which the insulating film 901 has a two-layer structure or more. The insulating film 901 has a two-layer structure of, for example, a 100 nm thick SiON (silicon oxynitride) film and a 200 nm thick LTO film (Low Temperature Oxide). Here, the SiON film was formed by the plasma CVD method, and the SiO ₂ film was formed by the low pressure CVD method as the LTO film. Thereafter, by performing etch back, a sidewall 903 having an L shape and an arc shape is formed.

FIG. 10B shows an example in which etching is performed so as to leave the gate insulating film 805 at the time of etch back. In this case, the insulating film 901 may have a single-layer structure or a stacked structure.

The sidewall functions as a mask when a high concentration n-type impurity is doped later to form a low concentration impurity region or a non-doped offset region below the sidewall 903. In any of the formation methods, the etch-back conditions may be changed as appropriate depending on the width of the low-concentration impurity region or offset region to be formed.

Next, a resist 904 covering the p-type TFT region is newly formed, and an impurity element 905 (typically P or As) imparting n-type is doped at a high concentration using the gate electrode 806 and the sidewall 903 as a mask. (Third doping step, FIG. 9H). The conditions of the third doping step are a dose amount: 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage: 60 to 100 keV. By this third doping step, a pair of n-type high concentration impurity regions 906 are formed.

Note that the impurity region may be thermally activated after the resist 904 is removed by ashing or the like. For example, after a 50 nm SiON film is formed, heat treatment may be performed in a nitrogen atmosphere at 550 ° C. for 4 hours. In addition, after the SiNx film containing hydrogen is formed to a thickness of 100 nm, defects in the crystalline semiconductor film can be improved by performing heat treatment at 410 ° C. for 1 hour in a nitrogen atmosphere. This terminates dangling bonds existing in, for example, crystalline silicon, and is called a hydrogenation process. Thereafter, a SiON film having a film thickness of 600 nm is formed as a cap insulating film for protecting the TFT. Note that the hydrogenation process may be performed after the formation of the SiON film. In this case, the SiNx \ SiON film can be continuously formed. As described above, a three-layer insulating film of SiON / SiNx / SiON is formed on the TFT, but the structure and material are not limited to these. In addition, these insulating films have a function of protecting the TFT, so that it is desirable to form them as much as possible.

Next, an interlayer film 907 is formed over the TFT (FIG. 9I). As the interlayer film 907, a heat-resistant organic resin such as polyimide, acrylic, polyamide, or siloxane can be used. Depending on the material, spin coating, dipping, spray coating, droplet discharge methods (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. are adopted as the forming method. be able to. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. Note that the interlayer film 907 may be formed by stacking these insulating films.

Further, a protective film 908 may be formed over the interlayer film 907. As the protective film 908, a film containing carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like can be used. As a formation method, a plasma CVD method, an atmospheric pressure plasma, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist, or benzocyclobutene, or a heat-resistant organic resin such as siloxane may be used.

In order to prevent the film from peeling or cracking of these films due to the stress caused by the difference in thermal expansion coefficient between the interlayer film 907 or the protective film 908 and a conductive material or the like constituting the wiring to be formed later, A filler may be mixed in the film 907 or the protective film 908.

Next, a contact hole is formed by forming a resist and etching to form a wiring 909 for connecting the TFTs and a connection wiring 910 for connecting to an external antenna (FIG. 9I). A gas used for etching when opening the contact hole is a mixed gas of CHF ₃ and He, but is not limited to this. Further, the wiring 909 and the connection wiring 910 may be formed at the same time using the same material, or may be formed separately. Here, the wiring 909 connected to the TFT has a five-layer structure of Ti \ TiN \ Al-Si \ Ti \ TiN, and is formed by sputtering and then patterned.

In addition, by mixing Si in the Al layer, generation of hillocks in resist baking during wiring patterning can be prevented. Further, instead of Si, about 0.5% Cu may be mixed. Further, the hillock resistance is further improved by sandwiching the Al—Si layer with Ti or TiN. In the patterning, it is desirable to use the hard mask made of SiON or the like. Note that the wiring material and the formation method are not limited to these, and the material used for the gate electrode described above may be employed.

In this embodiment, the case where only the TFT region and the connection terminal portion 911 connected to the antenna are integrally formed has been described. However, the present embodiment can also be applied to the case where the TFT region and the antenna are formed integrally. In this case, an antenna is preferably formed over the interlayer film 907 or the protective film 908 and further covered with another protective film. As the conductive material of the antenna, Ag, Au, Al, Cu, Zn, Sn, Ni, Cr, Fe, Co, or Ti, or an alloy containing them can be used, but is not limited thereto. Further, the material may be different between the wiring and the antenna. Note that the wiring and the antenna are preferably formed so as to have a metal material having excellent malleability and ductility, and more preferably, the wiring and the antenna are made thick to withstand stress due to deformation.

As a formation method, after forming a film on the entire surface by a sputtering method, patterning may be performed using a resist mask, or selective formation from a nozzle may be performed by a droplet discharge method. Note that the droplet discharge method here includes not only an inkjet method but also an offset printing method and a screen printing. The wiring and the antenna may be formed at the same time, or may be formed so that the other rides on after forming one first.

Through the above steps, a thin film integrated circuit device composed of TFTs is completed. In the case where a ring oscillator is configured using the TFTs thus produced, at a power supply voltage of 3 to 5 V, the oscillation frequency is 1 MHz or higher, preferably 100 MHz or higher. Further, at the same power supply voltage, the delay time per inverter stage is 26 nsec or less, preferably 0.26 nsec or less.

Although the top gate structure is used in this embodiment, a bottom gate structure (reverse stagger structure) may be used. Note that a base insulating film material, an interlayer insulating film material, and a wiring material are mainly provided in a region where a thin film active element portion (active element) such as a TFT does not exist, and this region is the entire thin film integrated circuit device. It is desirable to occupy 50% or more, preferably 70 to 95%. This makes it easy to bend the ID chip and facilitates handling of finished products such as ID labels. In this case, the island-shaped semiconductor region (island) of the active element including the TFT portion occupies 1 to 30%, preferably 5 to 15% of the entire thin film integrated circuit device.

Further, as shown in FIG. _9I , the distance (t _under ) from the semiconductor layer of the TFT to the lower protective layer in the thin film integrated circuit device, and the upper interlayer film (protective layer is formed from the semiconductor layer). In this case, the thicknesses of the upper and lower protective layers or interlayer films are adjusted so that the distance (t _over ) to the protective layer is equal or approximately equal, and the deviation from the center is the sum of the upper and lower protective layers. If the thickness is d, the thickness is smaller than ½d + 30 μm on either side, and ½d−30 μm << X << 1 / 2d + 30 μm, preferably 1 / 2d−10 μm << X << 1 / 2d + 10 μm. In this manner, by placing the semiconductor layer in the center of the thin film integrated circuit device, the stress on the semiconductor layer can be relaxed and the occurrence of cracks can be prevented.

In this embodiment, an application example of the semiconductor device of the present invention transferred to a flexible substrate will be described. The semiconductor device of the present invention is very thin and small, and a semiconductor device transferred onto a flexible substrate can have flexibility, so that it can be mounted on a sheet-like article. For example, the case where it mounts on a banknote as a sheet-like article is demonstrated.

As shown in FIG. 11A, an ID chip 1102 is mounted on the banknote 1101. In FIG. 11A, the ID chip 1102 is mounted on the inside of a bill, but may be exposed on the surface. Moreover, you may mount an ID chip by printing a banknote using the ink containing an ID chip, or mixing an ID chip with the material of a banknote. Since the semiconductor device can be produced at low cost, even if a plurality of ID chips are mounted, the production cost of banknotes can be reduced.

Moreover, high security can be ensured by mounting ID chips on securities other than banknotes, such as stock certificates, checks, or coins.

However, since such a sheet-shaped article has many opportunities to bend, it is necessary to consider the bending stress applied to the ID chip. In general, since a sheet-like article is easily bent or bent in the long axis direction, FIG. 11B illustrates a case where a banknote with an ID chip is bent in the long axis direction of an arrow.

The state of the ID chip at this time is shown in FIG. The ID chip includes a plurality of thin film transistors 1103, which include a source region 1104, a channel formation region 1105, and a drain region 1106. Such an ID chip 1102 is preferably arranged so that the arrow direction (bending direction) and the carrier moving direction are perpendicular to each other. That is, the thin film transistor 1103 is arranged so that the direction connecting the source region 1104, the channel formation region 1105, and the drain region 1106 is perpendicular to the bending direction. In the case where a crystalline semiconductor film using laser irradiation is used for the thin film transistor, the laser scanning direction is also set to be perpendicular to the bending direction. As a result, destruction and peeling of the thin film transistor due to bending stress can be prevented.

In addition, the proportion of the area occupied by the patterned semiconductor film in the ID chip is 1 to 30%, whereby the thin film transistor can be prevented from being broken or peeled off due to bending stress.

Furthermore, the ID chip of the present invention transferred onto a flexible substrate can be mounted on a commodity container such as a food product to perform safety management and physical distribution management.

FIG. 12 shows a label 1202 on which an ID chip 1201 is mounted and a meat pack 1203 to which the label is attached as an example of product safety management. The ID chip transferred to the flexible substrate has flexibility and can be mounted to some extent according to the shape of the product. Therefore, the ID chip 1201 may be mounted on the surface of the label 1202 or the label. It may be implemented internally. In the case of fresh food such as vegetables, an ID chip may be mounted on a wrap that covers the fresh food.

The memory area in the ID chip 1201 can record basic items related to the product such as the product production location, producer, date of processing, expiration date, and application items such as cooking examples using the product. .

In addition, it is important to be able to know the state of animals and plants before processing in order to carry out food safety management. For this reason, it is preferable to attach and embed ID chips to growing plants and animals to manage the plants and animals and accumulate information about them. Information on animals and plants includes breeding grounds, feed, breeders, presence of infectious diseases, and the like.

Furthermore, if the price of the product is recorded on the ID chip, the product on which the ID chip is mounted can be settled at a time, so it is easier to settle the product in a shorter time than the method using the conventional barcode. Can be done. Depending on the communication distance of the ID chip, even if the distance between the register and the merchandise is long, the merchandise can be settled. Applying this function will help prevent shoplifting. However, when reading a plurality of ID chips at a time, the reader device needs to be equipped with an anti-collision function that can exchange data with a plurality of ID chips at a time.

In addition, the ID chip can be used in combination with other information media such as a barcode and a magnetic tape. For example, basic items that do not need to be rewritten, such as a desired retail price, may be recorded on the ID chip, and information to be updated, for example, discount prices or special price information, may be recorded on the barcode. This is because, unlike an ID chip, a bar code can easily correct information.

By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

Next, as an example of distribution management, a case where an ID chip is mounted on a product container such as a beer bottle will be described. 12B and 12C illustrate an example in which the ID chip 1204 is mounted in a label 1205 and attached to a beer bottle 1206.

In the memory area in the ID chip, in addition to the date of manufacture, the place of manufacture, the materials used, etc., the delivery destination of each beer bottle, the delivery date, etc. can be recorded. For example, as shown in FIG. 12C, when each beer bottle flows by the belt conveyor 1207 and passes through the writer device 1208, each delivery destination and delivery date and time can be recorded.

Using this function, for example, when product delivery request information is transmitted to the distribution management center through the network, the writer device or a personal computer that controls the writer device, based on this information, determines the delivery destination and delivery date and time. It is desirable to construct a system that calculates and records to the ID chip.

Furthermore, food items suitable for purchased products, cooking methods using purchased products, advertisements for similar new products, and the like may be recorded in a memory area in the ID chip. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced.

Further, since delivery may be performed for each case, an ID chip can be mounted for each case or for each of a plurality of cases to record individual matters.

In particular, when there are a plurality of similar products, by mounting the ID chip, it is possible to reduce time required for manual input and input mistakes. Furthermore, since the most costly labor cost can be reduced in the field of physical distribution management, it is possible to carry out low-cost physical distribution management with few mistakes by mounting an ID chip.

By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

In this embodiment, in order to perform manufacturing management, a manufactured product on which the semiconductor device of the present invention is mounted and a manufacturing apparatus (manufacturing robot) controlled based on information on the semiconductor device will be described.

In recent years, there are an increasing number of consumers who desire original products instead of standard products in various products. When producing such original products, production lines are produced based on the original information of the products. For example, in an automobile production line in which a paint color can be freely selected, an ID chip is mounted on a part of the automobile, and the painting apparatus is controlled based on information written in the ID chip, so that the original color Can produce automobiles.

As a result of mounting the ID chip, there is no need to adjust the order of cars to be put on the production line or the number of the same color in advance, and it is not necessary to set a program for controlling the coating apparatus to match the order and number of cars I'm sorry. In addition, the manufacturing apparatus can operate individually based on the information of the ID chip mounted on the automobile.

Thus, since the ID chip can control the manufacturing apparatus by recording the unique information related to the manufacture of the product, it can also be used in a production line for a small variety of products.

In this embodiment, a mode in which the integrated circuit of the present invention is used as electronic money will be described.

FIG. 13 shows how payment is performed using the IC card 1301. The IC card 1301 has the integrated circuit 1302 of the present invention. 1303 corresponds to a register, and 1304 corresponds to a reader / writer.

The integrated circuit 1302 holds information about the amount of money deposited in the IC card 1301, and the reader / writer 1304 can read the amount information without contact and send it to the register 1303. The register 1303 confirms that the amount deposited in the IC card 1301 is equal to or greater than the amount to be settled, and performs settlement. Then, the information on the remaining amount after settlement is transmitted to the reader / writer 1304. The reader / writer 1304 can write the remaining amount information into the integrated circuit 1302 of the IC card 1301.

Note that an input key 1305 for inputting a password or the like may be added to the reader / writer 1304 so that a third party can be prevented from making a settlement using the IC card 1301 without permission.

FIG. 11 is a block diagram illustrating a structure of a semiconductor device of the invention. FIG. 11 is a block diagram illustrating a structure of a semiconductor device of the invention. FIG. 11 is a block diagram illustrating a structure of a semiconductor device of the invention. FIG. 11 is a block diagram illustrating a structure of a semiconductor device of the invention. FIG. 11 is a block diagram illustrating a structure of a semiconductor device of the invention. The figure explaining the structure of the circuit which determines the power supply level which generate | occur | produces a power information signal. FIG. 10 illustrates an example of a usage pattern of a semiconductor device. 8A and 8B illustrate a manufacturing process of a semiconductor device. 8A and 8B illustrate a manufacturing process of a semiconductor device. 8A and 8B illustrate a manufacturing process of a semiconductor device. FIG. 10 illustrates an example of a usage pattern of a semiconductor device. FIG. 10 illustrates an example of a usage pattern of a semiconductor device. FIG. 10 illustrates an example of a usage pattern of a semiconductor device.

Claims (21)

A central processing circuit for generating event signals;
A control circuit for generating a command signal including information for changing a power supply potential and a clock frequency supplied to the central processing circuit based on the event signal;
An integrated circuit comprising a connection terminal for connecting an antenna. 2. The event signal according to claim 1, wherein the event signal is a signal including information on an operating state of an integer unit, a floating point unit, a load / store unit, or a branch unit included in the central processing circuit, or a plurality of units included in the central processing circuit. Select from a signal including information on the execution status of an integer operation instruction, floating point operation instruction, load instruction, store instruction, branch instruction or NOP instruction, or a signal generated by a combinational circuit including a plurality selected from the plurality of units One or more integrated circuits. A central processing circuit, a power supply determination circuit for generating a power information signal, and
A control circuit for generating a command signal including information for changing a power supply potential and a clock frequency supplied to the central processing circuit based on the power supply information signal;
An integrated circuit comprising a connection terminal for connecting an antenna. 4. The power supply determination circuit according to claim 3, further comprising: a power supply circuit including a load resistor; a reference voltage generation circuit; and a comparison circuit that compares an output potential of the power supply circuit with an output potential of the reference voltage generation circuit. An integrated circuit characterized by that. A central processing circuit for generating a memory and a memory access signal;
A control circuit for generating a command signal including information for changing a power supply potential and a clock frequency supplied to the memory based on the memory access signal;
An integrated circuit comprising a connection terminal for connecting an antenna. 6. The memory access signal according to claim 5, wherein the memory access signal includes a signal including information on an operation status of a memory control unit included in the central processing circuit, a signal including information on an execution status of a load / store instruction of the central processing circuit, or the An integrated circuit comprising one or a plurality of signals selected from signals generated by a combinational circuit including a plurality selected from a plurality of units included in a central processing circuit. 5. The integrated circuit according to claim 1, wherein the control circuit is provided inside the central processing circuit. 6. 7. The integrated circuit according to claim 5, wherein the control circuit is provided in the central processing circuit or in the memory. 7. The memory according to claim 5, wherein the memory is one or more selected from SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and flash memory. An integrated circuit characterized by being. 10. The integrated circuit according to claim 1, wherein the integrated circuit is provided on a glass substrate or a flexible substrate. A central processing circuit for generating event signals;
A control circuit for generating a command signal including information for changing a power supply potential and a clock frequency supplied to the central processing circuit based on the event signal;
A semiconductor device comprising: the central processing circuit; and an antenna for supplying power to the control circuit. 12. The event signal according to claim 11, wherein the event signal is a signal including information on an operating state of an integer unit, a floating point unit, a load / store unit or a branch unit included in the central processing circuit, or a plurality of units included in the central processing circuit. Select from a signal including information on the execution status of an integer operation instruction, floating point operation instruction, load instruction, store instruction, branch instruction or NOP instruction, or a signal generated by a combinational circuit including a plurality selected from the plurality of units One or more of the semiconductor devices. A central processing circuit, a power supply determination circuit for generating a power information signal, and
A control circuit for generating a command signal including information for changing a power supply potential and a clock frequency supplied to the central processing circuit based on the power supply information signal;
A semiconductor device comprising: the central processing circuit; and an antenna for supplying power to the control circuit. 14. The power supply determination circuit according to claim 13, comprising a power supply circuit including a load resistor, a reference voltage generation circuit, and a comparison circuit that compares an output potential of the power supply circuit with an output potential of the reference voltage generation circuit. A semiconductor device. A central processing circuit for generating a memory and a memory access signal;
A control circuit for generating a command signal including information for changing a power supply potential and a clock frequency supplied to the memory based on the memory access signal;
A semiconductor device comprising: the memory; the central processing circuit; and an antenna for supplying power to the control circuit. 16. The memory access signal according to claim 15, wherein the memory access signal includes a signal including information on an operation status of a memory control unit included in the central processing circuit, a signal including information on an execution status of a load / store instruction of the central processing circuit, or the A semiconductor device comprising one or a plurality of signals selected from signals generated by a combinational circuit including a plurality selected from a plurality of units included in a central processing circuit. 15. The semiconductor device according to claim 11, wherein the control circuit is provided inside the central processing circuit. 17. The semiconductor device according to claim 15, wherein the control circuit is provided in the central processing circuit or in the memory. 17. The memory according to claim 15, wherein the memory is one or more selected from SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and flash memory. There is a semiconductor device. The semiconductor device according to claim 11, wherein the semiconductor device is provided on a glass substrate or a flexible substrate. A wireless chip in which the integrated circuit according to any one of claims 1 to 10 or the semiconductor device according to any one of claims 11 to 20 is incorporated.

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