JP2005267215A - Device and method for writing out data in processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device and method for writing out data in a processor. <P>SOLUTION: Data are saved in an internal register of a processor and written out to unaligned addresses in a memory. A rotator is coupled to the internal register for rotating data in the internal register to a first position according to the written address of the unaligned data. A store combine register is coupled to the internal register for temporarily saving the data in the rotator. A mask selector is coupled to the rotator and store combine register for selectively masking the data in the rotator and store combine register according to the written address and writing them out to the memory. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to the technical field of data processing, and more particularly to an apparatus and method for writing data in a kind of processor.

  When a processor processes data, whether or not the data is aligned is related to a number of key calculation functions, such as strings and arrays. As shown in FIG. 1, when data (ABCDEFGHIJKL) requiring processing is written from the registers R16, 17 and 18 to the 101Ch to 100Ch portion of the storage device 100, the data storage boundary of the storage device 100 is often set. Straddle. Since the storage device 100 does not have data processing capabilities, the processor must perform an extra number of operations when the processor attempts to store data in an unaligned location of the storage device 100.

  According to a well-known method for solving the problem of unalignment of data processing, after loading the data of the non-alignment position portion of the storage device 100 into the processor, the necessary data is obtained using various processor instruction operations. As shown in FIG. 2, when it is necessary to write the data ABCD to the non-alignment position, first, the data (abcd) located in the 100h portion is loaded into the register R1, and the register R1 is moved 24 bits to the left and saved. The data (a) that is necessary is left at an appropriate position. Further, the data (ABCD) in the register R16 is moved to the right by 8 bits and stored in the register R2 (0ABC), and the register R1 and the register R2 are subjected to an OR operation and the result is stored in R1 (aABC). Next, the data (efgh) located in the 104h portion is first loaded into the register R1, the register R1 is moved 8 bits to the left to save the data (fgh) that needs to be saved, and the register R1 is set to 8 bits to the right. The data (fgh) that needs to be moved and stored is stored in an appropriate location. Further, the data (ABCD) of the register R16 is moved 24 bits to the left and further stored in the register R2 (D000), the register R1 and the register R2 are ORed, and the result is stored in the register R1 (Dfgh). The contents of the register R1 are written into the storage device 104h.

  As can be seen from the above description, if the length of unaligned data that needs to be written to the storage device is n words (one word is 32 bits), according to a well-known method, if there are 12n instructions, The write operation cannot be described, and the write operation cannot be completed without an instruction period of at least 12n. As a result, the program code becomes redundant, occupies a storage space, and increases the burden on the processor, making the efficiency of the processor unclear.

  In order to solve the problem of program code redundancy and efficiency caused by processing unaligned data using processor instructions in a well-known method, Patent Document 1 discloses that alignment operation is performed simultaneously with loading of unaligned data. And a method for writing out data across the boundary in two steps. As shown in FIG. 3, according to this method, the contents (ABC) in the register R16 are first written from 101h to 103h, and at this time, the data in the storage device 100h is not changed. Further, the content (D) in the register R16 is written to the storage device 104h, and at this time, the data in the storage device 105h to 107h is not changed. Similarly, the contents of the registers R17 and R18 are written from the storage devices 105h to 10Ch.

US Pat. No. 4,814,976

  As can be seen from the above description, according to the technique described in Patent Document 1, if the length of unaligned data that needs to be written is n words (one word is 32 bits), there are no 2n instructions. Since the write operation cannot be described, and the same read / write operation is performed on the same storage device and register, the possibility of causing a pipeline stall in the processor is increased. In addition, since the same storage device location is written redundantly, the bus frequency width is wasted, and particularly in a system without a flash storage device, the error to be formed becomes more apparent. As a result, known processor designs have many drawbacks and need improvement.

  Therefore, the present invention provides an apparatus and method for writing data in a kind of processor, and solves the problem of the writing technique that cannot be written unless many instructions are used in the well-known technique, and writing operation with a reduced instruction cycle. The purpose is to improve the execution efficiency.

The invention of claim 1 is a method of writing data in a processor, wherein the data is written to an unaligned address in a storage device, and the storage device is divided into a plurality of m-bit words by word boundaries, The method includes a start rotation step, a first shield writing step, a relay rotation step, a first writing step, an end rotation step, a second writing step, and a second shielding writing step.
The starting rotation step captures the data and rotates it to the first position by the unaligned address of writing to generate first rotation data;
In the first shield writing step, the first rotation data is shielded by the unaligned address of writing and written to the storage device,
In the relay rotation step, the subsequent data of the data is captured and rotated to the first position by the unaligned address of the writing to generate the second rotation data,
In the first writing step, the unwritten portion of the first rotation data and a part of the second rotation data are combined and written to the storage device,
In the end rotation step, the subsequent data of the data is rotated to the first position to generate third rotation data,
In the second writing step, the unwritten portion of the second rotation data and a part of the third rotation data are combined and written to the storage device,
In the second shield writing step, the third rotation data is shielded and written to the storage device, and the data is written in the processor.
The invention of claim 2 is a method of writing data in the processor according to claim 1, wherein m is 32.
The invention according to claim 3 is the method for writing data in the processor according to claim 2, wherein the rotation to the first position is an 8-bit rotation to the right. It is said.
4. The method of writing data in the processor according to claim 2, wherein the rotation to the first position is a 16-bit rotation to the right. It is said.
The invention according to claim 5 is the method for writing data in the processor according to claim 2, wherein the rotation to the first position is a 24-bit rotation to the right. It is said.
The invention of claim 6 is a method for writing data in a processor, in which data is written to an unaligned address in one storage device, and the storage device is divided into a plurality of m-bit words by word boundaries. The method comprises a starting rotation step, a first shield writing step, a second shield writing step,
The starting rotation step captures data and rotates it to the first position by the unaligned address of writing to generate first rotation data;
In the first shield writing step, the first rotation data is shielded by an unaligned address and written to the storage device;
In the second shield writing step, a method of writing data in the processor is characterized in that shielding and writing to the storage device are executed for the unwritten portion of the first rotation data.
The invention according to claim 7 is the method for writing data in the processor according to claim 6, wherein the unwritten portion in the first rotation data is smaller than m bits. .
The invention of claim 8 is the method for writing data in the processor according to claim 6, wherein m is 32.
The invention according to claim 9 is the method for writing data in the processor according to claim 8, wherein the rotation to the first position is a rightward 8-bit rotation. It is said.
The invention according to claim 10 is the method for writing data in the processor according to claim 8, wherein the rotation to the first position is a 16-bit rotation to the right. It is said.
The invention according to claim 11 is the method for writing data in the processor according to claim 8, wherein the rotation to the first position is a 24-bit rotation to the right. It is said.
The invention of claim 12 is an apparatus for writing data in a processor, the data is stored in an internal register of the processor and written to an unaligned address in a storage device, and the storage device has a plurality of m by a word boundary. Divided into words of bits, the device comprises a rotating device, a store combine register, and a selective shielding device,
The rotating device is coupled to the internal register, and rotates the data in the internal register to the first position by the write address of the unaligned data.
The store combine register is coupled to the rotator to store the rotator data for a while,
The selective shielding device is coupled to the rotating device and the store combine register, and the data of the rotating device and the store combine register is selectively shielded by the write address and written to the storage device. , A device for writing data in the processor.
According to a thirteenth aspect of the present invention, in the apparatus for writing data in the processor according to the twelfth aspect, the processor executes the first instruction and sets the data in the internal register to the first position by the address of the data write to the rotating device. Rotating to generate the first rotation data and storing it in the store combine register, and the selective shielding device selectively shields the data of the rotating device and the store combine register by the address of the data write and A device for writing data in a processor is characterized by writing to a storage device.
The invention according to claim 14 is the apparatus for writing data in the processor according to claim 12, wherein the processor executes the second instruction to cause the rotating device to capture subsequent data of the data and to rotate it to the first position. Generating the second rotation data and storing the second rotation data in the store combine register, the selective shielding device combining the unwritten portion of the first rotation data and a part of the second rotation data according to the data write address, and This is a device for writing data in a processor, which is characterized by writing it to a storage device.
The invention according to claim 15 is the apparatus for writing data in the processor according to claim 12, wherein the processor executes a third instruction to cause the rotating device to capture subsequent data of the data and to rotate it to the first position. Generating the third rotation data and storing it in the store combine register, and the selective shielding device combines the unwritten portion of the second rotation data and a part of the third rotation data according to the write address of the data, and This is a device for writing data in a processor, which is characterized by writing it to a storage device.
According to a sixteenth aspect of the present invention, in the apparatus for writing data in the processor according to the fifteenth aspect, the selective shielding device stores the unrotated portion of the third rotation data according to the write start address of the data. It is a device for writing data in a processor, which is characterized by being written to.
The invention according to claim 17 is the apparatus for writing data in the processor according to claim 12, wherein m is 32, and the apparatus writes data in the processor.
The eighteenth aspect of the present invention is the apparatus for writing data in the processor according to the seventeenth aspect, wherein the rotating apparatus rotates the data by 8 bits to the right.
According to a nineteenth aspect of the present invention, there is provided an apparatus for writing data in a processor according to the seventeenth aspect, wherein the rotating device rotates 16 bits to the right.
According to a twentieth aspect of the present invention, in the apparatus for writing data in the processor according to the seventeenth aspect, the rotating apparatus rotates data by 24 bits to the right.

  If the data length of the unaligned address of the data that needs to be written to the storage device 500 is n words, the technique of the present invention can describe the write operation with only (n + 1) instructions, and the program code In addition to shortening, if there are only (n + 1) instruction cycles, the write operation can be completed and the execution efficiency can be greatly improved. In addition, it is possible to reduce the possibility of stalling of the processor pipeline without performing redundant writing to the same storage device and the register position, and only to write once to the same storage device position. And optimize the use of the bus frequency width.

  In summary, the present invention differs from the features of known techniques in any of its purposes, means, and functions, and has extremely practical value.

  The present invention provides a method for writing data in a processor, wherein the data is stored in one internal register, which is divided into a plurality of m-bit words by word boundaries, the method comprising a starting rotation step , A first shield writing step, a relay rotation step, a first writing top, an end rotation step, a second writing step, and a second shielding writing step. In the start rotation step, data is captured and rotated to the first position by the unaligned address of writing to generate first rotation data. In the first shield writing step, the first rotation data is shielded by the unaligned address of writing and is written to the storage device. In the relay rotation step, the subsequent data of the data is captured and rotated to the first position by the unaligned address that has been written to generate second rotation data. In the first writing step, the unwritten portion of the first rotation data and a part of the second rotation data are combined and written to the storage device. In the end rotation step, the subsequent data of the data is rotated to the first position to generate third rotation data. In the second writing step, the unwritten portion of the second rotation data and a part of the third rotation data are combined and written to the storage device. In the second shield writing step, the third rotation data is shielded and written to the storage device.

  The present invention also provides a method for writing data in a processor, wherein data is written to unaligned addresses in one storage device, and the storage device is divided into multiple m-bit words by word boundaries. The method includes a starting rotation step, a first shield writing step, and a second shield writing step. In the start rotation step, data is captured and rotated to the first position by the unaligned address of writing to generate first rotation data. In the first shield writing step, the first rotation data is shielded by the unaligned address and written to the storage device. In the second shield writing step, shielding and writing to the storage device are executed for the unwritten portion of the first rotation data.

  The present invention also provides an apparatus for writing data in a processor. Among them, data is stored in one internal register and written to an unaligned address in the storage device, and the storage device is divided into a plurality of m-bit words by word boundaries. A resistor and a selective shielding device are provided. The rotation device is coupled to the internal register, and rotates the data in the internal register to the first position according to the write address of the unaligned data. The store combine register is coupled to the rotator and stores the data of the rotator for a while. The selective shielding device is coupled to the rotating device and the store combine register, and selectively writes the data of the rotating device and the store combine register according to the write address, and writes it to the storage device.

  FIG. 4 is a block diagram of an apparatus for writing data in the processor of the present invention. It comprises a rotating device 200, a store combine register 300, and a selective shielding device 400. Among them, the data is stored in the internal register 100 of the processor, which is written to an unaligned position of the storage device 500, and the storage device 500 is divided into a plurality of m-bit words at word boundaries. m is 32 bits, that is, the storage device 500 is composed of a plurality of 32-bit words.

  The rotation device 200 is coupled to the internal register 100, and rotates the data in the internal register 100 to the first position according to the data unaligned address. The store combine register 300 is coupled to the rotating device 200 and stores data of the rotating device 200 for a while. The selective shielding device 400 is coupled to the rotating device 200 and the store combine register 300 to selectively shield the data of the rotating device 200 and the store combine register 300 by the unaligned address of the data and Write to the storage device 500.

  In the apparatus for writing data in the processor of the present invention, three instructions are defined to generate control signals related to the rotating device 200, the store combine register 300, and the selective shielding device 400. The three instructions are Store Combine Begin (SCB), Store Combine Word (SCW), and Store Combine End (SCE), respectively. The format is as shown in FIG.

  As shown in FIG. 6, the SCB rD [Addr] instruction rotates the contents of the register rD by 0, 1, 2, and 3 bytes according to the write address Addr (s = Addr [1: 0]). Writing to the store combine register 300 (STCR) and shielding the 0, 1, 2, and 3 bytes respectively by the write address Addr (s = Addr [1: 0]), and further writing to the storage device 500. For example, SCB R16, [101h] rotates the content value of the register R16 by one byte by the write address 101h (s = 1), and further writes it to the store combine register 300 (STCR), and also writes the write address 101h (s = 1). ), One write byte is shielded, and further written to the address 101h portion of the storage device 500, the content value of the register R16 is set to ABCD, and the execution of the SCB R16, [101h] instruction is completed, and then the store combine register 300 (STCR) The content value of the storage device address 101h to 013h is ABC, and the storage device address 100h content value is not changed.

  The SCW rD, [Addr] instruction rotates the contents of the register rD by 0, 1, 2, and 3 bytes, respectively, by the address Addr (s = Addr [1: 0]), as shown in FIG. After 0, 1, 2, and 3 bytes are shielded by the write address Addr (s = Addr [1: 0]) and further combined with the bytes stored in the store combine register 300 (STCR), the storage device Write to 500. Finally, the content value of the rotated register rD is written into the store combine register 300 (STCR). For example, the SCW R16, [101h] instruction rotates the contents of the register R16 (ABCD) by one byte (DABC) by the write address 101h (s = 1) and one by the write address 101h (s = 1). After the byte (D) is shielded and further combined with the byte (abcd) stored in the store combine register 300 (STCR) (aABC), further written to the address 101h portion of the storage device 500 (aABC), and finally rotated The content value (DABC) of the register rD is written into the store combine register 300 (STCR). Therefore, after execution of the SCW R16, [101h] instruction is completed, the content value of the store combine register 300 (STCR) becomes DABC. Addresses 101h to 013h The content value of the part is ABC, and the content value of the address 100h part of the storage device is a.

  The SCE [Addr] instruction is as shown in FIG. 8, and the contents of the store combine register 300 (STCR) are 0, 1, 2, and 3 respectively depending on the address Addr (s = Addr [1: 0]) to be written. Are then written to the storage device 500. For example, the SCW [101h] instruction blocks three bytes (bcd) with the write address 101h (s = 1) against the content value (abcd) of the store combine register 300 (STCR), and further addresses the address 100h of the storage device 500. After writing to the part (a), therefore, after executing the SCE [101h] instruction, the content value of the storage device address 101h to 103h portion is not modified, and the content value of the storage device address 100h portion is a.

  FIG. 9 shows various execution situations when the SCB rD, [Addr], SCW rD, [Addr], and SCE [Addr] instructions are in two types of data arrangement methods (little endian and big endian). Among them, the data in the store combine register 200 (LDCR) is abcd, the data of the 100h to 103h portions in the storage device is XYZW, the data in the register rD is ABCD, and s = 0 is the access storage device The address is 4N, s = 1 represents the access storage device address is 4N + 1, s = 2 represents the access storage device address is 4N + 2, and s = 3 is the access storage. It represents that the device address is 4N + 3. N is a positive integer.

  FIG. 10 is an application example display diagram of the present invention. When writing the data (ABCDEFGHIJKL) in the set of registers R16, R17, and R18 to the positions 101h to 10Ch of the storage device 500, first, the SCB R16 [101h] instruction is executed, and the content value of the register R16 is written to the address 101h. Rotate one byte by (s = 1) (DABC) (start rotation step), write to store combine register 300 (STCR), and block one byte by write address 101h (s = 1) Further, the data is written to the 101h to 103h portions of the storage device 500 (first shield writing step). Therefore, after the execution of the SCB R16 [101h] instruction is completed, the content value of the store combine register 300 (STCR) becomes DABC. Addresses 101h to 103 The content value of h is ABC, and the content value of the address 100h portion of the storage device is not changed and is (a).

  Further, the SCW R17, [105h] instruction is executed. The content value (EFGH) of the register R17 is rotated by one byte by the write address 105h (s = 1) (HEFG) (relay rotation step), and one byte (s) by the write address 105h (s = 1). H) is shielded, and further combined with a byte (DABC) stored in the store combine register 300 (STCR) (DEFG), and further written to four bytes 104h to 108h including the address 105h of the storage device 500 ( DEFG) (first writing step). Finally, the content value of the rotated register R17 is written into the store combine register 300 (STCR). Therefore, after the SCW R17, [105h] instruction is executed, the content value of the store combine register 300 (STCR) becomes HEFG, and the content value of the storage device addresses 104h to 107h becomes DEFG.

  Thereafter, the SCW R18, [109h] instruction is further executed, and the content value (IJKL) of the register R18 is rotated by one byte by the write address 109h (s = 1) (LIJK) (relay rotation step), and the write One byte (L) is shielded by the address 109h (s = 1) and further combined with the byte (HEFG) stored in the store combine register 300 (STCR) (HIJK), and further the address 109h portion of the storage device 500 Are written into the four bytes 108h to 10Bh (HIJK) (second writing step), and finally the contents value (IJKL) of the rotated register R18 is written into the store combine register 300 (STCR), and thus SCW R18, [109h] After execution of instruction, store controller The content value of the bin register 300 (STCR) is LIJK, and the content value of the storage device addresses 108h to 10Ch is HIJK.

  Finally, the SCE [10Dh] instruction is executed, and the three bytes (IJK) are shielded by the write address 10Dh (s = 1) with respect to the content value (LIJK) of the store combine register 300 (STCR). Writing to the address 10Ch portion of the storage device 500 (first shield writing step), therefore, after execution of the SCE [10Dh] instruction, the content value of the store combine register 300 (STCR) is LIJK, and the contents of the storage device addresses 10Dh to 10Fn The value is unmodified (n, o, p), and the content value of the address 10Ch portion of the storage device is L.

  FIG. 11 is a display diagram of another operation of the present invention. When the data (ABCD) in the set of registers R16 is written in the positions 101h to 104h of the storage device 500, first, the SCB R16, [101h] instruction is issued. When executed, the content value (ABCD) of the register R16 is rotated by one byte (DABC) by the write address 101h (s = 1), further written to the store combine register 300 (STCR), and the write address 101h ( After one byte is shielded by s = 1), it is written to the addresses 101h to 103h of the storage device 500. Therefore, after execution of the SCBR16, [101h] instruction is completed, the store combine register 300 (STCR) The content value is DABC, and the storage device addresses 101h to 013h The content value of the minute is ABC, and the content value of the address 100h portion of the storage device is unmodified (a).

  Thereafter, the SCE [105h] instruction is executed, and the three bytes (ABC) are shielded by the write address 105h (s = 1) with respect to the content value (DABC) of the store combine register 300 (STCR), and further the storage device Thus, after the execution of the SCE [105h] instruction is completed, the content value of the store combine register 300 (STCR) becomes DABC, and the content value of the storage device addresses 105h to 107h is It becomes unmodified (f, g, h), and the content value of the address 104h portion of the storage device is D.

It is a display figure which writes out one set of register data to the unaligned address in a memory | storage device. FIG. 11 is a program code display diagram for writing a set of register data to an unaligned address in a storage device in a known technique. In another known technique, it is a program code display diagram for writing a set of register data to an unaligned address in a storage device. It is a block diagram of the apparatus which writes data in the processor of this invention. It is a command format display figure of the technique of the present invention. It is a display figure of the SCB command of the technique of the present invention. It is a display figure of the SCW command of the technique of the present invention. It is a display figure of the SCE instruction | indication of the technique of this invention. It is an execution status display figure of the SCB, SCW, and SCE instructions of the technology of the present invention. It is an application example display figure of this invention. It is another application example display figure of this invention.

Explanation of symbols

100 register 200 rotating device 300 store combine register 400 selective shielding device 500 storage device

Claims (20)

A method for writing data in a processor, wherein data is written to unaligned addresses in a storage device, and the storage device is divided into a plurality of m-bit words by word boundaries, the method comprising a starting rotation step A first shielding writing step, a relay rotation step, a first writing step, an end rotation step, a second writing step, a second shielding writing step,
The starting rotation step captures the data and rotates it to the first position by the unaligned address of writing to generate first rotation data;
In the first shield writing step, the first rotation data is shielded by the unaligned address of writing and written to the storage device,
In the relay rotation step, the subsequent data of the data is captured and rotated to the first position by the unaligned address of the writing to generate the second rotation data,
In the first writing step, the unwritten portion of the first rotation data and a part of the second rotation data are combined and written to the storage device,
In the end rotation step, the subsequent data of the data is rotated to the first position to generate third rotation data,
In the second writing step, the unwritten portion of the second rotation data and a part of the third rotation data are combined and written to the storage device,
A method of writing data in a processor, characterized in that, in the second shield writing step, the third rotation data is shielded and written to the storage device.   2. The method of writing data in a processor according to claim 1, wherein m is 32.   3. The method of writing data in a processor according to claim 2, wherein the rotation to the first position is an 8-bit rotation to the right.   3. A method for writing data in a processor according to claim 2, wherein the rotation to the first position is a 16-bit rotation to the right.   3. A method of writing data in a processor according to claim 2, wherein the rotation to the first position is a 24 bit rotation to the right. A method for writing data in a processor, wherein data is written to unaligned addresses in one storage device, and the storage device is divided into a plurality of m-bit words by word boundaries, the method starts Comprising a rotation step, a first shield writing step, a second shield writing step,
The starting rotation step captures data and rotates it to the first position by the unaligned address of writing to generate first rotation data;
In the first shield writing step, the first rotation data is shielded by an unaligned address and written to the storage device;
A method of writing data in a processor, wherein, in the second shielding writing step, shielding and writing to a storage device are executed for an unwritten portion of the first rotation data.   7. The method for writing data in the processor according to claim 6, wherein an unwritten portion in the first rotation data is smaller than m bits.   7. The method of writing data in a processor according to claim 6, wherein m is 32.   9. A method for writing data in a processor according to claim 8, wherein the rotation to the first position is a rightward 8-bit rotation.   9. A method for writing data in a processor according to claim 8, wherein the rotation to the first position is a 16-bit rotation to the right.   9. The method of writing data in the processor of claim 8, wherein the rotation to the first position is a 24-bit rotation to the right. A device for writing data in a processor, the data being stored in an internal register of the processor and written to an unaligned address in a storage device, the storage device being divided into a plurality of m-bit words by word boundaries; The device comprises a rotating device, a store combine register, and a selective shielding device,
The rotating device is coupled to the internal register, and rotates the data in the internal register to the first position by the write address of the unaligned data.
The store combine register is coupled to the rotator to store the rotator data for a while,
The selective shielding device is coupled to the rotating device and the store combine register, and the data of the rotating device and the store combine register is selectively shielded by the write address and written to the storage device. A device that writes data in the processor.   13. The apparatus for writing data in the processor according to claim 12, wherein the processor executes the first instruction to rotate the data in the internal register to the first position according to the write address of the data to the rotation device, and to perform the first rotation. Data is generated and stored in a store combine register, and a selective shielding device selectively shields the data in the rotating device and the store combine register according to the data write address and writes it to a storage device. A device that writes data in a processor.   13. The apparatus for writing data in a processor according to claim 12, wherein the processor executes a second instruction to cause the rotating device to capture subsequent data of the data and rotate it to a first position, wherein the second rotated data is Generating and saving in the store combine register, the selective shielding device combines the unwritten portion of the first rotation data and a part of the second rotation data according to the write address of the data, and writes it to the storage device A device for writing data in a processor, characterized by:   13. The apparatus for writing data in a processor as recited in claim 12, wherein the processor executes a third instruction to cause the rotating device to capture subsequent data of the data and rotate it to the first position, Generating and storing in the store combine register, and the selective shielding device combines the unwritten portion of the second rotation data and a part of the third rotation data according to the write address of the data, and writes it to the storage device A device for writing data in a processor, characterized by:   16. The apparatus for writing data in the processor according to claim 15, wherein the selective shielding device writes the unwritten portion of the third rotation data to the storage device in accordance with the data writing address. A device that writes data in the processor.   13. The apparatus for writing data in the processor according to claim 12, wherein m is 32.   18. The apparatus for writing data in the processor according to claim 17, wherein the rotating device rotates 8 bits to the right.   18. The apparatus for writing data in the processor according to claim 17, wherein the rotating apparatus rotates 16 bits to the right. 18. The apparatus for writing data in a processor according to claim 17, wherein the rotating device rotates 24 bits to the right.

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