JP2005260598A - Method for manufacturing pll control signal generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a PLL control signal generator which facilitates the manufacturing of a crystal oscillator. <P>SOLUTION: This PLL control signal generator is provided with: a reference frequency source comprising the crystal oscillator generating a reference frequency fr; and a PLL control element. The PLL control element comprises: a first frequency divider for dividing the frequency of the reference frequency to obtain a first division frequency; a phase comparator for comparing phase difference between the first division frequency and a second division frequency to generate a phase differential voltage; a lowpass filter for smoothing the phase differential voltage to obtain a control voltage Vc; a voltage-controlled oscillator whose oscillation frequency is changed by the control voltage Vc; and a second frequency divider for dividing the frequency of the oscillation frequency to obtain the second division frequency. When the division frequency ratios of the first and second frequency dividers are defined as q and p, an output frequency fout is determined by fout = (p/q)fr. In this manufacturing method, the first and second division frequency ratios q and p are set on the basis of an actually measured reference frequency frx after actually measuring the reference frequency fr after manufacturing the crystal oscillator. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a manufacturing method of a PLL control signal generator using a crystal oscillator as a reference signal source, and more particularly to a manufacturing method that facilitates manufacturing of a crystal oscillator.

BACKGROUND OF THE INVENTION A PLL control signal generator is applied as a high-frequency signal generator because it can maintain the frequency stability of a reference signal source and, for example, can increase an output frequency. One of these is a crystal oscillator as a reference signal source.

FIG. 2 is a block circuit diagram of a PLL control signal generator for explaining one conventional example.

  The PLL control signal generator includes a reference signal source 1 and a PLL control element 2 indicated by a dotted frame. The reference signal source 1 is composed of a crystal oscillator and generates a reference frequency fr. The PLL control element 2 includes a first frequency divider 3, a phase comparator 4, a low pass filter (LPF) 5, a voltage controlled oscillator (VCO) 6, a second frequency divider 7, and a third frequency divider 8. These are integrated (integrated with IC).

  The first frequency divider 3 divides the reference frequency fr by 1 / q to obtain a first frequency division frequency fq. The phase comparator 4 compares the phases of a first frequency division frequency fq and a second frequency division frequency fp described later to generate a phase difference voltage. The low-pass filter 5 smoothes the phase difference voltage to obtain the control voltage Vc.

  The voltage controlled oscillator 6 is formed by inserting a voltage variable capacitance element into an LC oscillation circuit (not shown), for example. And the oscillation frequency fv which changes according to the control voltage Vc applied to the voltage variable capacitance element is output. The second divider 7 divides the oscillation frequency fv by 1 / p to obtain a second divided frequency fp. The third frequency divider 8 divides the oscillation frequency by 1 / n to obtain an output frequency fout (third frequency division fn).

In such a case, the output frequency fout of the PLL control signal generator is determined by the following equation (1). As apparent from the following equation (1), if the frequency dividing ratio p of the second frequency divider 7 is increased and the frequency dividing ratio qn of the first and third frequency dividers 3 and 8 is decreased, the output frequency fout can be multiplied by p / nq times the reference frequency fr. Therefore, it is possible to obtain a high-frequency oscillator of, for example, 100 MHz or more, which is the limit of the crystal oscillator.
fout = {p / (qn)} fr (1)

  For example, if the output frequency fout is 832 MHz and the first to third frequency division ratios qpn are 64, 1, 1, the reference frequency fr is 13 MHz. Normally, based on these values, the PLL control element 2 and the crystal oscillator are manufactured and mounted on the set substrate.

  Then, in the case of a mass-produced product with a constant output frequency fout, the PLL control element 2 in which the first to third frequency division ratio qpn is fixed is manufactured. In addition, when the output frequency fout is arbitrary and the quantity is small, the PLL control element 2 is provided with a write terminal. Then, the first to third frequency division ratio qpn corresponding to the output frequency fout and the reference frequency fr are written.

(Problems of the prior art) However, in the PLL control signal generator configured as described above, the frequency accuracy of the output frequency fout depends on the reference frequency source in any case, so the standard for the crystal oscillator is strict. For example, a frequency accuracy of ± 3.6 ppm or less (−30 to + 70 ° C.) is generally required in the ± 30 KHz band communication system of 832 MHz, including frequency fluctuations due to frequency temperature characteristics and the like.

  From this, the initial deviation of the crystal oscillator with respect to the nominal value (nominal frequency) fro of the reference frequency fr is set within ± 1 ppm, for example. Therefore, it has been difficult to manufacture a crystal oscillator. The initial deviation of the crystal oscillator is a difference between the oscillation frequency (reference frequency fr) at a normal temperature of 25 ° C. after manufacture and the nominal frequency fro, and is represented by (fro−fr) / fro. The initial deviation of the output frequency fout in the PLL control signal generator naturally depends on the crystal oscillator.

The present invention provides a method of manufacturing a PLL control signal generator that facilitates the manufacture of a crystal oscillator.

  The present invention includes a reference frequency source including a crystal oscillator that generates a reference frequency fr and a PLL control element, as described in the claims (Claim 1), and the PLL control element includes at least the reference frequency. A first frequency divider that obtains a first divided frequency, and a phase comparator that compares the phase difference between the first divided frequency and the second divided frequency to generate a phase difference voltage; A low-pass filter that obtains a control voltage Vc by smoothing the phase difference voltage, a voltage-controlled oscillator whose oscillation frequency changes according to the control voltage Vc, and a second frequency that divides the oscillation frequency to obtain the second divided frequency. And a PLL control signal generator in which the output frequency fout is determined by fout = (p / q) fr, where q and p are the frequency dividing ratios of the first and second frequency dividers. The reference frequency after the crystal oscillator is manufactured. A manufacturing method in which the first and second frequency division ratios q and p are set based on the actually measured reference frequency frx after actually measuring the number fr.

  In such a manufacturing method, the first and second frequency division ratios q and p corresponding to the output frequency fout are set based on the actually measured reference frequency frx of the crystal oscillator. Therefore, it is not necessary to adjust the oscillation frequency (reference frequency fr) of the crystal oscillator to the given frequency. This facilitates the manufacture of the crystal oscillator.

  According to a second aspect of the present invention, the actual measurement reference frequency frx is a frequency measured after the crystal oscillator is mounted on the set substrate. As a result, the first and second frequency division ratios qn can be set including the frequency variation when the crystal oscillator is mounted. Therefore, the frequency stability of the PLL control signal generator can be increased.

  In the third aspect, the first and second frequency division ratios q and p are set by a signal from a write terminal provided in the PLL control element. Thus, it is not necessary to manufacture a PLL control element in which the frequency dividing ratios q and p are set in advance, which is suitable for a wide variety of PLL control signal generators.

  In the fourth aspect of the present invention, the PLL control signal generator has a third frequency divider for obtaining a third frequency as the output frequency fout in the voltage controlled oscillator, and the frequency division ratio of the third frequency divider is set. When n, the output frequency fout is fout = {p / (qn)} fr together with the frequency division ratios q and p and the reference frequency fr. This further increases the accuracy of the output frequency fout.

  FIG. 1 is a schematic manufacturing process diagram of a PLL control signal generator for explaining an embodiment of the present invention. In addition, description of the same part as a prior art example is simplified or abbreviate | omitted.

  Here, the output frequency fout as the target value of the PLL control signal generator is set to 832 MHz, for example. First, a “crystal oscillator manufacturing process” for manufacturing a crystal oscillator having a nominal value fro of a reference frequency fr of 13 MHz. Next, a “mounting process on the set substrate” in which the crystal oscillator is mounted on the set substrate constituting the PLL control signal generator by so-called reflow in which a high-temperature furnace is conveyed and soldered.

  Then, an “oscillation frequency measurement process” that actually measures the oscillation frequency (reference frequency) fr of the crystal oscillator. For convenience, this will be referred to as an actually measured reference frequency frx. As a result, it is assumed that the actually measured reference frequency frx is 13.1 MHz, for example. In this case, the frequency deviation (frx−fro) / fr with respect to the nominal value fro of the actually measured reference frequency fr is +7692.3 ppm.

  Next, the frequency division ratio qpn of the first to third frequency dividers 3, 7, and 8 is set based on the actually measured reference frequency frx (13.1 MHz). These are set by a digital signal from the write terminal of the PLL control element 2. For example, when n = 1, q = 131 and p = 8320. As a result, the output frequency fo of the PLL control signal generator becomes 832 MHz as the target value. Therefore, even if the reference frequency fr of the crystal oscillator deviates from the nominal value fro, the initial deviation of the output frequency fout can be set to 0 ppm.

  Further, when the measured reference frequency frx of the crystal oscillator is 13.100013 MHz (frequency deviation with respect to the nominal value fro + 7693.3 ppm), if each frequency division ratio qpn is set to q = 88, p = 5589, n = 1, the PLL The output frequency fout of the control signal generator is 831.999689 MHz. Even in this case, the initial deviation of the output frequency fout with respect to the target value (832 MHz) is only −0.37 ppm, which is significantly less than ± 1 ppm of the normal standard. Since each frequency division ratio qpn is an integer value, an error occurs. Since this error depends on the frequency division ratio, the frequency divider may be designed within a desired error range.

  In this way, the crystal oscillator is mounted on the set substrate, and each frequency division ratio qpn is set after actually measuring the oscillation frequency (reference frequency fr). Therefore, the initial deviation of the output frequency fout in the PLL control signal generator can be reliably within ± 1 ppm. As a result, the target output frequency fout is set by each frequency division ratio qpn, so that frequency adjustment at the time of manufacturing the reference oscillator becomes unnecessary. Therefore, the manufacture of the crystal oscillator is facilitated. Also, an expensive frequency adjusting device can be saved.

  In this example, after the crystal oscillator is fixed (mounted) to the set substrate with solder or the like, the oscillation frequency (reference frequency fr) is measured. Accordingly, since the reference frequency fr is the oscillation frequency of the reference oscillator measured after mounting, it is possible to correct the frequency fluctuation due to the mounting of the reference oscillator and the frequency fluctuation due to the deviation from the specified value of the power load of each set substrate. From this, it is possible to easily achieve the frequency accuracy of ± 3.6 ppm or less of the PLL control signal generator.

(Other matters) In the above embodiment, the PLL control signal generator provided with the third frequency divider 8 is used, but the same effect can be obtained without the third frequency divider 8. Further, the crystal oscillator is measured after being mounted on the set substrate, but may be measured after being manufactured and before being mounted. However, since frequency fluctuation occurs after mounting, it is preferable after mounting.

It is a manufacturing-process figure of the PLL control signal generator explaining one Example of this invention. It is a block diagram of a PLL control signal generator for explaining a conventional example.

Explanation of symbols

  1 reference signal source, 2 PLL control element, 3, 7, 8 frequency divider, 4 phase comparator, 5 low pass filter, 6 voltage controlled oscillator.

Claims (4)

  A reference frequency source including a crystal oscillator that generates a reference frequency fr, and a PLL control element, and the PLL control element includes at least a first frequency divider that obtains a first frequency by dividing the reference frequency; A phase comparator that compares the phase difference between the first divided frequency and the second divided frequency to generate a phase difference voltage; a low-pass filter that smoothes the phase difference voltage to obtain a control voltage Vc; A voltage-controlled oscillator whose oscillation frequency is changed by a control voltage Vc; and a second divider that divides the oscillation frequency to obtain the second divided frequency, and is divided by the first and second dividers. In a PLL control signal generator in which the output frequency fout is determined by fout = (p / q) fr, where the frequency ratio is q and p, after the reference frequency fr is actually measured after the crystal oscillator is manufactured. Based on the measured reference frequency frx A method of manufacturing a PLL control signal generator, wherein the first and second frequency division ratios q and p are set.   2. The method of manufacturing a PLL control signal generator according to claim 1, wherein the actually measured reference frequency frx is a frequency measured after the crystal oscillator is mounted on a set substrate.   2. The method of manufacturing a PLL control signal generator according to claim 1, wherein the first and second frequency division ratios q and p are set by a signal from a write terminal provided in the PLL control element.   The PLL control signal generator has a third divider for obtaining a third divided frequency as the output frequency fout in the voltage controlled oscillator, and when the dividing ratio of the third divider is n, 2. The method of manufacturing a PLL control signal generator according to claim 1, wherein the output frequency fout is fout = {p / (qn)} fr together with the frequency division ratios q and p and the reference frequency fr.

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