CN114172510A - Frequency calibration method of phase-locked loop and phase-locked loop circuit - Google Patents

Frequency calibration method of phase-locked loop and phase-locked loop circuit Download PDF

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Publication number
CN114172510A
CN114172510A CN202111539104.6A CN202111539104A CN114172510A CN 114172510 A CN114172510 A CN 114172510A CN 202111539104 A CN202111539104 A CN 202111539104A CN 114172510 A CN114172510 A CN 114172510A
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China
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frequency
voltage
controlled oscillator
phase
output
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张健
朱正伦
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Hangzhou Shengde Micro Integrated Circuit Technology Co ltd
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Beijing Shengde Micro Integrated Circuit Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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Abstract

The invention discloses a frequency calibration method of a phase-locked loop and a phase-locked loop circuit, wherein the method comprises the following steps: acquiring the output frequency of a voltage-controlled oscillator in a phase-locked loop in the power-on process of the phase-locked loop; calibrating the output frequency of the voltage-controlled oscillator according to the target frequency value, so that the difference value between the output frequency of the voltage-controlled oscillator and the target frequency value is smaller than a preset threshold value; acquiring the output frequency of a voltage-controlled oscillator in the working process of a phase-locked loop; and calibrating the output frequency of the voltage-controlled oscillator according to the target frequency interval so as to enable the output frequency of the voltage-controlled oscillator to be located in the target frequency interval. The invention can simultaneously ensure the calibration performance and the calibration time of the system, can also realize the accurate control of the system parameters, and greatly improves the stability and the reliability of the phase-locked loop circuit.

Description

Frequency calibration method of phase-locked loop and phase-locked loop circuit
Technical Field
The invention relates to the technical field of power electronics, in particular to a frequency calibration method of a phase-locked loop and a phase-locked loop circuit.
Background
In general, telecommunication, computer and other digital electronic applications have very strict timing requirements on their components so that an electronic or computer can perform very precise operations. A Phase Locked Loop (PLL) circuit capable of generating a stable frequency and synchronizing an output signal with a reference signal is a widely used circuit in an electronic control system. The Phase-locked Loop circuit is composed of a Phase-Frequency Detector (PFD), a Charge Pump (CP), a Loop Filter (LF), a Voltage Controlled Oscillator (VCO), and a Frequency Divider (Divider).
When the phase-locked loop circuit works, the voltage-controlled oscillator has frequency drift of different degrees due to the environmental influences of manufacturing procedures, temperature and the like, although the frequency can be accurately locked at a target frequency when the phase-locked loop circuit works, the voltage value of the loop filter can be accordingly locked on different voltage values, so that the parameters of the phase-locked loop circuit are changed, the overall performance of the phase-locked loop circuit is deteriorated, and even the phase-locked loop circuit is unlocked.
At present, in order to suppress frequency variation of a phase-locked loop circuit in operation, two methods are generally adopted, one method is to design a larger working frequency range of a voltage-controlled oscillator in the phase-locked loop circuit, but the method has the defects that the design difficulty of the voltage-controlled oscillator is brought, the control voltage of the phase-locked loop circuit is difficult to control when the phase-locked loop circuit is locked due to the fact that the frequency of the voltage-controlled oscillator cannot be accurately controlled, and system performance is deteriorated due to the influence on system parameters. Another method is to select a reasonable operating state of the voltage controlled oscillator through frequency calibration, but the conventional calibration scheme cannot simultaneously consider both the calibration performance and the calibration time.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a frequency calibration method of a phase-locked loop and a phase-locked loop circuit, which can simultaneously ensure the calibration performance and the calibration time of a system by respectively calibrating the phase-locked loop circuit in the starting and working states, and simultaneously can realize the accurate control of system parameters, thereby greatly improving the stability, the reliability and the related performance parameters of the phase-locked loop circuit.
According to a first aspect of the present disclosure, there is provided a frequency calibration method for a phase-locked loop, including: acquiring the output frequency of a voltage-controlled oscillator in a phase-locked loop in the power-on process of the phase-locked loop;
calibrating the output frequency of the voltage-controlled oscillator according to a target frequency value, so that the difference value between the output frequency of the voltage-controlled oscillator and the target frequency value is smaller than a preset threshold value;
acquiring the output frequency of the voltage-controlled oscillator in the working process of the phase-locked loop;
and calibrating the output frequency of the voltage-controlled oscillator according to a target frequency interval so that the output frequency of the voltage-controlled oscillator is within the target frequency interval.
Optionally, the method for acquiring the output frequency of the voltage-controlled oscillator in the phase-locked loop includes:
counting rising edges or falling edges of output signals of the voltage-controlled oscillator within preset time;
and calculating according to the count value to obtain the output frequency of the voltage-controlled oscillator.
Optionally, calibrating the output frequency of the voltage-controlled oscillator according to the target frequency value includes:
comparing the output frequency of the voltage controlled oscillator to the target frequency value;
if the output frequency of the voltage-controlled oscillator is smaller than the target frequency value, the output frequency of the voltage-controlled oscillator is increased;
and if the output frequency of the voltage-controlled oscillator is not less than the target frequency value, ending the calibration.
Optionally, the increase amount of the output frequency of the voltage-controlled oscillator each time is less than or equal to the preset threshold.
Optionally, the target frequency value is a target locking frequency of the phase-locked loop.
Optionally, calibrating the output frequency of the voltage-controlled oscillator according to the target frequency interval includes:
comparing the output frequency of the voltage-controlled oscillator with a target upper limit frequency value and a target lower limit frequency value corresponding to the target frequency interval respectively;
if the output frequency of the voltage-controlled oscillator is greater than the target upper limit frequency value, the output frequency of the voltage-controlled oscillator is reduced;
if the output frequency of the voltage-controlled oscillator is smaller than the target lower limit frequency value, the output frequency of the voltage-controlled oscillator is increased;
and if the output frequency of the voltage-controlled oscillator is smaller than the target upper limit frequency value and larger than the target lower limit frequency value, ending the calibration.
Optionally, the amount of adjustment of the output frequency of the voltage-controlled oscillator is less than or equal to the preset threshold.
According to a second aspect of the present disclosure, there is provided a phase-locked loop circuit including: the voltage-controlled oscillator is used for outputting a frequency signal according to the voltage control signal;
the frequency divider is connected with the voltage-controlled oscillator and is used for dividing the frequency of the frequency signal;
the phase frequency detector is connected with the frequency divider and used for generating a pulse modulation signal according to the reference frequency signal and the frequency-divided frequency signal;
the charge pump is connected with the phase frequency detector and is used for generating a current pulse signal according to the pulse modulation signal;
the loop filter is respectively connected with the charge pump and the voltage-controlled oscillator and is used for generating the voltage control signal according to the current pulse signal; and
and the frequency calibration circuit is used for acquiring the frequency value of the frequency signal output by the voltage-controlled oscillator and calibrating the frequency signal output by the voltage-controlled oscillator in the power-on process of the phase-locked loop circuit and the working process of the phase-locked loop circuit respectively.
Optionally, the frequency calibration circuit calibrates the frequency signal output by the voltage-controlled oscillator according to a target frequency value in a power-up process of the phase-locked loop circuit, and calibrates the frequency signal output by the voltage-controlled oscillator according to a target frequency interval in a working process of the phase-locked loop circuit.
Optionally, the frequency calibration circuit comprises:
the counting unit is used for counting rising edges or falling edges of the frequency signals output by the voltage-controlled oscillator within preset time so as to obtain frequency values of the frequency signals output by the voltage-controlled oscillator;
the digital comparison unit is connected with the counting unit and used for comparing the frequency value of the frequency signal output by the voltage-controlled oscillator with a target value and generating an adjusting signal according to the comparison result;
and the digital signal processing unit is respectively connected with the digital comparison unit and the voltage-controlled oscillator and is used for increasing or decreasing the frequency value of the frequency signal output by the voltage-controlled oscillator according to the adjusting signal.
Optionally, during the power-up process of the phase-locked loop circuit, the digital signal processing unit increases the frequency value of the frequency signal output by the voltage-controlled oscillator when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjustment signal is smaller than the target value, and keeps the frequency value of the frequency signal output by the voltage-controlled oscillator unchanged when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjustment signal is not smaller than the target value,
wherein the target value is a target locking frequency of the phase-locked loop.
Optionally, in a working process of the phase-locked loop circuit, the target value is a target upper limit frequency value and a target lower limit frequency value corresponding to the target frequency interval; and the digital signal processing unit reduces the frequency value of the frequency signal output by the voltage-controlled oscillator when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjusting signal is greater than the target upper limit frequency value, increases the frequency value of the frequency signal output by the voltage-controlled oscillator when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjusting signal is less than the target lower limit frequency value, and keeps the frequency value of the frequency signal output by the voltage-controlled oscillator unchanged when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjusting signal is less than the target upper limit frequency value and greater than the target lower limit frequency value.
The beneficial effects of the invention at least comprise:
according to the frequency calibration method of the phase-locked loop and the phase-locked loop circuit, in the process of carrying out first calibration on the frequency signal output by the voltage-controlled oscillator according to the target frequency value in the power-on process of the phase-locked loop circuit, the frequency value of the frequency signal is increased to be equal to or larger than the target frequency value for the first time according to the comparison result of the frequency value (namely, the output frequency) of the frequency signal and the target frequency value, so that the desired frequency signal can be obtained, and the required calibration time is short; in the process of calibrating the frequency signal output by the voltage-controlled oscillator for the second time according to the target frequency interval in the working process of the phase-locked loop circuit, the frequency value of the frequency signal only needs to be adjusted in a small-range frequency interval in real time to ensure that the frequency signal is located in the target frequency interval, the required calibration time is short, and meanwhile, the problem of frequency deviation of the voltage-controlled oscillator caused by different working environments after the phase-locked loop is powered on and started can be effectively solved, so that the calibration performance and the calibration time of the phase-locked loop system/circuit are simultaneously ensured, the accurate control of the parameters of the phase-locked loop system is realized, and the stability and the reliability of the phase-locked loop system are greatly improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
Fig. 1 is a schematic diagram illustrating a phase-locked loop circuit according to an embodiment of the present invention;
FIG. 2 shows a schematic diagram of the frequency calibration circuit of FIG. 1;
fig. 3 is a schematic flowchart illustrating a method for calibrating a frequency of a phase-locked loop according to an embodiment of the present invention;
fig. 4 is a schematic flowchart illustrating a method for calibrating a frequency during a phase-locked loop boot process according to an embodiment of the present invention;
fig. 5 is a schematic flowchart illustrating a method for calibrating a frequency during operation of a phase-locked loop according to an embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
As shown in fig. 1, a phase-locked loop circuit disclosed in the embodiment of the present invention includes: a phase frequency detector 10, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, a frequency divider 50, and a frequency calibration circuit 60.
The voltage-controlled oscillator 40 is configured to output a corresponding frequency signal according to the voltage control signal. Illustratively, the voltage-controlled oscillator 40 is provided with a capacitor array, and the frequency of the output signal of the voltage-controlled oscillator 40 (which may be simply referred to as the output frequency herein) may be adjusted by adjusting the capacitor array.
The frequency divider 50 is connected to the voltage-controlled oscillator 40 and is configured to divide the frequency signal output by the voltage-controlled oscillator 40. Illustratively, the frequency divider 50 functions to convert an input frequency signal, i.e., the frequency signal output by the voltage-controlled oscillator 40, into a frequency of the same frequency or lower frequency according to an input frequency dividing ratio, and then output the converted frequency signal. The input and output of the frequency divider 50 satisfy the following relationship:
Fin＝ratio*Fout...........................................(1)，
where Fin is the frequency signal input to the frequency divider 50, i.e., the frequency signal output by the voltage-controlled oscillator 40, Fout is the frequency signal output by the frequency divider 50, and ratio is the frequency division ratio of the frequency divider 50. In a phase-locked loop system, for example, different frequency outputs may be achieved by varying the division ratio input to the divider 50.
The phase frequency detector 10 is connected to the frequency divider 50 for generating a pulse modulation signal according to the reference frequency signal REF and the frequency divided frequency signal. A first input terminal of the phase frequency detector 10 receives a reference frequency signal REF (which may be provided by a reference frequency oscillator such as a crystal oscillator), a second input terminal of the phase frequency detector 10 receives a frequency divided signal output by the frequency divider 50, and the phase frequency detector 10 generates pulse modulation signals (denoted as up and dn) with different widths according to a phase difference between two input signals. If the phase of the reference frequency signal leads the phase of the divided frequency signal, the pulse modulated signal up output is valid; the pulse modulated signal dn output is valid if the phase of the reference frequency signal lags the phase of the divided frequency signal.
The charge pump 20 is connected to the phase frequency detector 10 for generating a current pulse signal according to the pulse modulation signal. Illustratively, the charge pump 20 includes a first inverter, a second inverter, an operational amplifier, a first controllable switch, a second controllable switch, a third controllable switch and a fourth controllable switch, wherein an input terminal of the first inverter is connected to the pulse modulation signal up and a control terminal of the fourth controllable switch, an output terminal of the first inverter is connected to the control terminal of the first controllable switch, an input terminal of the second inverter is connected to the pulse modulation signal dn and the control terminal of the second controllable switch, an output terminal of the second inverter is connected to the control terminal of the third controllable switch, a first terminal of the fourth controllable switch and the first terminal of the first controllable switch are commonly connected to a first current source, a second terminal of the first controllable switch is connected to the first terminal of the third controllable switch and the output terminal of the operational amplifier, an output terminal of the operational amplifier is further connected to an inverting input terminal of the operational amplifier, a second terminal of the fourth controllable switch, The non-inverting input terminal of the operational amplifier and the first terminal of the second controllable switch are connected in common to form the output terminal of the charge pump 20, and the second terminal of the second controllable switch and the second terminal of the third controllable switch are connected in common to the second current source. The charge pump 20 controls the inflow and outflow of the charging current through the pulse modulation signals up and dn, when the pulse modulation signal up is high, the fourth controllable switch is closed, the first controllable switch is opened, the current output by the first current source passes through the fourth controllable switch and flows out through the output end of the charge pump 20, when the pulse modulation signal dn is high, the second controllable switch is closed, the third controllable switch is opened, and the current of the second current source passes through the second controllable switch and flows in through the output end of the charge pump 20.
The loop filter 30 is connected to the charge pump 20 and the voltage controlled oscillator 40, respectively, for generating a voltage control signal to the voltage controlled oscillator 40 according to the current pulse signal. Illustratively, the loop filter 30 is configured to output the voltage control signal after low-pass filtering the current pulse signal.
The frequency calibration circuit 60 is configured to obtain a frequency value of the frequency signal output by the voltage-controlled oscillator 40, and calibrate the frequency signal output by the voltage-controlled oscillator 40 in the power-on process of the phase-locked loop circuit and the working process of the phase-locked loop circuit, respectively. Specifically, in this embodiment, the frequency calibration circuit 60 calibrates the frequency signal output by the voltage-controlled oscillator 40 according to the target frequency value in the power-on process of the phase-locked loop circuit; in the operation process of the phase-locked loop circuit, the frequency signal output by the voltage-controlled oscillator 40 is calibrated according to the target frequency interval.
Exemplarily, in the present embodiment, as shown in fig. 2, the frequency calibration circuit 60 further includes: a counting unit 61, a digital comparing unit 62 and a digital signal processing unit 63.
The counting unit 61 is configured to count the number (denoted as n) of rising edges or falling edges of the frequency signal output by the voltage controlled oscillator 40 within a preset time (denoted as t) to obtain a frequency value of the frequency signal output by the voltage controlled oscillator 40. It will be appreciated that the frequency signal output by the voltage controlled oscillator 40 has a frequency value (denoted f) equal to n/t.
The digital comparison unit 62 is connected to the counting unit 61, and is configured to compare the frequency value of the frequency signal output by the voltage-controlled oscillator 40 with a target value, and generate an adjustment signal according to the comparison result. Optionally, the digital comparing unit 62 may determine a magnitude relationship between the frequency value of the frequency signal output by the voltage-controlled oscillator 40 and the target value by comparing the count value of the counting unit 61 with the count value corresponding to the target frequency value within the preset time, and generate a corresponding adjusting signal, or may first calculate and obtain the frequency value of the frequency signal output by the voltage-controlled oscillator 40 according to the count value of the counting unit 61, and then directly compare the magnitude relationship between the calculated frequency value and the target frequency value, and generate a corresponding adjusting signal, which is not limited in this disclosure.
The digital signal processing unit 63 is respectively connected to the digital comparing unit 62 and the voltage-controlled oscillator 40, and is configured to increase or decrease the frequency value of the frequency signal output by the voltage-controlled oscillator 40 according to the adjustment signal.
Alternatively, the digital signal processing unit 63 may increase or decrease the frequency value of the frequency signal output by the voltage-controlled oscillator 40 by changing the frequency dividing ratio input to the frequency divider 50 and/or by adjusting the capacitor array in the voltage-controlled oscillator 40.
Specifically, in this embodiment, in the power-on process of the pll circuit, the target value is the target locking frequency of the pll circuit. At this time, the digital signal processing unit 63 adjusts the frequency value of the frequency signal output by the voltage controlled oscillator 40 by the first step length when the frequency value of the adjustment signal output by the digital comparing unit 62 representing the frequency signal output by the voltage controlled oscillator 40 is smaller than the target value, and keeps the frequency value of the frequency signal output by the voltage controlled oscillator 40 unchanged (i.e., does not adjust the frequency value of the frequency signal output by the voltage controlled oscillator 40) when the frequency value of the adjustment signal output by the digital comparing unit 62 representing the frequency signal output by the voltage controlled oscillator 40 is not smaller than the target value. Because the frequency value of the frequency signal output by the voltage-controlled oscillator 40 is increased from zero in the process of powering on and starting up the phase-locked loop circuit, in the process, the frequency value of the frequency signal is only required to be increased to be equal to or larger than the target frequency value for the first time according to the comparison result of the frequency value of the frequency signal and the target frequency value, so that the desired frequency signal can be obtained, and the required calibration time is short.
In this embodiment, the first step length is smaller than a preset threshold. In this way, when the frequency value of the frequency signal output by the voltage controlled oscillator 40 is adjusted at a certain time so that the frequency value of the frequency signal is greater than the target frequency value for the first time, the difference between the frequency value of the frequency signal output by the voltage controlled oscillator 40 and the target frequency value can be smaller than the preset threshold.
Further, in the working process of the phase-locked loop circuit, the target value is a target upper limit frequency value and a target lower limit frequency value corresponding to the target frequency interval. The digital signal processing unit 63 adjusts the frequency value of the frequency signal output by the voltage-controlled oscillator 40 by the second step length when the adjustment signal output by the digital comparing unit 62 indicates that the frequency value of the frequency signal output by the voltage-controlled oscillator 40 is greater than the target upper limit frequency value. And when the frequency value of the frequency signal output by the voltage-controlled oscillator 40 is smaller than the target lower limit frequency value, the frequency value of the frequency signal output by the voltage-controlled oscillator 40 is adjusted according to the third step length. And when the frequency value of the frequency signal output by the voltage-controlled oscillator 40 is smaller than the target upper limit frequency value and larger than the target lower limit frequency value, the adjustment signal output by the digital comparison unit 62 keeps the frequency value of the frequency signal output by the voltage-controlled oscillator 40 unchanged. It can be understood that, compared with the case that a fixed frequency value is set as a comparison parameter in the working process of the phase-locked loop circuit, in the embodiment of the present invention, a frequency interval in a small range is used as a comparison parameter when the frequency signal is calibrated, and it is only necessary to adjust the frequency value of the frequency signal in the frequency interval in the small range in real time to ensure that the frequency signal is located in a target frequency interval, so that the calibration performance of the phase-locked loop can be improved by effectively solving the problem of frequency offset caused by different working environments of the voltage-controlled oscillator after the phase-locked loop is powered on and started up, and the required calibration time is shorter.
In this embodiment, both the second stepping length and the third stepping length are smaller than a preset threshold. Thus, when the frequency value of the frequency signal output by the voltage controlled oscillator 40 is increased or decreased at a certain time so that the frequency value of the frequency signal is within the target frequency interval for the first time, the difference between the frequency value of the frequency signal output by the voltage controlled oscillator 40 and the upper limit value or the lower limit value of the target frequency interval can be smaller than the preset threshold value.
Based on the above description, it can be seen that the embodiments of the present invention distribute the calibration process of the frequency signal output by the phase-locked loop circuit (system) in different working time slots of the system, including the first calibration with higher accuracy performed during the power-on and power-on processes of the system, and the second calibration with lower accuracy performed during the working processes of the system, so as to better meet the requirements of the phase-locked loop system on calibration performance and calibration time, implement accurate control of the parameters of the phase-locked loop system, and further greatly improve the stability and reliability of the phase-locked loop system.
Further, the invention also discloses a frequency calibration method of the phase-locked loop, which can be applied to the phase-locked loop circuit shown in fig. 1 and fig. 2. As shown in fig. 3, in this embodiment, the method for calibrating the frequency of the phase-locked loop includes the following steps:
in step S1, the output frequency of the voltage controlled oscillator in the phase-locked loop is obtained during the phase-locked loop power-up process.
In this embodiment, step S1 further includes: counting the number of rising edges or falling edges of output signals of the voltage-controlled oscillator within preset time in the power-on process of the phase-locked loop; and calculating according to the count value to obtain the output frequency of the voltage-controlled oscillator.
In one possible embodiment of the present invention, the ratio of the count value to the predetermined time may be used to represent the output frequency of the voltage-controlled oscillator, and the target value subsequently used as the comparison parameter should also be the frequency parameter. In another possible embodiment of the present invention, the count value may also be directly used to represent the output frequency of the voltage-controlled oscillator, and further, the target value as the comparison parameter should be the corresponding count value.
In step S2, the output frequency of the voltage controlled oscillator is calibrated according to the target frequency value, so that the difference between the output frequency of the voltage controlled oscillator and the target frequency value is smaller than a preset threshold.
In this embodiment, referring to fig. 4, step S2 further includes: comparing the output frequency of the voltage-controlled oscillator with the target frequency value to determine whether the output frequency of the voltage-controlled oscillator is greater than or equal to the target frequency value (step S21); if the output frequency of the voltage-controlled oscillator is less than the target frequency value, adjusting the output frequency of the voltage-controlled oscillator according to a first step length (step S22); if the output frequency of the voltage-controlled oscillator is not less than the target frequency value, the calibration is ended (step S23). And the target frequency value is the target locking frequency of the phase-locked loop. Reference is made to the foregoing description of the digital signal processing unit 63 for understanding, and the description thereof is omitted here.
Further, the adjustment amount of the output frequency of the voltage-controlled oscillator each time, namely the first step length, is smaller than or equal to a preset threshold value.
In step S3, the output frequency of the voltage controlled oscillator is obtained during the operation of the phase locked loop.
In this embodiment, step S3 further includes: counting the number of rising edges or falling edges of output signals of the voltage-controlled oscillator within preset time in the working process of the phase-locked loop; and calculating according to the count value to obtain the output frequency of the voltage-controlled oscillator.
In one possible embodiment of the present invention, the ratio of the count value to the predetermined time may be used to represent the output frequency of the voltage-controlled oscillator, and the target value subsequently used as the comparison parameter should also be the frequency parameter. In another possible embodiment of the present invention, the count value may also be directly used to represent the output frequency of the voltage-controlled oscillator, and further, the target value as the comparison parameter should be the corresponding count value.
In step S4, the output frequency of the voltage controlled oscillator is calibrated according to the target frequency interval so that the output frequency of the voltage controlled oscillator is within the target frequency interval.
In this embodiment, referring to fig. 5, step S4 further includes: comparing the output frequency of the voltage-controlled oscillator with a target upper limit frequency value and a target lower limit frequency value corresponding to the target frequency interval, respectively, to determine whether the output frequency of the voltage-controlled oscillator is greater than the target upper limit frequency value (step S41); if the output frequency of the voltage-controlled oscillator is greater than the target upper limit frequency value, adjusting the output frequency of the voltage-controlled oscillator according to a second step length (step S42), otherwise, continuously judging whether the output frequency of the voltage-controlled oscillator is less than the target lower limit frequency value (step S43); if the output frequency of the voltage-controlled oscillator is less than the target lower limit frequency value, adjusting the output frequency of the voltage-controlled oscillator according to a third step length (step S44); if the output frequency of the voltage controlled oscillator is less than the target upper limit frequency value and greater than the target lower limit frequency value, the calibration is ended (step S45). Reference is made to the foregoing description of the digital signal processing unit 63 for understanding, and the description thereof is omitted here.
Further, the adjustment-down amount, i.e. the second step length, and the adjustment-up amount, i.e. the third step length, of the output frequency of the voltage-controlled oscillator each time are less than or equal to a preset threshold value.
To sum up, in the process of performing the first calibration on the frequency signal output by the voltage-controlled oscillator according to the target frequency value in the power-on process of the phase-locked loop circuit, the frequency value of the frequency signal is increased to be equal to or greater than the target frequency value for the first time according to the comparison result between the frequency value (i.e., the output frequency) of the frequency signal and the target frequency value, so that the desired frequency signal can be obtained, and the required calibration time is short; in the process of calibrating the frequency signal output by the voltage-controlled oscillator for the second time according to the target frequency interval in the working process of the phase-locked loop circuit, the frequency value of the frequency signal only needs to be adjusted in a small-range frequency interval in real time to ensure that the frequency signal is located in the target frequency interval, the required calibration time is short, and meanwhile, the problem of frequency deviation of the voltage-controlled oscillator caused by different working environments after the phase-locked loop is powered on and started can be effectively solved, so that the calibration performance and the calibration time of the phase-locked loop system/circuit are simultaneously ensured, the accurate control of the parameters of the phase-locked loop system is realized, and the stability and the reliability of the phase-locked loop system are greatly improved.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims (12)

1. A method for frequency calibration of a phase locked loop, comprising:
acquiring the output frequency of a voltage-controlled oscillator in a phase-locked loop in the power-on process of the phase-locked loop;
calibrating the output frequency of the voltage-controlled oscillator according to a target frequency value, so that the difference value between the output frequency of the voltage-controlled oscillator and the target frequency value is smaller than a preset threshold value;
acquiring the output frequency of the voltage-controlled oscillator in the working process of the phase-locked loop;
and calibrating the output frequency of the voltage-controlled oscillator according to a target frequency interval so that the output frequency of the voltage-controlled oscillator is within the target frequency interval.
2. The method for frequency calibration of a phase locked loop of claim 1, wherein the method for obtaining the output frequency of the voltage controlled oscillator in the phase locked loop comprises:
counting rising edges or falling edges of output signals of the voltage-controlled oscillator within preset time;
and calculating according to the count value to obtain the output frequency of the voltage-controlled oscillator.
3. The method of frequency calibration of a phase locked loop of claim 1, wherein calibrating the output frequency of the voltage controlled oscillator according to a target frequency value comprises:
comparing the output frequency of the voltage controlled oscillator to the target frequency value;
if the output frequency of the voltage-controlled oscillator is smaller than the target frequency value, the output frequency of the voltage-controlled oscillator is increased;
and if the output frequency of the voltage-controlled oscillator is not less than the target frequency value, ending the calibration.
4. The method for frequency calibration of a phase-locked loop according to claim 3, wherein the increase of the output frequency of the voltage-controlled oscillator is less than or equal to the preset threshold each time.
5. The method for frequency calibration of a phase locked loop according to any of claims 1-4, wherein the target frequency value is a target locking frequency of the phase locked loop.
6. The method for frequency calibration of a phase locked loop of claim 1, wherein calibrating the output frequency of the voltage controlled oscillator according to the target frequency interval comprises:
comparing the output frequency of the voltage-controlled oscillator with a target upper limit frequency value and a target lower limit frequency value corresponding to the target frequency interval respectively;
if the output frequency of the voltage-controlled oscillator is greater than the target upper limit frequency value, the output frequency of the voltage-controlled oscillator is reduced;
if the output frequency of the voltage-controlled oscillator is smaller than the target lower limit frequency value, the output frequency of the voltage-controlled oscillator is increased;
and if the output frequency of the voltage-controlled oscillator is smaller than the target upper limit frequency value and larger than the target lower limit frequency value, ending the calibration.
7. The method for calibrating the frequency of the phase-locked loop according to claim 6, wherein the amount of the output frequency of the voltage-controlled oscillator that is adjusted up and down each time is less than or equal to the preset threshold.
8. A phase locked loop circuit, comprising:
the voltage-controlled oscillator is used for outputting a frequency signal according to the voltage control signal;
the frequency divider is connected with the voltage-controlled oscillator and is used for dividing the frequency of the frequency signal;
the phase frequency detector is connected with the frequency divider and used for generating a pulse modulation signal according to the reference frequency signal and the frequency-divided frequency signal;
the charge pump is connected with the phase frequency detector and is used for generating a current pulse signal according to the pulse modulation signal;
the loop filter is respectively connected with the charge pump and the voltage-controlled oscillator and is used for generating the voltage control signal according to the current pulse signal; and
and the frequency calibration circuit is used for acquiring the frequency value of the frequency signal output by the voltage-controlled oscillator and calibrating the frequency signal output by the voltage-controlled oscillator in the power-on process of the phase-locked loop circuit and the working process of the phase-locked loop circuit respectively.
9. The phase-locked loop circuit of claim 8, wherein the frequency calibration circuit calibrates the frequency signal output by the voltage-controlled oscillator according to a target frequency value during a power-up process of the phase-locked loop circuit, and calibrates the frequency signal output by the voltage-controlled oscillator according to a target frequency interval during an operation of the phase-locked loop circuit.
10. The phase locked loop circuit of claim 9, wherein the frequency calibration circuit comprises:
the counting unit is used for counting rising edges or falling edges of the frequency signals output by the voltage-controlled oscillator within preset time so as to obtain frequency values of the frequency signals output by the voltage-controlled oscillator;
the digital comparison unit is connected with the counting unit and used for comparing the frequency value of the frequency signal output by the voltage-controlled oscillator with a target value and generating an adjusting signal according to the comparison result;
and the digital signal processing unit is respectively connected with the digital comparison unit and the voltage-controlled oscillator and is used for increasing or decreasing the frequency value of the frequency signal output by the voltage-controlled oscillator according to the adjusting signal.
11. The phase-locked loop circuit of claim 10, wherein during a power-up procedure of the phase-locked loop circuit, the digital signal processing unit increases the frequency value of the frequency signal output by the voltage-controlled oscillator when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjustment signal is less than the target value, and maintains the frequency value of the frequency signal output by the voltage-controlled oscillator unchanged when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjustment signal is not less than the target value,
wherein the target value is a target locking frequency of the phase-locked loop.
12. The phase-locked loop circuit according to claim 10, wherein during operation of the phase-locked loop circuit, the target values are target upper limit frequency values and target lower limit frequency values corresponding to the target frequency interval; and the digital signal processing unit reduces the frequency value of the frequency signal output by the voltage-controlled oscillator when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjusting signal is greater than the target upper limit frequency value, increases the frequency value of the frequency signal output by the voltage-controlled oscillator when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjusting signal is less than the target lower limit frequency value, and keeps the frequency value of the frequency signal output by the voltage-controlled oscillator unchanged when the frequency value of the frequency signal output by the voltage-controlled oscillator represented by the adjusting signal is less than the target upper limit frequency value and greater than the target lower limit frequency value.
CN202111539104.6A 2021-12-15 2021-12-15 Frequency calibration method of phase-locked loop and phase-locked loop circuit Pending CN114172510A (en)

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