JP2005259865A - Semiconductor device, method for manufacturing the same and optoelectronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device containing a structure capable of enhancing the reliability of a semiconductor layer. <P>SOLUTION: The semiconductor device comprises a semiconductor layer 1a which is formed on a substrate 10A through middle layers 11, 12 at a given pattern. Regarding a surface roughness of the middle layer 12 arranged just under the semiconductor layer 1a, a difference in height between a projective top and a recess bottom in one cycle of a an uneven profile is 40 nm or less. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an electro-optical device.

2. Description of the Related Art Conventionally, electro-optical devices such as liquid crystal display devices that include a semiconductor device as a switching element are known. As such a semiconductor device, for example, a thin film transistor having a structure in which a semiconductor film having a source region and a drain region is formed on a substrate is known. Is disclosed, for example, in Japanese Patent Application Laid-Open No. H10-228707.
JP-A-7-181517

  When the light shielding layer is formed in order to prevent or suppress the light irradiation to the semiconductor layer as in Patent Document 1, a semiconductor layer having a defect may be formed, and the reliability may be lowered. In particular, when a light-shielding metal material is used as the light-shielding layer and a crystallized polysilicon film is used as the semiconductor layer, the crystallinity is inferior and the semiconductor characteristics may be deteriorated.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a configuration capable of generally improving the reliability of a semiconductor layer, not limited to the configuration including a light shielding layer.
Another object of the present invention is to provide a configuration capable of simultaneously exhibiting a sufficient light shielding function to the semiconductor layer and an improvement in the reliability of the semiconductor layer when the light shielding layer is provided.
It is another object of the present invention to provide a suitable method for manufacturing a semiconductor device having the above-described configuration, and to provide an electro-optical device including the semiconductor device.

  In order to solve the above-mentioned problems, the present inventors have studied. In a semiconductor device including a light-shielding layer as disclosed in Patent Document 1, a defect occurs in the semiconductor layer, which is one of the factors that lower the reliability. As a result, it has been found that it is in an uneven shape formed on the surface of the light shielding layer. Specifically, the present inventors have found that the probability of occurrence of defects in a semiconductor layer increases depending on the surface shape of a film or the like formed immediately below the semiconductor layer, regardless of the presence or absence of a light shielding layer. It was.

  That is, the semiconductor device of the present invention includes a semiconductor layer formed in a predetermined pattern on the substrate via the intermediate layer, and the profile 1 of the unevenness is obtained with respect to the surface roughness of the intermediate layer disposed immediately below the semiconductor layer. The difference in height between the convex top and the concave bottom of the period is 40 nm or less. As described above, when the intermediate layer made of an arbitrary material disposed immediately below the semiconductor layer is designed so that the surface roughness is within the above range, defects in the semiconductor layer are extremely unlikely to occur, which is very reliable. It has become possible to provide a semiconductor device having excellent properties.

  In particular, the intermediate layer includes a light-shielding layer, and the semiconductor layer is disposed at least at a position overlapping the light-shielding layer in a planar manner, and the surface roughness of the light-shielding layer on the semiconductor layer side is one period of the uneven profile. The height difference between the convex top and the concave bottom can be designed to be 40 nm or less. It has been found that the surface roughness of the light-shielding layer having a light-shielding layer between the substrate and the semiconductor layer greatly affects the characteristics of the semiconductor layer. Therefore, when the surface of the light shielding layer is designed to have the above surface roughness, almost no defects are generated in the semiconductor layer, and the reliability of the semiconductor device can be greatly improved.

  Furthermore, the semiconductor layer includes a light shielding layer and an insulating layer formed so as to cover the light shielding layer as the intermediate layer, and the semiconductor layer is disposed at a position overlapping at least with the light shielding layer For the surface roughness of the light-shielding layer on the semiconductor layer side, the difference in height between the convex top and concave bottom of one period of the concave / convex profile is 40 nm or less, and the semiconductor of the insulating layer follows the concave / convex shape. Regarding the surface roughness on the layer side, the height difference between the convex top portion and the concave bottom portion of one cycle of the concave / convex profile may be 40 nm or less. In this case, the surface shape of the insulating layer disposed immediately below the semiconductor layer has unevenness following the uneven shape of the light shielding layer, and as a result, a configuration with few defects in the semiconductor layer can be provided. Become.

  It was also found that the surface roughness varies depending on the layer thickness, particularly when the light shielding layer is made of a light shielding metal material. Specifically, in order to design the surface roughness as in the present invention, the thickness of the light shielding layer made of a metal material is preferably designed to be 100 nm to 150 nm, and the effect of blocking light is less than 100 nm. May not be sufficiently expressed, and if it exceeds 150 nm, the surface roughness range defined in the present invention may not be realized. When the light-shielding layer is made of a metal material, the surface irregularities appear to be largely due to the crystal growth of the metal material during film formation. The surface roughness range defined in the invention can also be realized.

  Examples of the metal material constituting the light shielding layer include molybdenum or titanium nitride. Such a metal material is excellent in light-shielding properties and can be designed with a relatively small surface roughness.

  Next, in order to solve the above problems, a method for manufacturing a semiconductor device of the present invention includes a step of forming a light shielding layer having a predetermined pattern on a substrate, and a step of forming an insulating layer so as to cover the light shielding layer. A step of forming a semiconductor layer on the insulating layer and at least overlapping with the light shielding layer in a plane, and in the step of forming the light shielding layer, the surface roughness of the light shielding layer The film formation is performed under the condition that the difference in height between the convex top portion and the concave bottom portion in one cycle of the profile is 40 nm or less. As described above, in the light shielding layer forming step, the structure according to the present invention can be suitably realized by forming the film under the condition that the surface roughness is in the above-described manner. As the light-shielding layer film-forming conditions, a method of relaxing the crystallization of the light-shielding layer material by setting the film-forming temperature to room temperature to about 150 ° C. or reducing the film-forming speed can be employed.

  In the step of forming the light shielding layer, the light shielding layer is formed of a light shielding metal material, and the layer thickness is formed to be 100 nm to 150 nm. can do. In other words, when the light shielding layer is made of a metal material, the surface roughness is found to vary depending on the layer thickness, and when this is designed to be 100 nm to 150 nm, it is possible to ensure light shielding and reduce the surface roughness. Both could be realized. Here, if the light shielding layer is formed with a layer thickness of less than 100 nm, the effect of blocking light may not be sufficiently exhibited. If the layer is formed with a layer thickness exceeding 150 nm, the surface roughness range defined in the present invention is realized. There are cases where it is not possible.

  Further, in the step of forming the light shielding layer, the light shielding layer can be formed of molybdenum or titanium nitride. By forming the light shielding layer with such a metal material, it is possible to design with excellent light shielding properties and a relatively small surface roughness.

  In the method of manufacturing a semiconductor device according to the present invention, in the step of forming the semiconductor layer, for example, an amorphous silicon film is formed on the entire surface of the insulating layer formed on the light shielding layer, and then patterned after laser annealing treatment. Can be adopted. Then, a step of further forming an insulating film (gate insulating film) on the semiconductor layer, a step of forming a conductive film (gate electrode) with a predetermined pattern on the insulating film, and using the conductive film (gate electrode) as a mask (Or forming a separate mask) and selectively implanting impurity ions into the semiconductor layer. A step of forming an interlayer insulating film on the insulating film including the conductive film (gate electrode); a step of forming contact holes in the interlayer insulating film that are electrically connected to a source region and a drain region of the semiconductor layer; A step of filling a contact hole with a conductive material and forming a wiring on the interlayer insulating film.

  The semiconductor device manufactured in this way is configured as a thin film transistor including a source region and a drain region in a semiconductor layer. In particular, in the low-temperature polysilicon formation process, by forming the light shielding layer having the above surface shape, abnormal growth during crystallization hardly occurs, and troubles such as generation of holes in the crystal film can be prevented. Or it can be suppressed.

  Next, an electro-optical device according to the present invention includes the above-described semiconductor device. An electro-optical device provided with such a semiconductor device has improved manufacturing yield and has highly reliable switching characteristics. As such an electro-optical device, a liquid crystal display device or the like can be exemplified, and an electronic apparatus such as a mobile phone provided with the electro-optical device is very reliable.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The liquid crystal device (electro-optical device) of the present embodiment described below is an active matrix type transmissive liquid crystal device using a TFT (Thin Film Transistor) element as a switching element. Here, the TFT element provided in the liquid crystal device of this embodiment adopts the structure of the semiconductor device of the present invention.

  FIG. 1 is an equivalent circuit diagram of switching elements, signal lines, etc. in a plurality of pixels arranged in a matrix of the transmissive liquid crystal device of this embodiment. FIG. 2 is a main part plan view showing the structure of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed, and FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. It is. Note that FIG. 3 illustrates the case where the upper side in the drawing is the light incident side and the lower side in the drawing is the viewing side (observer side). Moreover, in each figure, in order to make each layer and each member the size which can be recognized on drawing, the scale is varied for every layer and each member.

  In the liquid crystal device according to the present embodiment, as shown in FIG. 1, a plurality of pixels arranged in a matrix include a pixel electrode 9 and a TFT element which is a switching element for controlling energization to the pixel electrode 9. 30, and the data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT element 30. Image signals S1, S2,..., Sn to be written to the data line 6a are supplied line-sequentially in this order, or are supplied for each group to a plurality of adjacent data lines 6a.

  In addition, the scanning line 3a is electrically connected to the gate of the TFT element 30, and scanning signals G1, G2,..., Gm are applied to the plurality of scanning lines 3a in a pulse-sequential manner at predetermined timing. The Further, the pixel electrode 9 is electrically connected to the drain of the TFT element 30, and the image signal S1, S2,... Supplied from the data line 6a is turned on by turning on the TFT element 30 as a switching element for a certain period. , Sn is written at a predetermined timing.

  A predetermined level of image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9 is held for a certain period with the common electrode described later. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the common electrode.

  Next, the planar structure of the main part of the liquid crystal device of the present embodiment will be described with reference to FIG. As shown in FIG. 2, a rectangular pixel electrode 9 (dotted line portion 9A) made of a transparent conductive material such as indium tin oxide (hereinafter abbreviated as ITO) is formed on the TFT array substrate. Are provided in a matrix, and data lines 6a, scanning lines 3a, and capacitor lines 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9, respectively. Each pixel electrode 9 is electrically connected to a TFT element 30 provided corresponding to each intersection of the scanning line 3a and the data line 6a, and has a structure capable of performing display for each pixel. ing.

  The data line 6a is electrically connected to a source region, which will be described later, of the semiconductor layer 1a constituting the TFT element 30 via a contact hole 5, and the pixel electrode 9 is a drain, which will be described later, of the semiconductor layer 1a. The region is electrically connected through a contact hole 8. In addition, the scanning line 3a is disposed so as to face a channel region (a region with a diagonal line rising to the left in the figure), which will be described later, in the semiconductor layer 1a, and the scanning line 3a serves as a gate electrode at a portion facing the channel region. Function. The semiconductor layer 1a can be composed of, for example, a polysilicon film.

  The capacitor line 3b is formed from a main line portion extending in a substantially straight line along the scanning line 3a (that is, a first region formed along the scanning line 3a in a plan view) and a portion intersecting the data line 6a. And a protruding portion (that is, a second region extending along the data line 6 a when viewed in a plan view) protruding toward the previous stage (upward in the drawing) along the data line 6 a. Note that a light shielding layer 11 is provided in a part of the non-pixel region indicated by hatching.

  Next, a cross-sectional structure of the liquid crystal device of the present embodiment will be described with reference to FIG. 3 is a cross-sectional view taken along the line A-A ′ of FIG. 2 as described above, and is a cross-sectional view showing a configuration of a region where the TFT element 30 which is an embodiment of the semiconductor device of the present invention is formed. In the liquid crystal device of the present embodiment, the liquid crystal layer 50 is sandwiched between the TFT array substrate 10 and the counter substrate 20 disposed to face the TFT array substrate 10.

  The TFT array substrate 10 is mainly composed of a substrate body 10A made of a translucent material such as glass or quartz, a TFT element 30, a pixel electrode 9, and an alignment film 40 formed on the liquid crystal layer 50 side surface. The counter substrate 20 is mainly composed of a substrate body 20A made of a translucent material such as glass or quartz, a common electrode 21 formed on the surface of the liquid crystal layer 50, and an alignment film 60. Each substrate 10, 20 is maintained at a predetermined substrate interval (gap) via the spacer 15.

  In the TFT array substrate 10, a pixel electrode 9 and an alignment film 40 are provided on the surface of the liquid crystal layer 50, and a pixel switching TFT element 30 that controls switching of each pixel electrode 9 is located adjacent to each pixel electrode 9. Is provided. The pixel switching TFT element 30 has an LDD (Lightly Doped Drain) structure, and is disposed on the inner surface side of the substrate body 10A via an insulating layer 19, a light shielding layer 11, and an interlayer insulating film 12 (intermediate layer). ing.

  Here, the insulating layer 19 is provided to protect the substrate body 10A made of glass, quartz or the like in the manufacturing process of the pixel switching TFT element 30, that is, the manufacturing process of the TFT array substrate. It is composed of a nitride film or the like.

  The light shielding layer 11 is made of Mo or TiN which is a light shielding metal material, and the layer thickness is designed to be about 100 nm to 150 nm. Such a light shielding layer 11 has a planar surface on the surface of the substrate body 10A on the liquid crystal layer 50 side, in which the pixel switching TFT elements 30 are formed, in particular, the region where the semiconductor layer 1a is formed (particularly the channel region). It is arranged to overlap. In this case, the light shielding layer 11 is transmitted through the TFT array substrate 10, reflected by the lower surface of the TFT array substrate 10 (interface between the TFT array substrate 10 and air), and returned to the liquid crystal layer 50 side. The semiconductor layer 1a has a function of preventing incidence on the channel region 1a ′ and the low concentration source / drain regions 1b and 1c.

  Here, the light shielding layer 11 has the following characteristics in surface roughness. Specifically, when the upper layer (semiconductor layer 1a side) of the light shielding layer 11 is observed with a TEM (transmission electron microscope), the difference in height between the convex top and the concave bottom for one period of the concave / convex profile on the surface thereof. Is 40 nm or less (preferably 30 nm or less). That is, in the cross-sectional shape of the light shielding layer 11, the step between the adjacent convex portion, the convex top portion of the concave portion, and the concave bottom portion does not exceed 40 nm (preferably 30 nm) at the maximum.

  The first interlayer insulating film 12 formed on the light shielding layer 11 is formed to insulate the light shielding layer 11 and the semiconductor layer 1a, and is composed of, for example, a silicon oxide film or a silicon nitride film.

  On the other hand, a semiconductor layer 1a is formed on the first interlayer insulating film 12, and a pixel switching TFT element 30 is formed including the semiconductor layer 1a. The pixel switching TFT element 30 includes a scanning line 3a, a semiconductor layer 1a, a gate insulating film 2 that insulates the scanning line 3a and the semiconductor layer 1a, and a data line 6a. The semiconductor layer 1a is connected to the scanning line 3a. A channel region 1a ′ in which a channel is formed by the electric field of the high concentration source region 1d and low concentration source region 1b connected to the source electrode, and a high concentration drain region 1e and low concentration drain region 1c connected to the drain electrode. And.

  Further, on the substrate body 10A including the scanning line 3a and the gate insulating film 2, a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e are included. An interlayer insulating film 4 is formed. A data line 6 a is formed on the second interlayer insulating film 4, and the data line 6 a is electrically connected to the high concentration source region 1 d through a contact hole 5 that penetrates the second interlayer insulating film 4. Yes.

  Further, a third interlayer insulating film 7 including a contact hole 8 leading to the high concentration drain region 1e is formed on the data line 6a and the second interlayer insulating film 4. A pixel electrode 9 is formed on the third interlayer insulating film 7, and the pixel electrode 9 is connected to the high-concentration drain region 1 e through a contact hole 8 penetrating the second interlayer insulating film 4 and the third interlayer insulating film 7. Is electrically connected.

  In the present embodiment, the gate insulating film 2 is extended from a position facing the scanning line 3a to be used as a dielectric film, the semiconductor film 1a is extended to form the first storage capacitor electrode 1f, and further to these The storage capacitor 70 is configured by using a part of the opposing capacitor line 3b as a second storage capacitor electrode. As shown in FIG. 2, in addition to providing the light shielding layer 11 on the TFT array substrate 10, the light shielding layer 11 is electrically connected to the capacitor line 3b at the preceding stage or the subsequent stage through the contact hole 13. It is configured. Furthermore, on the outermost surface of the TFT array substrate 10 on the liquid crystal layer 50 side, that is, on the pixel electrode 9 and the third interlayer insulating film 7, an alignment film 40 for controlling the alignment of liquid crystal molecules in the liquid crystal layer 50 when no voltage is applied. However, it is formed using, for example, a rubbed polyimide film.

  On the other hand, the counter substrate 20 is incident on the surface of the substrate body 20A on the liquid crystal layer 50 side, which is opposite to the formation area (non-pixel area) of the data line 6a, the scanning line 3a, and the pixel switching TFT element 30. A counter-side light shielding layer 23 is provided to prevent light from entering the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a of the pixel switching TFT element 30. In addition, the common electrode 21 made of ITO or the like is formed on the liquid crystal layer 50 side of the substrate body 20A on which the opposite-side light shielding layer 23 is formed, and the liquid crystal layer 50 side is provided with no voltage applied. An alignment film 60 for controlling the alignment of liquid crystal molecules in the liquid crystal layer 50 is formed using, for example, a rubbed polyimide film.

  The liquid crystal device of the present embodiment as described above includes a pixel switching TFT element (semiconductor device) 30 having an LDD structure, and prevents or suppresses light incident on the semiconductor layer 1a of the pixel switching TFT element 30. A light shielding layer 11 is provided. 4, the pixel switching TFT element (semiconductor device) 30 includes the light shielding layer 11 having a flat surface on the semiconductor layer 1a side. The typical surface roughness is such that the height difference between the convex top part and the concave bottom part is 40 nm or less (preferably 30 nm or less) for one period of the concave-convex profile of the cross section. In FIG. 4, the drain electrode 6 b is generalized in place of the pixel electrode 9.

  According to such a configuration, the surface layer on the semiconductor layer 1 a side of the first interlayer insulating film 12 formed on the light shielding layer 11 also has irregularities following the surface shape of the light shielding layer 11. That is, with respect to the surface roughness of the layer (the first interlayer insulating film 12 in the present embodiment) disposed immediately below the semiconductor layer 1a, the difference in height between the convex top and the concave bottom of one period of the concave / convex profile is It is 40 nm or less (preferably 30 nm or less).

  As described above, since the surface roughness of the layer made of an arbitrary material disposed immediately below the semiconductor layer 1a is designed to be in the above range, holes are generated in the semiconductor layer 1a. Defects hardly occur, and as a result, the reliability of the pixel switching TFT element (semiconductor device) 30 can be improved.

  Here, in the first interlayer insulating film 12 immediately below the semiconductor layer 1a, the height difference (maximum and minimum difference) between the convex top portion and the concave bottom portion of one period of the concave / convex profile, and the probability of occurrence of holes in the semiconductor layer 1a. We examined the relationship. FIG. 5 is a graph in which the maximum / minimum difference (nm) is plotted on the x-axis and the probability of hole occurrence (%) is plotted on the y-axis. Thus, when the maximum / minimum difference is 40 nm or less, the hole generation probability is 5% or less and the reliability of the semiconductor layer 1a is high, and when the maximum / minimum difference is 30 nm or less, the hole generation probability is substantially 0% and the semiconductor. It can be seen that the reliability of the layer 1a is maximized.

  In particular, the light shielding layer 11 is made of a light shielding metal material such as molybdenum or tungsten nitride, and further has a layer thickness of 100 nm to 150 nm. In the present embodiment, the light-shielding layer 11 is formed of such a light-shielding metal material, thereby realizing sufficient light-shielding properties and surface flatness. Light is shielded when the layer thickness is less than 100 nm. In some cases, the effect cannot be sufficiently exhibited, and when the thickness exceeds 150 nm, the above surface roughness range may not be realized.

Next, an example of a method for manufacturing the liquid crystal device will be described. In the present embodiment, the semiconductor device manufacturing method according to the present invention is employed in the manufacturing process of the TFT element 30.
Here, a case where an n-channel type polycrystalline silicon TFT is manufactured as the TFT element (semiconductor device) 30 will be described as an example. 6 to 7 are schematic cross-sectional views showing a manufacturing method of a TFT element (semiconductor device), in particular, in the order of steps, with regard to a part of the manufacturing configuration of the liquid crystal device of this embodiment. In addition, in each figure, in order to make each layer and each member into a size that can be recognized on the drawing, the scale is varied for each layer and each member.

First, as shown in FIG. 6A, after preparing a glass substrate 10A cleaned by ultrasonic cleaning or the like, an insulating layer as a base protective film made of an insulating film such as a silicon oxide film is formed on the entire surface of the glass substrate 10A. 19 is formed by a plasma CVD method or the like, for example. As the source gas used in this step, a mixed gas of monosilane and dinitrogen monoxide, TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ) and oxygen, disilane and ammonia, and the like are preferable.

  Similarly, as shown in FIG. 6A, a light shielding layer 11 made of molybdenum is formed on the entire surface of the insulating layer 19 to a thickness of about 150 nm by, for example, sputtering. Then, a photomask 29 is formed on the light shielding layer 11, and the light shielding layer 11 is patterned by dry etching (FIG. 6B). Subsequently, as shown in FIG. 6C, an interlayer insulating film 12 made of a silicon oxide film, a silicon nitride film, a silicon oxynitride film or the like is formed by a plasma CVD method or the like.

  Here, when the light shielding layer 11 is formed, the surface roughness of the light shielding layer 11 is formed under the condition that the difference in height between the convex top and concave bottom of one period of the concave / convex profile is 40 nm or less. ing. Specifically, the surface roughness can be realized by relaxing the crystallization of the light shielding layer material by setting the film forming temperature to room temperature to about 150 ° C. or reducing the film forming speed. .

  Next, as shown in FIG. 6D, an amorphous silicon film 1 is formed by a plasma CVD method or the like. As the source gas used in this step, disilane or monosilane is suitable. Thereafter, as shown in FIG. 6D, laser annealing is performed by irradiating an excimer laser beam L (wavelength 308 nm in the case of XeCl excimer laser, wavelength 248 nm in the case of KrF excimer laser). By such heat treatment, silicon can be melted and crystallized. Alternatively, the polysilicon film may be formed by patterning the amorphous silicon film 1 and then performing laser annealing.

  Then, as shown in FIG. 7A, the polysilicon film 1a is patterned by photolithography and dry etching so as to be located in the region where the light shielding layer 11 exists, that is, to overlap the light shielding layer 11 in a plane. To do. That is, after applying a photoresist on the polysilicon film 1a, the polysilicon film 1a is patterned by exposing and developing the photoresist, etching the polysilicon film 1a, and removing the photoresist.

  Thereafter, as shown in FIG. 7B, a silicon oxide film is formed by a plasma CVD method or the like, and is patterned so as to cover the polysilicon film 1a, thereby forming the gate insulating film 2. As the source gas used in this step, a mixed gas of TEOS and oxygen gas or the like is suitable. Further, a conductive material such as a metal such as aluminum, tantalum, or molybdenum, an alloy containing any of these metals as a main component, or polysilicon (polycrystalline silicon) is formed on the entire surface of the gate insulating film 2 by sputtering or the like. After forming the conductive material, the gate electrode 3a is formed by patterning by a photolithography method.

  Next, as shown in FIG. 7B, a resist mask 28 having a width wider than that of the gate electrode 3a is formed, and a high-concentration impurity ion DP1 (here, a polysilicon film 1a) is formed using the resist mask 28 as a mask. Phosphorus ions) are implanted to form a high concentration source region 1d and a high concentration drain region 1e. After such impurity ion implantation, the resist mask 28 is peeled off by ashing.

  After the resist mask 28 peeling step, as shown in FIG. 7C, using the gate electrode 3a as a mask, low-concentration impurity ions DP2 (here, phosphorus ions) are implanted to form a low-concentration source region 1b, a low-concentration drain. Region 1c is formed. Here, the portion that is located immediately below the gate electrode 3a and into which impurity ions are not introduced becomes the channel region 1a. The semiconductor layer 1a is formed by the implantation of impurity ions as described above.

  The implanted impurity ions are activated by irradiating an excimer laser beam (not shown). By such annealing treatment, the impurities implanted into the source regions 1b and 1d and the drain regions 1c and 1e are activated effectively.

  Next, as shown in FIG. 7 (d), an interlayer insulating film 4 made of a silicon oxide film or the like is formed on the surface side of the gate electrode 3a by a CVD method or the like, and a predetermined hole is formed to form a contact hole. After forming a resist mask (not shown) of a pattern, the interlayer insulating film 4 is dry-etched through the resist mask, so that portions corresponding to the high concentration source region 1d and the high concentration drain region 1e in the interlayer insulating film 4 are formed. A contact hole 5 and a contact hole 8 are respectively formed.

  Thereafter, a conductive material such as aluminum, titanium, titanium nitride, tantalum, molybdenum, or an alloy mainly containing any of these metals is formed on the entire surface of the interlayer insulating film 4 by a sputtering method or the like, Patterning is performed by photolithography to form the source electrode 6a and the drain electrode 6b as shown in FIG. As described above, an n-channel polycrystalline silicon TFT (semiconductor device) 30 can be manufactured.

  By the manufacturing method as described above, the polycrystalline silicon TFT (semiconductor device) 30 of the above-described embodiment can be preferably and easily manufactured. That is, in the step of forming the light shielding layer 11, the film is formed under the condition that the surface roughness of the light shielding layer 11 is such that the height difference between the convex top portion and the concave bottom portion of one period of the concave / convex profile is 40 nm or less. Therefore, the configuration related to the TFT 30 of the present embodiment can be suitably realized. In order to configure the surface roughness of the light shielding layer 11 within the range of the present embodiment, the thickness of the light shielding layer 11 is reduced, the constituent material of the light shielding layer 11 is selected, and the film forming conditions are optimized. At least one of the elements is necessary, and the technique described in the above manufacturing method is an example. By satisfying all these three elements, the surface roughness in the above range can be realized most simply and accurately.

  Next, specific examples of electronic devices including the liquid crystal device of the above embodiment will be described. FIG. 8 is a perspective view showing an example of a mobile phone. In FIG. 8, reference numeral 1000 denotes a mobile phone body, and reference numeral 1001 denotes a display unit using the liquid crystal device. When the liquid crystal device according to any of the above embodiments is used for a display portion of such an electronic device such as a mobile phone, a highly reliable electronic device is unlikely to cause deterioration in switching characteristics in the semiconductor device included in the liquid crystal device. It can be realized.

  Although one embodiment of the present invention has been described above, the present invention is not limited to this, and the present invention is not limited to the wording of each claim without departing from the scope described in each claim. Improvements based on the knowledge that a person skilled in the art normally has can be added as appropriate to the extent that the person can easily replace them. For example, in this embodiment, the case of manufacturing an n-channel TFT has been described as an example. However, the manufacturing method of the present invention can be similarly applied to the manufacture of a p-channel TFT. The subject of the present invention is not limited to the TFT, and the configuration of the present invention can be adopted for a general semiconductor device including a light-shielding layer for shielding the semiconductor layer.

2 is an equivalent circuit diagram of a liquid crystal device including a semiconductor device. The top view which shows the structure of the pixel group of a liquid crystal device similarly. Sectional drawing which shows the cross-section of a liquid crystal device. FIG. 2 is an enlarged cross-sectional view of a semiconductor device provided in the liquid crystal device of FIG. 1. The graph which shows the relationship between the surface shape of the layer immediately under a semiconductor layer, and the hole generation probability in a semiconductor layer. FIG. 6 is a schematic cross-sectional view showing one manufacturing process example of a liquid crystal device including a method for manufacturing a semiconductor device. FIG. 7 is a schematic cross-sectional view illustrating a process example subsequent to FIG. 6. The perspective view which shows an example of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10A ... Board | substrate, 11 ... Light-shielding layer (intermediate layer), 12 ... 1st interlayer insulation film (intermediate layer), 1a ... Semiconductor layer, 30 ... TFT element (semiconductor device)

Claims (9)

  A semiconductor layer formed in a predetermined pattern via an intermediate layer on a substrate, and the surface roughness of the intermediate layer disposed immediately below the semiconductor layer is determined by the relationship between the convex top and the concave bottom of one period of the concave / convex profile. A semiconductor device having a height difference of 40 nm or less.   The intermediate layer includes a light-shielding layer, and the semiconductor layer is disposed at least in a position overlapping the light-shielding layer in a planar manner. 2. The semiconductor device according to claim 1, wherein a difference in height between the top portion and the concave bottom portion is 40 nm or less.   The intermediate layer includes a light-shielding layer and an insulating layer formed so as to cover the light-shielding layer, and the semiconductor layer is disposed at least at a position overlapping the light-shielding layer in a planar manner. Regarding the surface roughness of the semiconductor layer side of the layer, the difference in height between the convex top portion and the concave bottom portion of one period of the concave / convex profile is set to 40 nm or less, and the surface roughness on the semiconductor layer side of the insulating layer according to the concave / convex shape 3. The semiconductor device according to claim 1, wherein the height difference between the convex top portion and the concave bottom portion of one cycle of the uneven profile is 40 nm or less.   4. The semiconductor device according to claim 2, wherein the light shielding layer is made of a light shielding metal material, and has a layer thickness of 100 nm to 150 nm.   The semiconductor device according to claim 4, wherein the light shielding layer is made of molybdenum or titanium nitride. Forming a light shielding layer of a predetermined pattern on the substrate;
Forming an insulating layer so as to cover the light shielding layer;
Forming a semiconductor layer on the insulating layer at a position overlapping at least with the light shielding layer in a plane,
In the step of forming the light shielding layer, the surface roughness of the light shielding layer is formed under the condition that the difference in height between the convex top portion and the concave bottom portion of one cycle of the uneven profile is 40 nm or less. A method for manufacturing a semiconductor device.   7. The method of manufacturing a semiconductor device according to claim 6, wherein, in the step of forming the light shielding layer, the light shielding layer is formed of a light shielding metal material, and the layer thickness thereof is formed from 100 nm to 150 nm. .   8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of forming the light shielding layer, the light shielding layer is formed of molybdenum or tungsten nitride.   An electro-optical device comprising the semiconductor device according to claim 1.

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