JP2005259250A - Ferroelectric memory device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory device enabling reading operation at a high speed. <P>SOLUTION: This ferroelectric memory device is provided with a plurality of bit lines, a plurality of ferroelectric capacitors connected to the plurality for storing predetermined data; a plurality of level shifters, connected to the plurality of bit lines to convert and output the potential level of the plurality of bit lines; a sense amplifier line for making the output of the level shifter transmitted; a level shifter selection section for selecting one of the plurality of level shifters for transmitting the output of the selected level shifter through the sense amplifier line; and a current mirror type sense amplifier for determining predetermined data stored in a ferroelectric capacitor, based on the potential of the sense amplifier line. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a ferroelectric memory device and an electronic apparatus. In particular, the present invention relates to a ferroelectric memory device using a differential amplification type sense amplifier and an electronic apparatus including the same.

A conventional FeRAM is disclosed in Japanese Patent Laid-Open No. 2000-40376 (Patent Document 1). In the conventional FeRAM disclosed in Patent Document 1, when data is read from a ferroelectric capacitor to a bit line, a differential amplifier amplifies a precharge voltage held on the bit line as a reference voltage.
JP 2000-40376 A

  However, in the conventional FeRAM disclosed in Patent Document 1, when data is read from the ferroelectric capacitor to the bit line, there is a problem that if the amount of charge taken out from the ferroelectric capacitor is small, the reading speed becomes slow. It was happening.

  Accordingly, an object of the present invention is to provide a ferroelectric memory device and an electronic apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above-described problem, according to a first aspect of the present invention, a plurality of bit lines, a plurality of ferroelectric capacitors connected to the plurality of bit lines via transistors and storing predetermined data, Select one of a plurality of level shifters that are connected to a plurality of bit lines and that convert and output the potential levels of the plurality of bit lines, a sense amplifier line that propagates the output of the level shifter, and a plurality of level shifters, respectively. A level shifter selection unit that propagates the output of the selected level shifter to the sense amplifier line, and a current mirror type sense amplifier that determines predetermined data stored in the ferroelectric capacitor based on the potential of the sense amplifier line A ferroelectric memory device is provided.

  According to the above configuration, the level shifter is arranged for each bit line, and the current mirror type sense amplifier is arranged corresponding to the plurality of level shifters. Therefore, according to the above configuration, for example, even when the ferroelectric memory device has a narrow pitch configuration such as 1T1C type, a current mirror type sense amplifier can be used. Therefore, according to the above configuration, it is possible to provide a ferroelectric memory device having a small circuit arrangement area and capable of performing a read operation at high speed.

  For example, one current mirror type sense amplifier is arranged for each of a plurality of memory cell blocks formed by a plurality of ferroelectric capacitors. Thereby, the arrangement area of the current mirror type sense amplifier can be reduced, so that a ferroelectric memory device with a smaller area can be provided.

  For example, the ferroelectric memory device includes a plurality of plate lines connected to a plurality of ferroelectric capacitors and a plate line based on a plate line selection signal indicating which of the plurality of plate lines is selected. And a level shifter selection unit selects the level shifter based on the plate line selection signal.

  In the ferroelectric memory device, each level shifter preferably includes an n-type MOS transistor having a drain connected to a sense amplifier line and a gate connected to a bit line.

  According to the above configuration, a predetermined current flows through the n-type MOS transistor according to the potential of the bit line supplied to the gate of the n-type MOS transistor. That is, the potential of the sense amplifier line is controlled based on the current flowing through the n-type MOS transistor. Therefore, according to the above configuration, since the potential level of the bit line can be converted with a very simple configuration, the level shifter can be arranged in accordance with the arrangement interval of the bit lines.

  In the ferroelectric memory device, the level shifter selection unit selects a level shifter including the grounded n-type MOS transistor by grounding one of the plurality of n-type MOS transistors in the plurality of level shifters. It is preferable.

  According to the above configuration, the output of the selected level shifter is supplied to the sense amplifier line, but no current flows through the n-type MOS transistor of the unselected level shifter. Therefore, according to the above configuration, the power consumption of the ferroelectric memory device can be reduced.

  In the ferroelectric memory device, the level shifter selection unit preferably selects the level shifter based further on a sense amplifier control signal indicating whether or not to operate the current mirror type sense amplifier.

  According to the above configuration, the n-type MOS transistor of the level shifter can be made non-conductive when the current mirror type sense amplifier is not operating. Therefore, according to the above configuration, it is possible to prevent a current from flowing through the level shifter when the level shifter does not need to supply an output to the sense amplifier line, such as when the current mirror type sense amplifier is not operating. A ferroelectric memory device with low power consumption can be provided.

  The ferroelectric memory device further includes a write control unit that writes predetermined data to the ferroelectric capacitor, and the write control unit is based on a write control signal that indicates whether or not the write operation of the write control unit is permitted. It is preferable that the predetermined data is written, and the level shifter selection unit further selects the level shifter based on the write control signal.

  According to the above configuration, the n-type MOS transistor of the level shifter can be turned off when data is written to the ferroelectric capacitor. Therefore, according to the above configuration, it is possible to prevent a current from flowing through the level shifter when the level shifter does not need to supply an output to the sense amplifier line at the time of data writing or the like. A memory device can be provided.

  In the ferroelectric memory device, the level shifter selection unit preferably grounds the bit line connected to the unselected level shifter when the source of the n-type MOS transistor included in the selected level shifter is grounded.

  According to the above configuration, the bit line connected to the unselected level shifter is grounded. Therefore, according to the above configuration, the potential of the unselected bit line can be stabilized, so that the malfunction of the ferroelectric memory device can be prevented.

  The ferroelectric memory device preferably further includes a p-type MOS transistor in which a predetermined voltage is supplied to the source and the gate and drain are connected to the sense amplifier line.

  According to the above configuration, a current is supplied to each level conversion circuit using the p-type MOS transistor as a load. Therefore, according to the above configuration, when the charge accumulated in the ferroelectric capacitor is discharged to the bit line, that is, when reading the data stored in the ferroelectric capacitor, the read data different from the initial read data Can appear on the bit line, the level shifter can supply an output corresponding to the potential of the bit line to the sense amplifier line.

  The p-type MOS transistor is preferably shared by a plurality of level shifters. That is, the p-type MOS transistor may be connected to one sense amplifier line in a number smaller than the number of level shifters connected to the sense amplifier line. For example, one p-type MOS transistor is connected to one sense amplifier line.

  According to a second aspect of the present invention, there is provided an electronic apparatus comprising the ferroelectric memory device. Here, the electronic device refers to a general device having a certain function provided with the ferroelectric memory device according to the present invention, and its configuration is not particularly limited. For example, a computer including the above ferroelectric memory device is used. General devices, mobile phones, PHS, PDAs, electronic notebooks, IC cards, and other devices that require storage devices are included.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

  FIG. 1 is a diagram showing a configuration of a ferroelectric memory device 100 according to an embodiment of the present invention. The ferroelectric memory device 100 includes a plurality of memory cell blocks 110-j (j is a positive integer), a word line control unit 120, a plate line control unit 130, a write circuit 140, a plurality of level shifters 150, A plurality of sense amplifiers 160 and a plurality of p-type MOS transistors 170 are provided.

  Each of the plurality of memory cell blocks 110-j includes a plurality of ferroelectric capacitors C arranged in an array, and a plurality of n-type MOS transistors TR connected to the plurality of ferroelectric capacitors C. Configured. A plurality of bit lines BLn (n is a positive integer), a plurality of word lines WLij (i is a positive integer), and a plurality of plate lines PLij are arranged in the plurality of memory cell blocks 110-j. .

  One end of the ferroelectric capacitor C is connected to one of the source and the drain of the n-type MOS transistor TR, and the other end is connected to the plate line PLij. In the n-type MOS transistor TR, the other of the source and the drain is connected to the bit line BLn and the gate is connected to the word line WLij. Based on the potential of the word line WLij, the ferroelectric capacitor C and the bit line BLn Switch whether or not to connect.

  The word line controller 120 selects a specific word line WLij by controlling the potential of the word line WLij based on the word line selection signal. Further, the plate line control unit 130 controls the potential of the plate line PLij based on the block selection signal BLK indicating the memory cell block 110-n to be selected and the plate line selection signal PLS indicating the plate line PLij to be selected. , Select a specific plate line PLij. In this embodiment, the word line control unit 120 and the plate line control unit 130 are provided for each memory cell block, and each word line control unit 120 and the plate line control unit 130 are connected to the corresponding memory cell block 110. The arranged word line WLij and plate line PLij are controlled.

  The write circuit 140 writes predetermined data to the ferroelectric capacitor C arranged in each memory cell block 110. The write circuit 140 is connected to the data lines DATA0 and DATA1, and writes data to the ferroelectric capacitor C by controlling the potential of the bit line BLn via the data lines DATA0 and DATA1. The write circuit 140 is supplied with a write control signal WE indicating whether or not to allow the write operation of the write circuit 140 and a sense amplifier output signal SAOUT to be described later, and based on the change in the potential of the WE, the data lines DATA0 and The timing for changing the potential of DATA1 is controlled, and the potentials of data lines DATA0 and DATA1 are controlled based on the potential of SAOUT.

  The level shifter 150-n is provided for each bit line BLn, converts the potential level of the bit line BLn, and outputs it to the sense amplifier line SL. A plurality of level shifters 150-n are connected to the sense amplifier line SL, and a level shifter 150-n selected by a later-described level shifter selection unit (see FIG. 2) is a bit line BLn connected to the level shifter 150-n. Are shifted to the sense amplifier line SL.

  The level shifter 150-n includes n-type MOS transistors 220, 230, 240, and 250. The n-type MOS transistor 220 has a drain connected to the sense amplifier line SL, a source connected to the drain of the n-type MOS transistor 230, and a gate connected to the bit line BLn. The n-type MOS transistor 220 controls the potential of the sense amplifier line SL by controlling the current flowing between the drain and source of the n-type MOS transistor 220 based on the potential level of the bit line BLn. . That is, n-type MOS transistor 220 outputs a potential obtained by converting the potential level of bit line BLn to sense amplifier line SL.

  The source of the n-type MOS transistor 230 is grounded, and switches whether to ground the source of the n-type MOS transistor 220 based on the potential of the control signal Yn (R) supplied to the gate.

  The n-type MOS transistor 240 has a drain connected to the data line DATA0 or DATA1, and a source connected to the drain of the n-type MOS transistor 250 and the bit line BLn. A control signal Yn (W) is supplied to the gate of the n-type MOS transistor 240, and whether to connect the bit line BLn and the data line DATA0 or DATA1 is switched based on the potential of the control signal. The n-type MOS transistor 250 has a source grounded, and switches whether to ground the bit line BLn based on the potential of the selection signal / Yn supplied to the gate.

  In the p-type MOS transistor 170, a predetermined voltage is supplied to the source, and the gate and drain are connected to the sense amplifier line SL and the drain of the n-type MOS transistor 220. That is, the p-type MOS transistor 170 functions as a load circuit for the level shifter 150-n. In the present embodiment, the p-type MOS transistor 170 is shared by a plurality of level shifters 150-n.

  The sense amplifier 160 receives the data stored in the ferroelectric capacitor C corresponding to the level shifter 150-n based on the output of the level shifter 150-n propagated by the sense amplifier line SL, that is, the potential of the sense amplifier line SL. judge. In the present embodiment, the sense amplifier 160 determines the data stored in the ferroelectric capacitor C by comparing the sense amplifier line SL with a reference voltage.

  In this embodiment, the sense amplifier 160 is a current mirror type sense amplifier, and includes p-type MOS transistors 162 and 164 and n-type MOS transistors 166, 168, and 170.

  In the p-type MOS transistors 162 and 164, a predetermined current is supplied to the sources, and the drains are connected to the drains of the n-type MOS transistors 166 and 168, respectively. The gates of the p-type MOS transistors 162 and 164 are connected to the source of the p-type MOS transistor 164.

  The n-type MOS transistor 180 has a drain connected to the sources of the n-type MOS transistors 166 and 168, and a gate supplied with a sense amplifier control signal SAE indicating whether or not to operate the sense amplifier 160. The n-type MOS transistor 180 switches the sense amplifier 160 based on the potential of the sense amplifier control signal SAE by switching whether or not to pass current to the p-type MOS transistors 162 and 164 and the n-type MOS transistors 166 and 168. Switches whether to operate.

  Each of the n-type MOS transistors 166 and 168 has a gate connected to a sense amplifier line SL and a dummy sense amplifier line DSL supplied with a reference voltage, and is based on the potentials of the sense amplifier line SL and the dummy sense amplifier line DSL. The current flowing through the n-type MOS transistors 166 and 168 is controlled. As a result, the potential of the drain of the n-type MOS transistor 166 changes and is output as a sense amplifier output SAOUT that is a determination result obtained by determining the data stored in the ferroelectric capacitor C.

  In the present embodiment, the ferroelectric memory device 100 includes a dummy memory cell block 112, a dummy word line control unit 122, and a dummy plate line control unit as circuits for generating a reference voltage supplied to the dummy sense amplifier line DSL. 132, a level shifter 152, and a p-type MOS transistor 162.

  The dummy memory cell block 112, the dummy word line control unit 122, the dummy plate line control unit 132, the level shifter 152, the p-type MOS transistor 172, the dummy word line DWL, the dummy bit line DBL, and the dummy plate line DPL are respectively memory cells. The block 110, the word line control unit 120, the plate line control unit 130, the level shifter 150, the p-type MOS transistor 170, the word line WL, the bit line BL, and the plate line PL have substantially the same configuration. The reference voltage is output to the dummy sense amplifier line DSL based on the data stored in the dummy ferroelectric capacitor DC.

  The n-type MOS transistors 222, 232, 242 and 252 constituting the level shifter 152 have substantially the same configuration as the n-type MOS transistors 220, 230, 240 and 250 constituting the level shifter 150-n, respectively. In the present embodiment, the n-type MOS transistor 222 having the gate connected to the dummy bit line DBL is configured to be smaller in size than the n-type MOS transistor 220. That is, the n-type MOS transistors 220 and 222 are configured such that the potential of the sense amplifier line SL when the data read from the ferroelectric capacitor C is “1” is higher than the potential of the dummy sense amplifier line DSL. The potential of the dummy sense amplifier DLS is used as a reference potential. In another example, the ferroelectric memory device 100 may generate the reference voltage using a low voltage circuit or the like.

  FIG. 2 is a diagram illustrating an example of the configuration of the level shifter selection unit 300 that determines which one of the plurality of level shifters 150-n is selected. The level shifter selection unit 300 includes a selection circuit 310, inverters 320, 340, 350, and 370, and NAND circuits 330 and 360.

  The selection circuit 310 receives the block selection signal BLK and the plate line selection signal PLS as inputs, and generates a selection signal Yn indicating which level shifter 150-n is selected by taking the logic of BLK and PLS. The inverter 320 generates an inverted selection signal / Yn obtained by inverting the logic value of the selection signal Yn, and supplies the inverted selection signal / Yn to the gates of the n-type MOS transistors 250 constituting the level shifter 150-n.

  The NAND circuit 330 receives the selection signal Yn and the write control signal WE as inputs, and supplies a negative logical product of Yn and WE to the inverter 340 as an output signal. The inverter 340 outputs a signal obtained by inverting the output signal to a control signal Yn (W indicating whether or not to write data to the ferroelectric capacitor C connected to the bit line BLn connected to the selected level shifter 150-n. ) And supplied to the gate of the n-type MOS transistor 240 constituting the level shifter 150-n.

  The NAND circuit 360 receives the selection signal Yn, the inverted signal obtained by inverting the write control signal WE, and the sense amplifier control signal SAE as inputs, and supplies a negative logical product of Yn, WE, and SAE to the inverter 370 as an output signal. The inverter 370 is a control signal indicating whether or not to read out the data stored in the ferroelectric capacitor C connected to the bit line BLn connected to the selected level shifter 150-n from the inverted signal of the output signal. Yn (R) is generated and supplied to the gate of the n-type MOS transistor 230 constituting the level shifter 150-n.

  FIG. 3 is a timing chart showing the operation of the ferroelectric memory device 100 according to this embodiment. With reference to FIGS. 1 to 3, the case where data stored in the ferroelectric capacitor C controlled by the word line WL11, the bit line BL1, and the plate line PL11 is read as an example is described. The operation will be described. In the following example, each control signal is a digital signal indicating H logic or L logic. The potential of the control signal when each control signal indicates H logic is substantially the same as the drive voltage VCC of the ferroelectric memory device 100. Further, when each control signal indicates L logic, the potential of the control signal is a ground potential.

  First, in cycle I (initial state), the write control signal WE and the sense amplifier control signal SAE indicate L logic, and neither the memory cell block 110-j nor the plate line PLij is selected. The selection signal BLK and the plate line selection signal PLS also indicate L logic. Accordingly, in cycle I, all selection signals Yn indicate L logic, and therefore all selection signals / Yn indicate H logic. Therefore, the n-type MOS transistor 250 constituting the level shifter 150-n becomes conductive, so that the bit line BLn is precharged to 0V.

  The word line control unit 120 changes the potential of the word line WL11 from 0 V to VCC based on the supplied word line selection signal, thereby allowing the ferroelectric capacitor C and the bit line BL11 to pass through the n-type MOS transistor TR. And connect.

  Next, in cycle II, data stored in the ferroelectric capacitor C is read. First, the block selection signal BLK and the plate line selection signal PLS become logical values for selecting the plate line PL11, and the plate line control unit 130 changes the potential of the plate line PL11 from 0 V to VCC based on the logical values. As a result, the plate line PL11 is selected.

  When the block selection signal BLK and the plate line selection signal PLS change to a logical value for selecting the plate line PL11, referring to FIG. 2, the selection circuit 310 selects the level shifter 150-1 connected to the bit line BL1. Therefore, the logic value of Y1 is set to H logic, and the other logic values of Yn (n ≠ 1) are set to L logic. Therefore, the logical value of / Y1 is L logic, the logical value of / Yn (n ≠ 1) is H logic, and since WE is L logic, all the logical values of Yn (W) are L logic. . Therefore, the bit line BL1 is in a floating state, and the other bit lines BLn (n ≠ 1) remain grounded.

  Further, in synchronization with the timing at which a specific plate line PL is selected, the logic value of SAE becomes H logic, so the logic value of Y1 (R) becomes H logic, and other Yn (R) (n ≠ 1 ) Is L logic. Therefore, the n-type MOS transistor 230 constituting the level shifter 150-1 is turned on, and the n-type MOS transistor constituting the other level shifter 150-n (n ≠ 1) is turned off, and the level shifter 150-1 is selected. . That is, the output of the level shifter 150-1 is supplied to the sense amplifier line SL.

  When the potential of the plate line PL11 changes from 0 V to VCC, the ferroelectric capacitor C storing “1” is applied with a voltage of −VCC with respect to the plate line PL11, and its polarization is inverted. As a result, charges accumulated in the ferroelectric capacitor C are released to the bit line BL11, and the potential of the bit line BL11 rises. On the other hand, when the ferroelectric capacitor C stores “0”, since the polarization of the ferroelectric capacitor C is not reversed, the potential of the bit line BL11 hardly increases (see the dotted line in FIG. 3).

  When the potential of the bit line BL11 rises, the potential of the gate of the n-type MOS transistor 220 also rises, and accordingly, the n-type MOS transistor 220 becomes conductive. Therefore, since current is consumed by the n-type MOS transistor 220, the output of the level shifter 150-1, that is, the potential of the sense amplifier line SL is lower than the reference voltage.

  On the other hand, when the ferroelectric capacitor C stores “0”, the potential of the bit line BL11 hardly rises, so that the n-type MOS transistor 220 does not conduct. Therefore, since almost no current is consumed by the n-type MOS transistor 220, the output potential of the level shifter 150-1 is substantially VCC (see the dotted line in FIG. 3).

  In this embodiment, the gate of the p-type MOS transistor 170 is connected to the sense amplifier line SL so that the p-type MOS transistor 170 functions as a load circuit. However, in another example, a plate line selection signal is applied to the gate. A pulse signal may be supplied in accordance with a change in the PLS potential. As a result, even when the ferroelectric capacitor C stores “1”, the current passing through the level shifter 150-1 hardly occurs, so that the power consumption can be suppressed.

  The equalize signal SAEQb is supplied to the sense amplifier 160, and SAEQb changes to L logic when SAE changes to H logic, and changes to H logic after a predetermined time has elapsed. Therefore, the sense amplifier 160 is equalized when SAE changes to H logic, and when the predetermined time has elapsed, the equalization is canceled and the operation is started. Thereby, it is possible to prevent a delay in reading due to the sense amplifier 160 outputting erroneous data. For example, when the ferroelectric capacitor C reads “1”, the predetermined time is a time longer than the time when the output of the level shifter 150-n is lower than the reference voltage.

  Therefore, when the SAE logic value changes to H logic, the potential of SAOUT, which is the output of the sense amplifier 160, gradually decreases. When the logic value of SAEQb changes to logic H, the sense amplifier 160 operates. At this time, since the potential of the sense amplifier line SL is lower than the reference potential, the potential of SAOUT becomes 0V. On the other hand, when the ferroelectric capacitor C stores “0”, since the potential of the sense amplifier line SL is substantially VCC, the potential of SAOUT rises to a potential close to VCC (see the dotted line in FIG. 3). .

  Next, in cycles III and IV, the data read from the ferroelectric capacitor C is rewritten. First, in cycle III, the logic value of WE is changed to logic H, and as a result, referring to FIG. 2, the level shifter selection unit 300 sets the logic value of Y1n (W) to logic H, and other Yn (W ) The logic value of (n ≠ 1) is L logic. Further, the level shifter selection unit 300 sets the logic value of Y1 (R) to L logic and sets the other logic values of Yn (R) (n ≠ 1) to L logic. As a result, the data line DATA0 and the bit line BL1 are connected, and the level shifter 150-1 stops supplying the output to the sense amplifier line SL.

  The write circuit 140 controls the potentials of the data lines DATA0 and DATA1 based on the supplied logical value of SAOUT when the logical value of WE is high, that is, when the write operation of the write circuit 140 is permitted. . In the present embodiment, the data read from the ferroelectric capacitor C is “1”, and the write circuit 140 sets the potential of the data line DATA0 to which the bit line BL1 is connected to VCC, so that the bit line The potential of BL1 is raised to VCC. In the present embodiment, the cycle III is a cycle in which “0” data is rewritten to the ferroelectric capacitor C. When the data read from the ferroelectric capacitor C is “1”, the plate line Since the potentials of the PL11 and the bit line BL1 are both VCC, the voltage applied to the ferroelectric capacitor C is substantially zero, so that no data is written.

  On the other hand, when the data read from the ferroelectric capacitor C is “0”, the write circuit 140 sets the potential of the bit line BL1 to 0V by setting the potential of the data line DATA0 to 0V. As a result, -VCC is applied to the ferroelectric capacitor C connected to the bit line BL1 with reference to the plate line PL11, and therefore data "0" is rewritten to the ferroelectric capacitor C.

  Next, in cycle IV, the potential of the plate line PL11 is changed to 0V. As a result, a voltage of + VCC is applied to the ferroelectric capacitor C with reference to the plate line PL11, so that “1” data is rewritten to the ferroelectric capacitor C.

  On the other hand, when the data read from the ferroelectric capacitor C is “0”, the voltage applied to the ferroelectric capacitor C is substantially zero, so that the data “0” written in the cycle III is retained. The

  Next, in cycle V, the logic values of SAE and WE are changed to L logic. As a result, the level shifter selection unit 300 sets the logical value of Y1 (W) to L logic, and sets the other logical values of Yn (W) (n ≠ 1) to L logic. Thereby, the data line DATA0 and the bit line BL1 are electrically disconnected. Further, the potential of the bit line BL1 drops to 0V. Then, the read operation for reading data stored in the ferroelectric capacitor C and the rewrite operation for rewriting the data are finished by changing the potential of the word line WL11 from VCC to 0V.

  According to the present embodiment, the level shifter 150-n is arranged for each bit line BLn, and the sense amplifier 160 is arranged corresponding to the plurality of level shifters 150-n. Therefore, according to the present embodiment, for example, a current mirror type sense amplifier can be used as the sense amplifier 160 even when the ferroelectric memory device 100 has a narrow pitch configuration such as the 1T1C type. Therefore, according to the present embodiment, it is possible to provide the ferroelectric memory device 100 having a small circuit arrangement area and capable of performing a read operation at high speed.

  FIG. 4 is a perspective view showing a configuration of a personal computer 1000 which is an example of the electronic apparatus of the present invention. In FIG. 4, the personal computer 1000 includes a display panel 1002 and a main body 1006 having a keyboard 1004. As a storage medium of the main body 1004 of the personal computer 1000, particularly a non-volatile memory, a semiconductor device including the storage circuit of the present invention is used.

  The examples and application examples described through the embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not a thing. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

1 is a diagram showing a configuration of a ferroelectric memory device 100 according to an embodiment of the present invention. It is a figure which shows an example of a structure of the level shifter selection part 300 which determines which of several level shifter 150-n is selected. 3 is a timing chart showing the operation of the ferroelectric memory device 100 according to the present embodiment. 1 is a perspective view illustrating a configuration of a personal computer 1000 which is an example of an electronic apparatus according to the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device, 110 ... Memory cell block, 112 ... Dummy memory cell block, 120 ... Word line control part, 122 ... Dummy word line control part, 130 ... Plate line control unit, 132 ... dummy plate line control unit, 140 ... write circuit, 150 ... level shifter, 160 ... sense amplifier, 170 ... p-type MOS transistor, 300 ... level shifter selection Part

Claims (9)

Multiple bit lines,
A plurality of ferroelectric capacitors respectively connected to the plurality of bit lines via transistors and storing predetermined data;
A plurality of level shifters connected to the plurality of bit lines, respectively, for converting and outputting potential levels of the plurality of bit lines;
A sense amplifier line for propagating the output of the level shifter;
A level shifter selection unit that selects any one of the plurality of level shifters and propagates the output of the selected level shifter to the sense amplifier line;
A ferroelectric memory device comprising: a current mirror type sense amplifier that determines the predetermined data stored in the ferroelectric capacitor based on a potential of the sense amplifier line. A plurality of plate lines respectively connected to the plurality of ferroelectric capacitors;
A plate line control unit that selects the plate line based on a plate line selection signal indicating which of the plurality of plate lines is selected;
2. The ferroelectric memory device according to claim 1, wherein the level shifter selection unit selects the level shifter based on the plate line selection signal.   3. The ferroelectric memory device according to claim 1, wherein each level shifter includes an n-type MOS transistor having a drain connected to the sense amplifier line and a gate connected to the bit line.   The level shifter selection unit selects a level shifter including the grounded n-type MOS transistor by grounding one of the plurality of n-type MOS transistors in the plurality of level shifters. The ferroelectric memory device according to claim 3.   5. The ferroelectric memory device according to claim 4, wherein the level shifter selection unit selects the level shifter further based on a sense amplifier control signal indicating whether or not to operate the current mirror type sense amplifier. . A write controller for writing predetermined data in the ferroelectric capacitor;
The write control unit writes the predetermined data based on a write control signal indicating whether or not to permit the write operation of the write control unit;
6. The ferroelectric memory device according to claim 4, wherein the level shifter selecting unit selects the level shifter further based on the write control signal.   The level shifter selecting unit grounds the bit line connected to the unselected level shifter when the source of the n-type MOS transistor included in the selected level shifter is grounded. Item 7. The ferroelectric memory device according to any one of Items 4 to 6.   8. The ferroelectric according to claim 3, further comprising a p-type MOS transistor having a predetermined voltage supplied to a source and a gate and a drain connected to the sense amplifier line. Memory device. 9. An electronic apparatus comprising the ferroelectric memory device according to claim 1.

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