JP2005252654A - Semiconductor integrated circuit incorporating a/d converter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, even if there is no change in externally inputted analog values in a semiconductor integrated circuit incorporating an A/D converter circuit and a CPU, upon receipt of a conversion completion notice from the A/D converter circuit when the A/D converter circuit is used, the CPU needs to confirm the A/D conversion result with interrupting main program processes, and further to reconfirm the conversion result after repeating the A/D conversion once. <P>SOLUTION: An A/D converter circuit 2 completes an A/D conversion operation to issue an A/D conversion completion notice (signal 109) to a CPU 6 only when the level of an externally inputted analog signal varies. The circuit 2 may generate a completion notice after verifying that the analog signal level is in a stationary state after its transient state, thus omitting the confirmation operation of the A/D conversion result by the CPU 6 after receiving the completion notice, thus reducing the load of the CPU 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit such as a general-purpose microcontroller.

Conventionally, when A / D conversion is performed in a semiconductor integrated circuit having an A / D conversion circuit having one or more analog input terminals and a CPU, how the signal level of the analog signal input from the analog input terminal changes. Regardless, the A / D conversion operation is executed, and the completion of the A / D conversion is notified to the CPU when the A / D conversion is completed. Further, upon receiving the completion notification, the CPU suspends the execution of the main program to check the A / D conversion result, and increases the accuracy of the A / D conversion result by executing the A / D conversion operation again. It was.
JP 61-123999 A

  In the above-described conventional configuration, the A / D conversion circuit issues an A / D conversion completion notification to the CPU, and this completion notification performs the A / D conversion operation regardless of the change in the signal level of the analog signal. Since it is executed and issued, it is necessary for the CPU to suspend the processing of the main program and check the A / D conversion result every time a completion notification is issued, which increases the burden on the CPU and includes the CPU. Hardware resources could not be used effectively.

  In addition, since the A / D conversion result may be a conversion result when the signal level of the analog signal is not stable, the CPU causes the A / D conversion operation to be performed once again when the conversion completion notification is received. Therefore, it is necessary to reconfirm the conversion result, which increases the burden on the CPU.

  In addition, unnecessary power consumption occurs because the A / D conversion operation is executed regardless of the change in the signal level of the analog signal.

  In addition, when there are a plurality of analog input terminals, it takes time to perform A / D conversion for a terminal whose signal level does not change, and therefore, until the A / D conversion operation for an analog input terminal whose signal level has changed is started. There was a problem that the delay time was long.

  An object of the present invention is to provide a semiconductor integrated circuit that can reduce the load on the CPU during an A / D conversion operation, and further enables low power consumption and high-speed sensing of an analog input terminal.

  A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having an A / D conversion circuit that has an analog input terminal of one or more systems, A / D converts an analog signal input from the analog input terminal, and a CPU. The A / D conversion circuit has a function of detecting a change in the signal level of the analog signal input from the analog input terminal, and only when the change in the signal level of the analog signal is detected. It has a function of completing the D conversion operation and notifying the CPU of the completion of A / D conversion.

  According to this configuration, since the completion of the A / D conversion is notified to the CPU only when the signal level of the analog signal is changed, the A / D conversion is performed regardless of the change in the signal level of the analog signal as in the related art. Compared with the case where the D conversion operation is executed and notified to the CPU, the burden on the CPU can be reduced.

  In the present invention, when the A / D conversion circuit detects a change in the signal level of the analog signal, the A / D conversion circuit completes the first A / D conversion operation and then performs the second time on the analog signal. It is preferable to notify the CPU of the completion of A / D conversion when an A / D conversion operation is performed and there is no difference between the first and second A / D conversion results.

  As a result, there is no difference between the first and second A / D conversion results, that is, the completion of the A / D conversion is notified after the signal level of the analog signal is stabilized. Accordingly, when the A / D conversion operation is completed, it is confirmed that the signal level of the analog signal at that time has passed the transient state and is in a steady state, and then the completion of A / D conversion is notified. The operation of checking the A / D conversion result of the CPU after acceptance can be omitted, and the burden on the CPU can be reduced.

  In the present invention, it is preferable that the A / D conversion circuit interrupts the A / D conversion operation when a change in the signal level of the analog signal is not detected.

  Thereby, low power consumption can be realized.

  In the present invention, the A / D conversion circuit interrupts the A / D conversion operation when no change in the signal level of the analog signal is detected, and the analog signal input from the same or another analog input terminal It is preferable to start the A / D conversion operation.

  In this way, high-speed sensing of analog input terminals can be realized by interrupting the A / D conversion operation and A / D converting analog signals of the same or different analog input terminals.

  As described above, according to the present invention, by appropriately processing the A / D conversion operation, it is possible to reduce the burden on the CPU, reduce power consumption, and realize high-speed sensing of analog input terminals.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, 1 is a semiconductor integrated circuit, 2 is an A / D conversion circuit, and 6 is a CPU. The A / D conversion circuit 2 and the CPU 6 are built in the semiconductor integrated circuit 1.

  Reference numeral 3 denotes an analog input selection circuit that selects an analog signal 101 selected from the analog input terminals T101 and T102 and outputs the selected analog signal as an analog signal 104. Reference numeral 4 denotes an A of the input analog signal 104. This is an A / D conversion processing circuit that performs / D conversion and outputs a digital conversion result 105. 5 stores the input digital conversion result 105, controls the A / D conversion operation of the A / D conversion processing circuit 4 by the conversion operation control signal 106, and supplies the analog input selection circuit 3 by the input terminal switching signal 107. On the other hand, the A / D conversion that selects which of the analog signals 101 and 102 is input to the A / D conversion processing circuit 4 and outputs the A / D conversion completion signal 109 to the CPU 6 when the A / D conversion is completed. It is a control circuit.

  The CPU 6 outputs to the A / D conversion control circuit 5 an A / D conversion start signal 108 for controlling the start of A / D conversion and a conversion clock 111 used for A / D conversion. Further, the CPU 6 acquires an A / D conversion result from the A / D conversion control circuit 5 via the internal bus 110. Reference numerals 7 and 8 denote resistors added to the analog signals 101 and 102, and one ends of the resistors 7 and 8 are connected to the reference voltage 20.

  FIG. 2 is a configuration diagram of the A / D conversion control circuit 5 in FIG.

  In FIG. 2, reference numeral 13 denotes an A / D conversion result storage register that takes in the digital conversion result 105 as a trigger for the conversion clock 111. When the conversion clock 111 is input, it is shifted to the right bit by bit. Reference numeral 16 denotes a memory register for storing the value of the A / D conversion result storage register 13 when A / D conversion is completed. Reference numeral 15 denotes a value for storing the value of the memory register 16 at the start of A / D conversion. A buffer register to shift.

  FIG. 3 is a flowchart showing the operation of the buffer register 15. When the conversion clock 111 is input, each bit of the buffer register 15 is shifted to the right by one bit. It is assumed that the shift destination of B9 which is the most significant bit is B0. Reference numeral 14 denotes a comparison circuit that performs bit comparison between the A / D conversion result storage register 13 and the buffer register 15.

  Reference numeral 9 denotes an A / D conversion completion bit number counter, which has a function of counting the number of bits for which A / D conversion is completed. Reference numerals 10, 11, and 12 are incorporated in the A / D conversion completion bit number counter 9, and 11 is a comparison register for defining the number of bits for interrupting the A / D conversion operation and performing halfway comparison of conversion results, Reference numeral 12 denotes a count register for counting the number of bits subjected to A / D conversion. Reference numeral 10 denotes a comparison circuit for comparing the values of the comparison register 11 and the count register 12. If the comparison results match, a match signal is obtained. 114 is output, and when the count value of the register for counting 12 becomes equal to the number of bits that can be stored in the A / D conversion result storage register 13, the conversion completion signal 115 is output. Here, it is assumed that the A / D conversion result storage register 13, the buffer register 15, and the memory register 16 each have 10 bits, and the conversion is completed when the count value of the counting register 12 becomes “10” in decimal. Assume that signal 115 is output.

  A control circuit 17 in the A / D conversion control circuit 5 outputs a comparison start signal 119 to the conversion result comparison circuit 14 and receives a comparison coincidence signal 118. Further, the memory register 16 can be accessed via the signal line 117, and the A / D conversion result storage register 13 can be accessed via the signal line 120. When the A / D conversion is completed, the data in the A / D conversion result storage register 13 can be accessed. Is copied to the memory register 16. Reference numerals 18 and 19 are built in the control circuit 17, and 18 is an analog signal change detection flag that is set when there is a change in the signal level of the analog signal input from the analog input terminal. Reference numeral 19 denotes a low consumption mode setting flag, which sets the operation mode of the A / D conversion control circuit 5. The analog signal change detection flag 18 is set when the comparison coincidence signal 118 is negated. The analog signal change detection flag 18 is mounted on each of the analog signals 101 and 102. The setting of the low consumption mode is determined at the timing of operating the LSI, and the setting of the low consumption mode setting flag 19 is performed by the CPU 6 via the internal bus 110.

  Hereinafter, the operation of the semiconductor integrated circuit according to the present embodiment will be described with reference to the control flowchart of FIG.

  The A / D conversion circuit 2 transitions to a standby state by raising the power supply of the semiconductor integrated circuit 1 from off (S0) to on (S1).

  When the A / D conversion circuit 2 is used, the CPU 6 first inputs the number of bits for temporarily interrupting the A / D conversion to the comparison register 11 via the internal bus 110 (S2). Here, “3” in decimal is set.

  Next, the CPU 6 supplies a conversion clock 111 to the A / D conversion circuit 5 and outputs an A / D conversion start signal 108. As a result, the control circuit 17 outputs an input terminal switching signal 107 to the analog input selection circuit 3 to select an analog signal, and outputs a conversion operation control signal 106 to the A / D conversion processing circuit 4. The A / D conversion processing circuit 4 is caused to start an A / D conversion operation (S3). Here, it is assumed that the analog signal 101 is selected. In response to the output of the A / D conversion start signal 108, the value of the memory register 16 is copied to the buffer register 15 (S4).

  The digital conversion result 105 output from the A / D conversion processing circuit 4 is input to the A / D conversion result storage register 13, but the 3-bit conversion that matches “3” set in the comparison register 11 is completed. At that time, the coincidence signal 114 is output from the comparison circuit 10.

  FIG. 5 shows the states of the A / D conversion result storage register 13 and the buffer register 15 when the 3-bit A / D conversion operation is completed. A9, A8, and A7 of the A / D conversion result storage register 13 are digital conversion results output from the A / D conversion processing circuit 4, and the control circuit 17 that receives the coincidence signal 114 starts comparison with the conversion result comparison circuit 14. The signal 119 is output to start the comparison operation (S5). At this time, A9 and B9, A8 and B8, and A7 and B7 in FIG. 5 are compared. When these bits all match, a comparison match signal 118 is output. Here, when the comparison coincidence signal 118 is not output, it indicates that the analog signal 101 from the outside has changed, and thus A / D conversion is repeated until the comparison coincidence signal 118 is output (S11 to S11). .

  The control circuit 17 receives the comparison coincidence signal 118 (the above bit comparison result coincides) and determines that the signal level of the analog signal 101 does not change when the analog signal change detection flag 18 is not set. When the analog signal change detection flag 18 is set, it is determined that the signal level of the analog signal 101 has changed.

  If there is no change in the signal level of the analog signal 101, it is determined whether or not the low consumption mode is set based on the set value of the low consumption mode setting flag 19 (S21). The time until the / D conversion operation is completed is counted by the counting register 12, and the A / D conversion processing circuit 4 is stopped until the conversion completion signal 115 is output, thereby realizing low power consumption. (S22). When not in the low power consumption mode, the count register 12 is cleared (S23), and the input terminal switching signal 107 is generated to switch the selected analog signal 104 from 101 to 102 (S24), thereby enabling high-speed operation. It is possible to sense the analog input terminal. Also in the low power consumption mode, when the conversion completion signal 115 is output, the count register 12 is cleared (S23), and the input terminal switching signal 107 is generated to select the selected analog signal 104 from 101. By switching to 102 (S24), it becomes possible to sense the analog input terminal at high speed. After S24, A / D conversion processing from S3 is performed on the switched analog signal 102.

  If the signal level of the analog signal 101 is changed, the remaining 7-bit A / D conversion operation is performed (S31). When the conversion is completed and the conversion completion signal 115 is output from the comparison circuit 10. Then, all the bits of the A / D conversion storage register 13 and the memory register 16 are compared (S32). The conversion result comparison circuit 14 also performs the comparison in S32. If the comparison results match, an A / D conversion completion signal 109 is output (S35), and at the same time, the analog signal change detection flag 18 is cleared (S33), and the data in the A / D conversion result storage register 13 is stored in the memory register. 16 (S34). Note that the loop of S3, S4, S5, S31, S32 → S3 represents a state in which the upper three bits are stabilized in S5 and then waits until the lower bits are stabilized.

  FIG. 6 shows the relationship between the change in the analog signal 101, the A / D conversion completion signal 109, and the analog signal change detection flag 18. In the transition state in which the analog signal is changing, the analog signal change detection flag 18 is set, and the data in the A / D conversion storage register 13 and the memory register 16 match at the time of A / D conversion after the steady state is reached ( At the same time when the A / D conversion completion signal 109 is output, the analog signal change detection flag 18 is cleared, and the data in the A / D conversion result storage register 13 is stored in the memory register 16. Copy to. Note that one conversion time in FIG. 6 represents a basic time for performing A / D conversion, and is shown as an equivalent time in FIG. 6, but there are cases where there is a change in the input analog and there is no change. The time is different.

  As described above, according to the present embodiment, the A / D conversion circuit 2 completes the A / D conversion operation only when there is a change in the signal level of the analog signal input from the outside and subject to A / D conversion. At the same time, an A / D conversion completion notification (A / D conversion completion signal 109) is issued to the CPU 6. Further, when the A / D conversion operation is completed, it is confirmed that the signal level of the analog signal at that time passes the transient state and is in a steady state, and then a completion notification is generated, whereby the CPU 6 after the completion notification is received. The confirmation operation of the A / D conversion result is omitted. As a result, the burden on the CPU 6 can be reduced.

  In addition, when there is no change in the signal level of the analog signal, the A / D conversion operation is interrupted, and the A / D conversion of the analog signal at the same or different analog input terminal is started, so that a high-speed analog input terminal Can be realized. Here, when A / D conversion of analog signals at the same or different analog input terminals is not started, power consumption can be reduced by interrupting the A / D conversion operation. In an actual set, A / D conversion is always performed regardless of whether the analog input terminal is a single terminal or a plurality of terminals, and when the conversion is completed, the conversion is performed again.

  The semiconductor integrated circuit according to the present invention can reduce the load on the CPU when A / D converting an analog input signal, and is useful as a general-purpose microcontroller or the like.

Schematic configuration diagram of a semiconductor integrated circuit in an embodiment of the present invention Schematic configuration diagram of an A / D conversion control circuit in an embodiment of the present invention The figure which shows the operation | movement of the buffer register in embodiment of this invention Control flow diagram in the embodiment of the present invention The figure for demonstrating operation | movement of the A / D conversion result storage register | resistor in the embodiment of this invention, a buffer register, and a conversion result comparison circuit Time chart in the embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 A / D conversion circuit 3 Analog input selection circuit 4 A / D conversion processing circuit 5 A / D conversion control circuit 6 CPU (central processing unit)
7 Resistance 8 Resistance 9 A / D conversion completion bit number counter 10 Comparison circuit 11 Comparison register 12 Count register 13 A / D conversion result storage register 14 Conversion result comparison circuit 15 Buffer register 16 Memory register 17 Control circuit 18 Analog signal change Detection flag 19 Low consumption mode setting flag 101 Analog signal 102 Analog signal 104 Analog signal 105 Digital conversion result 106 Conversion operation control signal 107 Input terminal switching signal 108 A / D conversion start signal 109 A / D conversion completion signal 110 Internal bus 111 Conversion Clock 112 Count value 113 Count value 114 Match signal 115 Conversion completion signal 116 Counter reset signal 117 Signal line 118 Comparison match signal 119 Comparison start signal 120 Signal line

Claims (4)

A semiconductor integrated circuit having an analog input terminal of one or more systems, an A / D conversion circuit for A / D converting an analog signal input from the analog input terminal, and a CPU;
The A / D conversion circuit has a function of detecting a change in the signal level of the analog signal input from the analog input terminal, and only when the change in the signal level of the analog signal is detected. A semiconductor integrated circuit having a function of completing a D conversion operation and notifying the CPU of the completion of A / D conversion.   When the A / D conversion circuit detects a change in the signal level of the analog signal, the A / D conversion circuit completes the first A / D conversion operation and then performs the second A / D on the analog signal. 2. The semiconductor integrated circuit according to claim 1, wherein a conversion operation is performed, and when there is no difference between the first and second A / D conversion results, completion of A / D conversion is notified to the CPU.   The semiconductor integrated circuit according to claim 1, wherein the A / D conversion circuit interrupts the A / D conversion operation when a change in the signal level of the analog signal is not detected.   The A / D conversion circuit interrupts the A / D conversion operation when no change in the signal level of the analog signal is detected, and the analog signal input from the same or another analog input terminal is The semiconductor integrated circuit according to claim 1, wherein the / D conversion operation is started.

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