JP2000105604A - Method for making output interval constant at constant scan setting of programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the output intervals by constant scan setting constant by initiating no constant-period interruption during refreshing. SOLUTION: In the programmable controller, a constant-period interruption generating circuit 9 of a CPU unit 1 counts pulses from a clock circuit 8 and initiates an interruption to a CPU chip 2 according to the count value. This programmable controller is provided with a specific error adjustment time between the end of a constant-period process and the start of a refreshing process so that the constant-period interruption process (constant-period interruption generation timing) do not extend into a refreshing time. Namely, the generation period of a constant-period interruption is synchronized with 'after power-on operation → RUN and STOP →RUN' by being adjusted finely in the timing of 'after power-on operation → RUN and STOP → RUN'. Consequently, the constant-period interruption is initiated not in the refreshing period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of variation in output control when a constant scan of a CPU unit is set in a programmable controller used in industrial equipment or the like.

[0002]

2. Description of the Related Art A constant scan function is a program execution time (T1) and an input / output refresh time required for executing a sequence program from a 0th step to an END process as disclosed in Japanese Patent Application Laid-Open No. 1-119804. This is a function for stabilizing the scan time (T1 + T2) represented by the sum of (T2), and is generally an effective function in a system in which control is hindered by input / output variations.

A processing method of a constant scan function in a conventional CPU unit will be described with reference to FIGS. A, B, and C are general-purpose registers built into the CPU chip, and the constant scan setting time is 10 times.
It is assumed that the fixed-cycle interrupt interval is set such that a fixed-cycle interrupt occurs at an interval of 5 ms. here,
The periodic interrupt is a process generated by a signal from a clock circuit in the CPU unit, and is not required to be executed for each END process such as checking for a drop in the power supply voltage of a battery and needs to be processed periodically. Things.

FIG. 6 is a system configuration diagram showing the system configuration of the CPU unit. In the figure, reference numeral 1 denotes a CPU unit which executes a program described in the OS-ROM 7A, decodes and executes a sequence program, and a peripheral which receives a sequence program programmed by the user on the peripheral device 14. A device I / F unit 3, a sequence program memory 4 for storing received sequence programs, and a device memory 5 for storing execution results of the sequence programs
A work memory 6 used for temporary data saving, an input unit 11 for acquiring information from an input device such as a switch, and an output unit for outputting a calculation result to an output device such as a lamp. 12, a RUN / STOP switch 13 for enabling the user to change the execution and stop of the sequence program, and counts the pulses from the clock circuit 8, and counts the CP from the count value.
A fixed-cycle interrupt generation circuit 9 for generating an interrupt for the U chip 2 and a TMR used by the CPU unit 1 for time measurement
A register 10 is provided. Here, the fixed cycle interrupt generation circuit 9 and the TMR register 10 continue to operate as long as the pulse signal from the clock circuit 8 is received.

FIG. 7 is a flow chart showing a fixed period interrupt process. FIG. 8 is a flowchart showing processing after the power of the CPU unit is turned on when the constant scan is set. FIG. 9 is a diagram illustrating timings of the periodic interrupt and the output refresh.

Next, a conventional operation will be described with reference to FIGS. The CPU unit 1 is equipped with various operation state checking functions such as a battery power supply voltage drop check (hereinafter referred to as a battery check), a peripheral device installation check, and a work memory failure check. At the timing of the interrupt from the generation circuit 9, the operation status check corresponding to the counter value of the interrupt is processed one by one. The processing time of these operation state checks differs for each operation state check function, and the processing time changes even when the check is OK / NG.

[0007] First, an internal process when a fixed period interrupt is performed will be described with reference to FIG. First, step S
At 51, it is checked whether the value of the fixed-cycle interrupt occurrence counter for determining which operation state check function is to be executed exceeds the number of operation state check functions (in this case, for example, n). As a result of the check in step S51, if the number exceeds (for example, n + 1), n
Since the check function corresponding to +1 does not exist, the value of the fixed-cycle interrupt occurrence counter is initialized to 0 (step S5).
2) Then, the process proceeds to step S53. On the other hand, step S
As a result of the check in 51, if the number does not exceed (for example, 1), the process directly proceeds to step S53.

In step S53, the value of the fixed-cycle interrupt occurrence counter is determined, and an operation state check according to the value of the counter is performed. For example, if the value of the fixed cycle interrupt occurrence counter is "0", the battery is checked (step S5).
4) If "1", an operation status check function such as a peripheral device mounting check (step S55), if "n", a work memory failure check (step S56), etc.

After executing the operation state check function, in step S57, 1 is added to the fixed cycle interrupt occurrence counter, and the fixed cycle interrupt is terminated in preparation for the next fixed cycle interrupt occurrence. By performing the above-described processing, it becomes possible to execute each operation state check function at regular intervals.

Next, a description will be given of processing after turning on the power of the CPU unit when the conventional constant scan is set, with reference to FIG. When the CPU unit 1 is started,
First, in step S61, initialization for operating the CPU unit 1 is performed. In this initial setting, the CPU 2 sets the interval of the periodic interrupt occurrence and the like.
This is performed by a program described in the S-ROM 7A.

Subsequently, in step S62, in order to determine whether the CPU unit 1 is in the RUN mode or the STOP mode,
The RUN / STOP switch 13 is determined.
Here, the RUN / STOP switch 13 is set to ST
If it is turned to the OP side, the process shifts to step S73 to perform a STOP process of turning off all outputs in order to stop the operation of the normal CPU unit 1, and then to the RU again.
A determination is made by the N / STOP switch 13 (step S62), and this is repeated.

On the other hand, a RUN / STOP switch 1
If No. 3 faces the RUN side, the process proceeds to step S63, and the current TMR register value is stored in the work memory 6 as the constant scan wait start TMR value.
Here, the TMR register value stored in the work memory 6 is
This is used to determine whether the time has reached the constant scan set time.

Subsequently, in step S64, output refresh processing is performed, and data in the device memory 5 (output) for storing the operation result of the sequence program is written to the output unit 12 in order to output the data to an output device such as a lamp. . In step S65, input refresh processing is performed, and information on input devices such as switches is read from the input unit 11 to the device memory 5 (input).

Subsequently, in step S66, a sequence program is executed based on the information in the device memory 5 (input) to output an operation result based on the input condition to the device memory 5 (output). Then, an END process for mainly communicating with the peripheral device 14 is performed.

In steps S68 to S71, a constant scan time waiting process is performed. First, the current value of the TMR register 10 is read into the register B (step S68). Subsequently, the constant scan wait start TMR value is subtracted from the register B, and the result is stored in the register C (step S69). Therefore, register C
Stores the time elapsed since the start of the constant scan wait.

Subsequently, in step S70, the constant scan set time is compared with the register C, and
Is less than the constant scan set time (10 msec), the process returns to step S68. On the other hand, if the value of the register C is equal to or longer than the constant scan set time (10 msec), the process proceeds to step S71, where the register B is stored in the constant scan wait start TMR work memory 6, and the next constant scan wait process is performed. Prepare.

After the end of the constant scan waiting process, the RUN / STOP switch 13 is judged again (step S72).
After performing the TOP process (step S73), the process proceeds to step S62, where the determination of the RUN / STOP switch 13 is made again, and this is repeated. On the other hand, if the player is facing the RUN side, the process from step S64 is performed.
This is repeated below.

The period of generation of the periodic interrupt is generally such that the pulse signal of the clock circuit 8 is generated from the periodic interrupt generating circuit at power-on or immediately after resetting. Synchronized with time or immediately after reset.

[0019]

As described above, the fixed-period interrupt is synchronized with power-on and immediately after reset. That is, the generation timing of the periodic interrupt is RUN / S
Since the TOP switch is not synchronized with the switch from STOP to RUN, when the RUN / STOP switch is switched from STOP to RUN, as shown in FIG.
For example, a periodic interrupt may occur during output refresh. Here, the input / output refresh is executed at regular intervals due to the configuration of the system. However, as described above, when a periodic interrupt occurs during output refresh, the processing interval of output refresh is not constant. ,
There is a problem that the output interval cannot be made constant by the constant scan setting.

The present invention has been made in order to solve the above-mentioned problem. In order to solve the above-mentioned problem, a fixed-period interrupt is executed by setting a RUN / STOP switch to STOP → RUN or after power-on → R
An object of the present invention is to provide a CPU unit capable of stabilizing an output interval by constant scan setting by synchronizing with UN.

[0021]

According to the method for stabilizing the output interval at the time of setting the constant scan of the programmable controller according to the present invention, a program execution time for executing a predetermined sequence program and a refresh time required for refreshing are described. In order to stabilize the scan time, which is the sum of the above, a programmable controller that performs a constant scan waiting process does not generate a periodic interrupt during refresh.

Further, in order to prevent occurrence of a periodic interrupt during refresh, a periodic interrupt is forcibly generated immediately before the refresh processing.

Further, in order to prevent the occurrence of a periodic interrupt during refresh, an error adjustment time is provided from when a periodic interrupt is forcibly generated immediately before the refresh process to when the process shifts to the refresh process. Is what you do.

Further, when the operation is changed to the RUN operation by the RUN / STOP switch, fine adjustment of the occurrence of the periodic interrupt is immediately performed.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiments of the present invention will be described with reference to FIGS. FIG.
FIG. 1 is a system configuration diagram showing a system configuration of a CPU unit. In the figure, reference numeral 1 denotes a CPU unit;
A CPU chip 2 for executing a program described in the S-ROM 7 or for decoding and executing a sequence program; and a peripheral device I / F unit 3 for receiving a sequence program programmed in the peripheral device 14 by a user.
And a sequence program memory 4 for storing the received sequence program, a device memory 5 for storing the execution result of the sequence program, a work memory 6 used for temporary data saving, etc., and input devices such as switches. An input unit 11 for acquiring information, an output unit 12 for outputting a calculation result to an output device such as a lamp, and a RUN / STOP switch for enabling a user to change the execution and stop of the sequence program 13, a fixed-cycle interrupt generation circuit 9 for counting pulses from the clock circuit 8 and generating an interrupt for the CPU chip 2 based on the count value, and a TMR register 10 used by the CPU unit 1 for time measurement. Here, the fixed cycle interrupt generation circuit 9 and the TMR register 10 continue to operate as long as the pulse signal from the clock circuit 8 is received.

FIG. 2 is a flowchart showing the periodic interrupt processing. FIG. 3 is a flowchart showing processing after turning on the CPU unit power when constant scan is set in the present invention. FIG. 4 is a flowchart showing the fixed-period interrupt occurrence timing fine adjustment processing according to the embodiment of the present invention. FIG. 5 is a diagram showing a periodic interrupt and a timing of an output refresh when a constant scan is set in the embodiment of the present invention.

The CPU unit 1 is equipped with various operation status check functions such as a battery power supply voltage drop check (hereinafter referred to as a battery check), a peripheral device attachment check, and a work memory failure check. At the timing of the interruption from the fixed-period interruption generating circuit 9, an operation state check corresponding to the counter value of the interruption is processed one by one. The processing time of these operation state checks differs for each operation state check function, and the processing time changes even when the check is OK / NG.

First, an internal process when a periodic interrupt is performed in order to perform various operation state checking functions such as a battery power supply voltage drop check (hereinafter referred to as a battery check), a peripheral device mounting check, and a work memory failure check is shown in FIG. This will be described with reference to FIG. Here, the operation state check function performs an operation state check in accordance with the counter value of the interrupt one by one at the timing of an interrupt from the periodic interrupt generation circuit 9. The processing time of these operation state checks differs for each operation state check function, and the processing time changes even when the check is OK / NG.

First, in step S1, it is checked whether the value of the fixed-cycle interrupt occurrence counter for determining which operation state check function is to be executed exceeds the number of operation state check functions (in this case, for example, n). I do. If the result of the check in step S1 exceeds (eg, n + 1), there is no check function corresponding to n + 1, so that the value of the fixed-cycle interrupt occurrence counter is initialized to 0 (step S2), and then to step S3. Transition. On the other hand, if the result of the check in step S1 does not exceed (for example, 1), the process proceeds to step S3.
Move to

In step S3, the value of the fixed-cycle interrupt occurrence counter is determined, and an operation state check according to the value of the counter is performed. For example, if the value of the fixed-cycle interrupt occurrence counter is "0", a battery check is performed (step S4).
If "1", check the attachment of peripheral devices (step S
5) If "n", an operation state check function such as a work memory failure check (step S6) is performed.

After executing the operation state check function, in step S7, 1 is added to the fixed-cycle interrupt occurrence counter, and the fixed-cycle interrupt is terminated in preparation for the next fixed-cycle interrupt occurrence. By performing the above-described processing, it becomes possible to execute each operation state check function at regular intervals.

Next, the operation after the CPU unit is turned on when the constant scan is set in the present invention will be described with reference to FIG. In addition, Usato Hondo is an OS
-Operate based on a program stored in the ROM 7.

When the power of the CPU unit is turned on and the CPU unit 1 is started, first, in step S11, initialization for operating the CPU unit 1 is performed. In this initial setting, setting of an interval of occurrence of a fixed-cycle interrupt and the like are performed.

Subsequently, in step S12, in order to determine whether the CPU unit 1 is in the RUN mode or the STOP mode,
The RUN / STOP switch 13 is determined.
Here, the RUN / STOP switch 13 is set to ST
If the player is facing the OP side, the process proceeds to step S24,
After performing a STOP process for turning off all outputs to stop the operation of the normal CPU unit 1, RUN /
The STOP switch 13 is determined (step S
12) Repeat this.

On the other hand, a RUN / STOP switch 1
If No. 3 is directed to the RUN side, the process proceeds to step S13, where a fixed-period interrupt generation timing fine adjustment process different from the related art is performed.

As shown in the prior art, R in FIG.
UN / STOP switch determination (step S62)
Thereafter, when performing the RUN operation, the output refresh processing occurs immediately. However, if the RUN operation is performed here, a periodic interrupt may occur during output refresh and output to an external device may fluctuate. Therefore, in the present embodiment, step S in FIG.
13 (periodic interrupt generation timing fine adjustment processing).

Here, the fixed-period interrupt generation timing fine adjustment processing will be described with reference to FIG. Step S3
Each time a fixed-cycle interrupt occurs, 0, 1, 2,.
The value of the fixed cycle interrupt occurrence counter which counts up like n is read out to the register A.

Subsequently, at step S32, the register A
Is compared with the current value of the fixed-cycle interrupt generation counter. If the values match, a new fixed-cycle interrupt has not occurred since step S31, so that time waiting is performed until a fixed-cycle interrupt occurs. Step S32 again to perform
Is performed. On the other hand, the value of the register A is compared with the current value of the fixed-period interrupt occurrence counter.
Since a fixed-period interrupt has occurred after step S31, the flow shifts to step S33 to perform the following processing.

In step S33, the TMR register 10
Is stored in the read register B. Note that the TMR register 10 in the present embodiment starts counting when the power of the CPU unit 1 is turned on.
The change is repeated like 0, 1, 2,... 65565,0.

Subsequently, in step S34, the current TM
The value of the register B is subtracted from the value of the R register 10 and stored in the register C. That is, the time after the occurrence of the periodic interrupt has been confirmed in step S32 is stored in the register C.

Here, the processing time required for the periodic interrupt changes depending on the content of the interrupt processing. for that reason,
This fixed-cycle interrupt processing (fixed-cycle interrupt generation timing)
After the fixed-period interrupt process is completed, a predetermined error adjustment time is provided before the refresh process is started so that the refresh time is not taken.

Therefore, in step S35, the time of the register C is compared with the error adjustment time for adjusting so that the fixed period interrupt processing time is extended and the refresh time is not required. As a result of the comparison, if the value of the register C is smaller than the error adjustment time, that is, if the time during which the interrupt processing time is likely to increase after the occurrence of the fixed-period interrupt has not elapsed, the flow returns to step S34. The processing for making the value of the register C equal to or longer than the error adjustment time is repeated. On the other hand, if the result of the comparison indicates that the value of the register C is equal to or longer than the error adjustment time, the processing waits for the error adjustment time, so that even if the processing time of the periodic interrupt is extended, it does not take the refresh time. Therefore, the fixed-period interrupt generation timing fine adjustment processing is ended, and the routine goes to Step S14 in FIG.

Returning to FIG. 2, in step S14, the current TMR register value is set to the constant scan wait start TM
It is stored in the work memory 6 as an R value. Here, the TMR register value stored in the work memory 6 is used to determine whether or not the time has reached the constant scan set time.

Subsequently, in step S15, output refresh processing is performed, and data of the device memory 5 (output) for storing the operation result of the sequence program is written to the output unit 12 in order to output the data to an output device such as a lamp. . In step S16, input refresh processing is performed, and information on input devices such as switches is read from the input unit 11 to the device memory 5 (input).

Subsequently, in step S17, a sequence program is executed based on the information in the device memory 5 (input), and an operation result based on the input condition is output to the device memory 5 (output). Then, an END process for mainly communicating with the peripheral device 14 is performed.

Then, in steps S19 to S22, a constant scan time waiting process is performed. First, the current value of the TMR register 10 is read into the register B (step S19). Subsequently, the constant scan wait start TMR value is subtracted from the register B, and the result is stored in the register C (step S20). Therefore, register C
Stores the time elapsed since the start of the constant scan wait.

Subsequently, in step S21, the constant scan set time is compared with the register C, and
Is a constant scan set time (for example, 10 msec
If less than c), the process returns to step S19. on the other hand,
When the register C has a constant scan set time (for example,
If it is 10 msec) or more, the process proceeds to step S22, and the register B is set to the constant scan wait start TMR.
And prepares for the next constant scan waiting process.

After completion of the constant scan waiting process, the RUN / STOP switch 13 is judged again (step S23).
After performing the TOP process (step S24), the process proceeds to step S12, where the determination of the RUN / STOP switch 13 is performed again, and this is repeated. On the other hand, if the player is facing the RUN side, the process from step S15 is performed.
This is repeated below.

The period of occurrence of the fixed-period interrupt is synchronized with “after power-on → RUN and STOP → RUN” by performing fine adjustment at the timing of “after power-on → RUN and STOP → RUN”. That is, as shown in FIG. 5, the fixed-period interrupt occurs at a timing that excludes the output refresh time. Therefore, according to the present embodiment, a fixed-cycle interrupt does not occur at the time of input / output refresh, the constant scan set time is stabilized, and the error of the output interval is reduced by TM.
Since the error of the R register (for example, the minimum unit of the TMR register = ± 100 μS) can be suppressed, the control of the external device is stabilized.

[0050]

Since the present invention is configured as described above, it has the following effects.

According to the present invention, it is possible to prevent a periodic interruption process occurring during the refresh process, and to suppress the error of the output interval to the error of the TMR register when the constant scan is set. I do.
Further, even if the processing time of the periodic interrupt processing varies, it is possible to reliably prevent the occurrence during the refresh processing.

[Brief description of the drawings]

FIG. 1 shows a system CPU according to an embodiment of the present invention.
It is a system configuration diagram of a unit.

FIG. 2 is a flowchart showing a periodic interrupt process according to the embodiment of the present invention.

FIG. 3 is a flowchart showing processing after power-on of a CPU unit when a constant scan is set in the embodiment of the present invention.

FIG. 4 is a flowchart showing a fixed-period interrupt occurrence timing fine adjustment process according to the embodiment of the present invention.

FIG. 5 is a diagram showing a fixed-period interruption when a constant scan is set and an output refresh timing in the embodiment of the present invention.

FIG. 6 is a system configuration diagram of a conventional system CPU unit.

FIG. 7 is a flowchart showing conventional fixed-cycle interrupt processing.

FIG. 8 shows a conventional CPU when a constant scan is set.
It is a flowchart which shows a process after power-on of a unit.

FIG. 9 is a diagram illustrating a conventional fixed-cycle interrupt and a timing of output refresh when constant scan is set.

[Explanation of symbols]

1 CPU unit, 2 CPU, 3 peripheral device I / F
Section, 4 sequence program memory, 5 device memory, 6 work memory, 7 OS-ROM, 8 clock circuit, 9 fixed-cycle interrupt generation circuit, 10 TMR register, 11 input section, 12 output section, 13 RUN / S
TOP switch, 14 peripheral devices.

Continuation of front page (72) Inventor Hiroyuki Kagami 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) in Mitsubishi Electric Corporation 5B098 AA05 BA06 BA15 BB01 GA01 5H220 BB09 CC05 CX03 EE12 FF07 GG04 JJ16 JJ26 JJ34 LL01

Claims (4)

[Claims] 1. A programmable controller that performs a constant scan waiting process to stabilize a scan time, which is a sum of a program execution time for executing a predetermined sequence program and a refresh time required for refreshing, during a refresh. A method for stabilizing an output interval when a constant scan is set in a programmable controller, wherein a periodic interrupt is not generated. 2. The programmable controller according to claim 1, wherein a fixed-cycle interrupt is forcibly generated immediately before the refresh processing to prevent occurrence of a fixed-cycle interrupt during refresh. Output interval stabilization method. 3. An error adjusting time is provided for preventing occurrence of a fixed-period interruption during refreshing, forcibly generating a fixed-period interruption immediately before the refreshing processing, and then proceeding to the refreshing processing. 4. The method according to claim 3, wherein the constant output interval is set when the constant scan is set in the programmable controller. 4. A RUN / STOP switch,
4. The method for stabilizing an output interval when a constant scan is set in a programmable controller according to any one of claims 1 to 3, wherein fine adjustment of occurrence of a fixed period interrupt is immediately performed when the operation is changed to the RUN operation.