JP2000056816A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the PC which prevents an increase in power consumption due to a high-performance computing element and a memory. SOLUTION: An input module 5, an output module 10, a user program memory 1, a write count part 11 for the frequency of variation of input and/or output, and a computing element 2 which executes a user program are connected by a system bus 6 and a computing element switch 3, a system timer 8 and a system program memory 4 are connected to the computing element 2. The operation system of the computing element 2 is switched by the computing element switch 3 according to the frequency of variation of the input and/or output of the write count part 11 to suppress the power consumption of the computing element 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter, referred to as a PC), and more particularly to a system for stopping an arithmetic unit when there is no change in input / output and reducing power consumption.

[0002]

2. Description of the Related Art A conventional PC scanning process will be described with reference to FIG. FIG. 7 is a block diagram of a conventional PC. In FIG. 7, 1 is a user program memory for storing a program or the like for instructing a processing operation, 2 is a computing unit for taking out programs in the user program memory in a predetermined order, taking in, calculating, and sending out data; 4 is a system ROM for storing a program for operating the PC, 5 is an input module for processing input signals, and 6 is a data exchange for connecting an input module, an output module, a user program memory, a computing unit and the like. The system bus 8, at regular intervals,
A timer that activates system processing (such as updating a timer or monitoring a write counter) that must always be performed by the PC. This system processing detects the change in the output coil of the timer and determines the status of the system processing. Reference numeral 9 denotes an output module for holding a constant cycle signal between the system timer and the arithmetic unit, and 10 an output module for holding an output signal for driving an external device. The computing unit 2 is connected to the user program memory 1, the input module 5, and the output module 5 by a system bus 6. Further, a system ROM 4 and a system timer 8 are connected to the computing unit 2, and a PC is connected. It is configured.

[0003] The scanning process will be described with reference to FIG. FIG. 8 is a sequence diagram of a scanning process in a conventional PC. As shown in the figure, changes in external inputs X0 and X1, such as limit switches and relay contacts, for example, ON / OFF signals, are taken into the arithmetic unit 2, for example, a CPU unit, through the input module 5. If the external inputs X0 and X1 turn on at the same time, the output Y0 turns on. Further, when the external input X2 or X3 is turned on, the output Y1 is turned on.

Next, the operation of FIG. 9 will be described. FIG.
It is a flowchart figure of a scanning process. Arithmetic unit 2
Is the current input state of the input module 5;
Read X3. An operation is performed on the read X0 to X3 in accordance with the program stored in the user program memory 1. Since the program is read for each step and the program is executed sequentially in accordance with the calculation result, the program is written to the output module 5 and output. This execution operation is repeated until the last step of the user program. The system timer 8 outputs a scanning cycle signal from the beginning to the last step of the user program and a time signal for performing necessary processing.
The user program describes what input is taken, what kind of operation is executed, and where it is output.

Conventionally, as described above, an input change is detected by a scanning method in which the user program 1 is scanned from the beginning to the end, returned to the beginning, and repeated.
Control was running. This scanning time is
Although it depends on the number of steps and the processing content of the sequence program, it is generally about several msec to several tens msec.

Recently, various functions have been demanded of the PC, and the PC has been multi-functionalized to increase the program capacity. In the above-mentioned scanning method, when the program capacity is increased, the scanning time is proportionately longer. Therefore, the scanning detection interval is longer than the input change interval, and the input change, for example, 10 msec.
In some cases, a change of about c cannot be captured.

As a measure against this, conventionally, the above problem has been often dealt with by a method of shortening the scanning time. In other words, this method is to increase the operation speed of the arithmetic unit, increase the scanning speed, and reduce the scanning time. Reducing the scanning time requires a high-speed computing unit and a large amount of memory. Since the power consumption of the high-speed arithmetic unit increases in proportion to the operating frequency, the higher the speed, the higher the power consumption of the arithmetic unit.

[0008]

In the programmable controller of the prior art, since all changes in input / output are detected by executing the scanning of the user program, the execution time of the control operation is defined by the scan time. In general, it could not follow faster processing and response.

Therefore, in order to improve the responsiveness of the entire system, it is necessary to increase the operation speed and reduce the scan time. Normally, a high-speed computing unit, a high-speed memory, or the like is used to increase the operation speed. However, generally speaking, a device with a high processing speed consumes power in proportion to the processing speed. Since most of the power consumption of the PC is occupied by the computing unit, adopting the scanning method using a computing unit with a high computing speed has a disadvantage that the power consumption increases as a result.

[0010] In order to solve this drawback, in a PC having an input module, when there is no change in the information received from the control object between the previous time and this time, the PC which stops reading the information from the input module is used. is there. As a technique related to this, there is a technique described in Japanese Patent Application Laid-Open No. 3-296104. Further, in the sequence control device, the operation of the program processing device is always suppressed, and when the information is changed, the program processing device is operated while the program processing device executes the program once. There is a cans control device. A technique related to this is disclosed in Japanese Patent Application Laid-Open No. 54-62474.

In the former case, since the number of times of input / output signal transfer processing is reduced, idle time is generated in a time area allocated to input / output signal processing, and system processing can be executed effectively. However, consideration is given to power consumption. It was not enough. Regarding the latter, the power consumption and heat generation of the program processing device are considered, but since the operation of the program processing device is always suppressed, adaptation to a control object that changes frequently or slightly decreases. There was insufficient consideration for sex.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and detects a change in input and output without executing a user program by using only a scanning method. By executing the user program in a so-called event-driven state in the state described above, the operation unit is stopped or the execution speed of the operation is slowed down except for the period in which high-speed operation is required, so that the control target having various changes can be controlled. It is an object of the present invention to provide a PC that appropriately responds and reduces the power consumption of the arithmetic unit.

[0013]

In order to achieve the above object, a configuration of a programmable controller according to the present invention comprises an input module, an output module, a user program memory, and writing of the number of changes of an input and / or an output. A counting unit and a computing unit for executing a user program are connected by a system bus, and a computing unit switching unit, a system timer, and a system program memory are connected to the computing unit. The operation system of the arithmetic unit is switched by the arithmetic unit switching unit based on the number of output changes, so that power consumption of the arithmetic unit is suppressed. In the above-mentioned programmable controller, a system timer and a write counter are provided in the arithmetic unit. In the programmable controller according to the preceding aspect, a differentiating circuit is provided in a section for receiving an input signal from each device to be controlled in the input module.

The functional configuration of the programmable controller having the above configuration will be described. An input device (input module) having a transmitting means for detecting a change in input and transmitting the detected input change to a computing unit, a computing unit having a low power consumption mode (standby mode), and a user program storing a user program An arithmetic unit comprising a memory, a timer for performing a periodic system processing, and a write counter for comparing write data of an input change signal from the arithmetic unit and counting the number of times the write data differs is provided. It is a thing.

Further, a differentiation circuit is provided for each input of the input module, and means for detecting a change in the input and notifying the arithmetic unit is provided. By providing the means, the arithmetic unit can detect only when there is a change in the input, and it becomes possible to execute the operation of the user program by the change in the input.

Further, in the control system, since there are many changes immediately after the start-up, it is highly likely that the processing cannot catch up simply by a method of simply detecting and processing a normal input change. The high-speed scanning method is performed on the user program.

Normally, the operation unit performs an operation in word units, but the operation of the coil of the output module is a bit change. The PC normally reads the output module coil in word units and writes bit changes,
The arithmetic unit performs so-called read-modify-write. By utilizing this characteristic, read data and write data are compared to constitute the above-described write counter.

The arithmetic unit measures the amount of change in the write counter per unit time, thereby detecting a change in the control system. The arithmetic unit can detect that the fluctuation of the control system has been reduced, and can thereby cause the arithmetic unit to be in the low power consumption mode (standby mode) or to stop the operation except for the required system processing in which the fluctuation of the control system is large. is there. The object of the invention is achieved.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a PC according to the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of an embodiment of a PC according to the present invention, FIG. 2 is an explanatory diagram of a flowchart of the event-driven system processing of FIG. 1, and FIG. 3 is an explanation of an event-driven system and a scanning system of the PC of FIG. FIG. 4 is an explanatory diagram of the event-driven system processing of the PC of FIG. 1, FIG. 5 is a configuration diagram of an input module of another embodiment of the PC of FIG. 1, and FIG. It is a lineblock diagram of another embodiment.

In FIG. 1, the basic configuration of a PC according to an embodiment of the present invention has many parts having the same specifications as those of the conventional PC shown in FIG. Also, in FIG. 1, the same reference numerals as those in FIG. 7 have the same functions, and thus the description thereof will be omitted, and characteristic components will be described. In FIG.
In the high-speed processing mode, the program in the user program memory is fetched in a predetermined order, data is fetched, operated, and sent out. , An arithmetic unit that performs high-speed processing only in the event driven case, an input module 6, an output module 10
An operation stop unit for changing the operation mode of the operation unit and the PC according to the state of the operation unit; 7 is an input change interrupt signal, 11 is a write counter for counting the number of different output signals, and 12 is a write counter 1
1 is a clear signal.

The configuration of the PC of FIG. 1 to which the above-described devices are connected is almost the same as that of FIG. 7, but the differences will be described. P in FIG.
C connects the write counter 11 to the system bus 6 and counts the number of times of writing different data from the arithmetic unit 2 to the output module 10 from the arithmetic unit 2 via the system bus 6; In step 2, the count is read. The operation stop unit 3 is connected to the operation unit 2, and stops or stops the operation unit 2 according to the magnitude of the count number. Further, it is connected to the system timer 8 and outputs a necessary signal from the system timer 8, for example, a clear signal of the write counter 11 every unit time.

The PC having the above configuration will be described with reference to FIGS. Now, it is assumed that the PC is operated by the scanning method. The computing unit 2 and the like consume normal power (step S ₁ ). Next, in this embodiment, a write counter 11 for counting the number of times of writing different data to the output is provided, and the write counter 11 counts the number of times of writing different data from the arithmetic unit 2 to the output module 10 (step S1). S ₂ ).

When different data is written to the output module 10, since the input has changed, the input change is detected by the number of times of writing the different data to the output. The number of times n of writing the data per unit time is transmitted from the counter 11 to the arithmetic unit 2 via the system bus, or the arithmetic unit 2 reads out from the counter 11 via the system bus. (Step S _3). In the arithmetic unit 2, a reference write counter number N per unit time is set in advance, and N is compared with n. Accordingly, the arithmetic unit 2 monitors the number of times of writing, and can determine that the change of the control target system has decreased because the number of times of writing per unit time decreases.
(Step S _4).

As a result, if N ≧ n, it is determined that the number of different data to output is small and the change of the control object is small,
Switching to the event driven mode, the operation stop unit 3 stops the operation unit 2 or switches to the energy saving mode. Switching of stop or power saving mode may be facilitated by the frequency reduction circuit reduces the circuit or sequence timer of the supply voltage (Step S _5). N
<If n, to sustain the scanning method (Step S _6). Next, the write counter 11 is cleared in a unit time by the signal 12 from the system timer 8,
Returns to the step S _2, repeated until the step S _6.

As described above, the operation stop unit 3 stops the operation unit 2 in the low power consumption mode or stops the operation, and changes the operation mode of the PC from the normal scanning mode to the operation mode by detecting the input change interrupt signal 7. It can be changed to the event driven system.

Further, referring to FIGS. 3 to 6, the difference between the scanning system and the event-driven system according to the present invention will be described, and FIG. As described above, in the scanning method, the operation unit 2 uses the instruction signal from the system timer 8 to perform (A) and (B) on the entire user program.
(B) and (c) are sequentially detected.

As shown in FIGS. 3 (b) and 3 (c), in the event-driven system, the arithmetic unit 2 performs an interrupt process only when an input change appears in the user program.
In other cases, the arithmetic unit 2 is in the low power consumption mode or is stopped. FIG. 3B shows a case where the rising edge becomes event-driven, and FIG.
Is a case where an event is driven at the falling edge. Either one may be used, but in this explanation, taking the case where the event is driven by the rising edge as an example,
I will explain.

In FIG. 4, first, since there are many changes immediately after the start of the control target of the PC, the arithmetic unit 2 executes the scanning method by high-speed processing which consumes a large amount of power. As described above, as described above, the operation stop unit 3 causes the operation unit 2 to be in the low power consumption mode or to stop, depending on the number of counts of different data input to the output module 10 of the write counter 11.

In the above state, the count number of the write counter 11 becomes small, the arithmetic unit 2 becomes the event-driven system, and the execution of the interrupt program causes the high-speed processing mode only at that time. In this case, the operation stop unit 3 again switches to the low power consumption mode or the mode for stopping the operation unit 2.

The PC according to the present invention is not limited to the above embodiment, and many modifications of the input module and the write counter can be considered. FIG. 5 shows the PC of FIG.
5 is another configuration example of the input module of FIG. FIG. 2 exemplifies a case in which one module has 16 points. However, a differentiating circuit 13 is provided in a circuit for taking in an input signal 16 from each device to be controlled, and a sum signal is output by a logical operation unit 14 of the output of the differentiating circuit 13. 15 is detected and output to the arithmetic unit 2 as an input change interrupt. The sum signal 15 causes the computing unit 2 to indicate that the input has changed, and causes the computing unit 2 to perform event-driven processing.

FIG. 6 shows an embodiment in which a computing unit 2A optimized in advance so as to be suitable for a PC according to the present invention is used. The arithmetic unit 2 includes a system timer 8, a write counter 11, and an interrupt control circuit 18.
Are arranged in the hardware of the arithmetic unit 2 to reduce the load on the system software. The PC shown in FIG. 6 is the same as that in FIG. 1, and thus detailed description is omitted.

[0032]

As described above in detail, according to the configuration of the present invention, when the control processing system is unstable immediately after the start of startup, the operation of the user program is performed by high-speed scanning as in a normal PC. By doing so, it is possible to prevent a reduction in response speed due to overhead or the like when processing is performed using interrupts. When the control processing system is stable and the input change is reduced, the magnitude of the input change is determined by a write counter, the method is switched to an event-driven processing method based on input change detection, and the operation unit is operated with low power consumption. By switching to the mode or stop, the power consumption of the arithmetic unit can be reduced without impairing the function of the PC.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a PC according to the present invention.

FIG. 2 is an explanatory diagram of a flowchart of the event-driven system processing of FIG. 1;

FIG. 3 is an explanatory diagram of an event-driven system and a scan system of the PC in FIG. 1;

FIG. 4 is an explanatory diagram of an event-driven system process of the PC in FIG. 1;

FIG. 5 is a configuration diagram of an input module according to another embodiment of the PC in FIG. 1;

FIG. 6 is a configuration diagram of still another embodiment of a PC according to the present invention.

FIG. 7 is a block diagram of a conventional PC.

FIG. 8 is a sequence diagram of a scanning process in a conventional PC.

FIG. 9 is a flowchart of a scanning process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... User program memory, 2 ... Operation unit, 2A ... Optimization operation unit, 3 ... Operation stop unit, 4 ... System ROM, 5 ...
Input module 6 Data bus 7 Input change interrupt 8 System timer 9 Timer interrupt 10
Output module, 11 Write counter, 12 Counter clear signal, 13 Differentiator circuit, 14 Logical operation unit (sum) 15 Interrupt signal, 16 Input signal from device, 17 Input data, 18 Interrupt control circuit

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Tsurumasa Matsushita 46, Tomioka, Oji, Nakajo-cho, Kitakanbara-gun, Niigata Prefecture Inside the Industrial Equipment Division, Hitachi, Ltd. No. 1 Hitachi, Ltd. Industrial Equipment Division (72) Inventor Yasunori Katsube 7-1-1 Higashi Narashino, Narashino-shi, Chiba F-term within Hitachi Keiyo Engineering Co., Ltd. 5H220 BB01 CC05 CX03 CX05 EE12 JJ16 JJ17 JJ26 JJ34 KK03 LL02

Claims (3)

[Claims] 1. An input module, an output module,
A user program memory, an input and / or output change count writing / counting unit, and an arithmetic unit for executing the user program are connected by a system bus, and the arithmetic unit is connected to the arithmetic unit by a system timer and a system timer. Are connected to each other, and the operation system of the arithmetic unit is switched by the arithmetic unit switching unit based on the number of changes in the input and / or output of the write counting unit, so that the power consumption of the arithmetic unit is suppressed. Programmable controller characterized by: 2. The programmable controller according to claim 1, wherein a system timer and a write counter are provided in the arithmetic unit. 3. The programmable controller according to claim 1, wherein a differentiating circuit is provided in a portion for receiving an input signal from each device to be controlled in the input module.