JP2002358139A - Low power consumption processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low power consumption processor capable of operating with low power consumption for a program from which any quick response is not expected, and quickly operating with the power consumption scarified for a program whose priority order is high to be processed within a limited time or a program from which a quicker response is expected. SOLUTION: This processor is provided with a processor 11 for performing a program, a plurality of performance time timer counter device 21 whose count enable is possible for measuring the performing time of a program, a performance target register 21 for storing the target value of the performance time of each program, an arithmetic unit 27 for comparing the performance target value with the performance time, an LP mode counter device 28 for storing the arithmetic result, and a controller 31 for controlling clock supply to the processor based on the output signal of the LP mode counter device 28.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power consumption processor for controlling power consumption, and more particularly to a processor suitable for use in portable electronic devices such as a notebook personal computer and a PDA.

[0002]

2. Description of the Related Art The power consumed by a processor operated by a clock signal increases in proportion to the frequency of the clock signal. In electronic devices using processors, it has been an important issue to reduce power consumption.

Conventionally, as a technique for reducing the power consumption of a processor, there has been known a technique of performing control such as lowering a clock frequency or stopping a clock supply to an unused circuit block in a low power consumption mode. I have. For example, it has been proposed in Japanese Patent Application Laid-Open No. 10-301659.

Japanese Patent Application Laid-Open No. 7-200106 discloses that power is supplied only to peripheral devices specified by a processor in accordance with the operation mode of the processor, and power consumption is reduced by controlling the power supply. Is shown to do.

Japanese Patent Laid-Open Publication No. Hei 10-133789 discloses a means for counting a system clock in order to prevent the amount of heat generated due to power consumption from becoming more than a certain value regardless of the behavior of a program to be executed. A processor having means for counting the number of operation clocks of each module, and when the activation rate of the module reaches a predetermined value, the module or the entire system shifts to a low power consumption mode.

In Japanese Patent No. 275520, attention is paid to the fact that the processor always waits for an idle state in which a hardware interrupt is expected during execution of a program or waits for transition to the next task processing. A processor configured to reduce power consumption by interrupting the clock supply of the processor at the time of task transfer is shown. This patent includes a means for generating a timer interrupt signal after a predetermined time after the processor is started after entering a specific idle routine, and a means for generating a timer interrupt signal when the processor is completed at the end of one task processing of the task processing routine and after a predetermined time. Means for generating a signal.

[0007]

As described above, one of the conventional methods for reducing the power consumption of a microprocessor in a system using a microprocessor, which is particularly expected to operate with low power consumption. A known method is to lower the clock frequency. In this method, there is a problem that all the programs are uniformly slowed down, the response is deteriorated, and the processing does not end within the time limit.

As another conventional method, there is known a method in which an interrupt wait state is set to an idle (IDLE) state, and a clock supply is stopped in the idle state. However, in this method, it is impossible to reduce the power consumption while the processor is executing the program, and there is a problem that the effect on the power consumption is small.

In view of the above problems, the present invention controls the execution time for each program, and for a program with little effect, the processor itself actively creates an IDLE state so that the program may run slowly. For programs with higher priority that need to be processed within the time limit and programs that expect faster response, run faster with lower power consumption. It is an object to provide a low power processor with control means that can be controlled.

[0010]

A low power consumption processor according to the present invention includes a processor for executing a program, a storage device for setting an execution target value for each program, and a counter for measuring the execution time of the program. If the execution time of the program is less than the execution target value,
Means for stopping the supply of the clock of the processor until the target execution time is reached, and controlling the execution time and power consumption of each program by rewriting a storage device for setting the target execution value of each program. It is characterized by the following.

A low power consumption processor according to the present invention includes a processor for executing a program, a plurality of timer counter devices capable of resetting and enabling a count from the processor to measure the execution time of the program, and a target execution time for each program. A plurality of storage devices for storing values, an arithmetic unit for comparing an execution target value with an execution time, a wait counter device for storing an operation result, and a clock supply to a processor based on an output signal of the wait counter device. And a control device for controlling.

Further, the present invention resets the timer counter for measuring the execution time at a desired position of the program according to a command of the processor, and enables the counter. Means for calculating the difference between the target execution time and the execution time by the arithmetic unit at the position, and storing the calculated value in the weight counter device; It is characterized by comprising a means for decrementing the counter device in synchronization with the clock, and a control means for stopping the supply of the clock to the processor when the wait counter value is 1 or more.

As described above, the storage device for setting the execution target value for each program in the processor, the counter means for simultaneously measuring the execution time of the program, and the execution time of the program with respect to the execution target value And a means for stopping the supply of the clock of the processor until the target execution time is reached, so that the target execution time can be controlled for each program. Also,
Since the storage device for setting the execution target value for each program is rewritten, means for controlling the execution time and power consumption for each program are provided. For programs with higher priority that need to be processed within the time limit and programs that expect faster response, run faster with lower power consumption. Can be

Further, a low power consumption processor according to the present invention is connected to a processor for executing a program, a plurality of storage devices for storing a target value of the execution time of the program, and a target value of the execution time. And a means for controlling clock supply to a processor from a status output signal from the counter stack. The counter stack apparatus operates counters of respective levels simultaneously. A counter function for setting the upper-level counter to a value indicating that the target execution time has been reached when the lower-level counter value reaches the target execution time. When the highest level counter reaches the execution target time, its status signal And outputs.

In the invention having the above configuration, since the counter stack device for measuring whether the execution target value has been reached is provided, even when the same program is nested,
It is possible to control the execution time and power consumption for each program. In addition, when the lower-level counter value reaches the target execution time, a function for setting the higher-level counter to a value indicating that the target execution time has been reached is provided. Since the clock supply to the processor has been stopped because the target value has not been reached and the previously executed program has reached the execution target value, it is possible to cause the processor to start supplying the clock, Even a nested program can be executed in a more accurate time with respect to the execution target value.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a system configuration of a processor according to the first embodiment of the present invention.

In FIG. 1, a processor 11 has a configuration of a normal processor portion.
A program stored in a memory (not shown) is read, and the program is executed while performing data access. An address bus 12, a data bus 17, and a control bus 18 are connected to the processor 11.

For the processor 11, the interrupt generator 1
3, a plurality of interrupt signals 16a are input to the interrupt terminal of the processor 11. The processor 11 processes the requested task based on the input interrupt signal.

The clock signal 14b generated by the clock generator 14 is supplied to the clock input terminal of the processor 11 as a signal 16b through the AND gate 15. The processor 11 executes a process at a speed according to a given clock signal.

The execution time timer counter 21 measures the execution time of a task. In this embodiment, the first, second, and third execution time timer counters 21a, 21a
1b and 21c. That is, as will be described later, this embodiment describes a case where three tasks are processed, and the first, second, and third execution time timer counters 21a, 21b,
21c is provided.

Then, in order to measure the execution time according to each task, the processor 11, the data bus 17 and the data bus 17 are provided to each of the first, second, and third execution time timer counters 21a, 21b, 21c. Processor 1
1 and a control signal 22 for timer enable. Further, the execution time timer counters 21a, 21a,
It is assumed that the reset and count operations of 1b and 21c are controlled.

In this embodiment, three examples of the execution time timer counter are shown, but the present invention can be applied without any problem even with other numbers of components. In this embodiment, the first, second, and third execution time timer counters 2
1a, 21b, and 21c operate according to the respective tasks as described later.

The execution target register 23 stores a target processing time to be executed by each task. In this embodiment, three execution target registers 23a, 23b, and 23c are provided for three tasks. Each execution target register 23a, 23b, 23c has a processor 1
1 are connected by a data bus 17 and a read / write signal 24, and the respective execution target registers 23a and 23
It is assumed that the data b and 23c are at least writable and possibly readable by the processor 11. In this embodiment, the target values of the execution target registers 23a, 23b, and 23c are set corresponding to the respective tasks.

The outputs of the execution time timer counter 21 and the execution target register 23 are output from a bus 25 and a bus 26, respectively.
The output of one of the register values of the execution target register 23 and the output of one of the timer values of the execution time timer counter 21 are selectively supplied to the subtractor 27, although not shown in FIG. It is input to the subtractor 27.

The subtractor 27 subtracts the execution target register value-the execution time timer counter value. If the operation result is positive, that is, if the execution target register value> the execution time timer counter value, the value is subtracted. Can be written to any of the LP mode counters 28. In this embodiment, the LP mode counter 28 also includes first, second, and third LP mode counters 28a, 28b, and 28c corresponding to tasks.

The written LP mode counter value is decremented until it becomes 0 by the system clock supplied from the control bus 18 via the bus 29. When the respective counter values of the LP mode counter 28 are 0, signals Z1, Z2, and Z3 indicating 0 are input to the low power consumption control signal block circuit 31 through the bus 30. In this embodiment, the first LP
The mode counter 28a outputs a Z1 signal, the second LP mode counter 28b outputs a Z2 signal, and the third LP mode counter 28c.

The low power control block circuit 31 is connected to the LP mode counter 28 through a bus 32.
And a task end signal such as a return instruction signal.

Low power consumption control block circuit 31
From when the value of the LP mode counter 28 of the currently executed foreground task processing is not zero and when the interrupt request signal 16a from the interrupt generator 13 is not requested, the AND gate 15 is Lo
It is assumed that a w-level clock supply stop signal 31a is output. The power consumption control block circuit 31
Supplies a control signal 31b to the clock generator 14 in order to generate a clock corresponding to the task.

The above is the description of the simple configuration of FIG. 1 showing a typical embodiment. Based on this, the operation of the embodiment of the present invention will be described in detail.

FIGS. 3 to 9 are diagrams showing the relationship between task operations of the processor. In these figures, the horizontal direction represents a time axis, and a time unit per span is T. In the vertical direction, the operation of the processor 11 is classified, and indicates a state in which a solid line is drawn in a state of waiting for a task, a task 1, a task 2, and a task 3 are running.

Assume that the state of the task being executed by the processor is as shown in FIG. In FIG. 3, task 1 is a process requiring a total of 4T time to execute, and tasks 2 and 3 require 2T and 1T respectively.

In the case of task switching, an interrupt of a task processing request enters the processor 11, the task requested by the interrupt request runs, and at the end of the task, a return instruction from the interrupt runs and returns. And

In the description of FIGS. 3 to 9, the priorities of tasks 1 to 3 are: task 1 <task 2 <task 3
And

FIG. 3 shows a normal operation in which the processor 11 does not perform the low power consumption operation. This operation will be described with reference to FIG. As shown in FIG. 3, at 0T time,
At 1T time in task waiting state, a request for task 1 enters,
Task 1 runs. Then, a request for task 2 enters at 2T time, and this task ends at 4T time,
Return to the task 1 run.

At time 5T, a task 3 request is received, and task 3
Travels, task 3 ends at time 6T, and returns to task 1. Running of task 1 ends at 8T time, 8T-10T
Until the task waits.

It is assumed that the operation from 10T to 20T is the same as the operation from 0T to 10T.

In the operation of FIG. 3, if no low power consumption design is performed, the task waits and one of tasks 1 to 3 is running. Therefore, the processor 11 runs (RU) from 0T to 10T.
N) state.

Here, as a measure of power consumption, the power consumption is set to 1 W in the RUN state, 1/10 W in the IDLE state, and 1/10 W in the clock frequency when the processor runs normally. Assume 1 / 2W. Assuming such a situation, in the example shown in FIG. 3, the power is consumed by 20 TW since all of the devices are in the RUN state during the period of 0 to 20 T.

Considering the throughput during the task processing within the 20T time as a guide for the processing, the throughput in the example of FIG.
4 for task 2 and 2 for task 3 for a total of 14 throughput.

Here, in the case of the conventional task waiting time described above, the clock supply to the processor 11 is stopped, and
FIG. 4 shows a method for setting the IDLE state. In the case of this example, between 0 and 1T, between 8T and 11T, 1
The IDLE state is set between 8T and 20T.

The power consumption is 1 / in the case of the IDLE state.
Since the power is 10 W, the power consumption is as follows in FIG.

1 / 10W × 6T + 1W × 14T = 14.6TW

The throughput is 14.

As a problem in the case shown in FIG. 4, when there is 6T during the 20T period where no task is running, the power consumption can be reduced by that amount, but there is always a task request. Has a problem that power consumption does not decrease.

FIG. 5 shows a case in which the operating frequency is reduced to 1/2 of the normal frequency in addition to the conventional method shown in FIG. As shown in FIG. 4, when the operating frequency is reduced to 通常 of the normal frequency, the time required to execute tasks 1 to 3 doubles to 8T, 4T, and 2T, respectively.

In the case of FIG. 5, the power consumption is IDL
Since the power is 1/10 W in the E state, the power consumption is as follows.

1 / 10W × 6T + ／ W × 14T = 7.6TW

The throughput is 7.

When the operating frequency is reduced as in the example of FIG. 5, the power consumption is surely reduced, but there is a problem that the throughput is similarly reduced.

According to the present invention, the power consumption is reduced without reducing the throughput.
FIG. 6 shows an operation example of the processor of the present invention having the configuration shown in FIG.

Normally, for tasks 1 to 3 requiring 4T, 2T, and 1T, respectively, in order to reduce power consumption,
Task 1 is 8T, task 2 is 6T, twice the execution time, 3
The target value is set to double, and task 3 is controlled so as to run in the same 1T time.

For this reason, the processor 21 previously registers each of the execution target registers 21 of FIG.
Values corresponding to 8T, 6T, and 1T are set for a, 21b, and 21c.

In the description of the operation shown in FIG. 6, as in FIGS. 3 and 4, the task is in a task waiting state from 0T to 1T.

At time 1T, a request interrupt for task 1 enters processor 11 as signal 16a through interrupt generator 13 of FIG. The processor 11 executes the task 1 program in response to the interrupt.

The start portion of the program of task 1 where the execution time is to be controlled is provided with an execution time timer counter 21.
Is controlled, and when the processor 11 reaches there, the first execution timer counter 21a is reset and then enabled.

For example, in the case where an instruction for controlling the execution timer counter 21 and an STIM instruction are mounted in the processor 11, the following instruction is added to the start portion for which the execution time is to be controlled, for example, the start portion of the task 1. Put in.

STIM 1 (Instruction to reset the first execution time timer counter 21a and enable the counter)

With this instruction, the first execution time timer counter 21a starts measuring the execution time of the task 1.

At the position of the 2T time, the request interrupt of the task 2 enters the processor 11 as the signal 16a through the interrupt generation circuit 13 of FIG. Task 2
Also, in the same manner as at the start of the task 1, the execution time of the task 2 is started to be measured by resetting the second execution time timer counter 21b and enabling the counter.

At time 4T in FIG. 6, the execution of task 2 is completed, and a return instruction from the interrupt is executed to return to task 1. Immediately before that, the second execution time timer counter 21b of task 2 and the second 2. An instruction to compare the value of the execution target register 23b is issued. For example, the command is CTIM
As an instruction, the next instruction is executed.

CTIM 2 (the second execution target register 23b-the second execution time timer counter 21b, and if the result is positive, the second L
The value is stored in the P mode counter 28b. )

If the second LP mode counter 28b contains a value other than zero, the second LP mode counter 28b automatically decrements the value to zero, and controls the status signal 30 which is a Z2 signal indicating a value of zero, to the power consumption control. It outputs to the circuit 31 as a status signal of the LP mode counter 28.

In the example shown in FIG. 6, the value of the time (6T-2T = 4T) is loaded into the second LP mode counter 28b, and during the 4T period, the status signal 30 as the LOW level Z2 signal is supplied to the low power consumption control block circuit. 3
1 is output. In response to the LOW level input of the status signal 30, the low power consumption control block circuit 31
Sets the control signal 31a to the LOW level and stops the clock supply signal 16b from the AND circuit 15.

As described above, when the execution time is shorter than the execution target of the task 2, an IDLE state in which the clock is actively stopped is created, and the processor 11 enters the low power consumption state.

In the example shown in FIG.
At time T, the request interrupt of task 3 is
And enters the processor 11 as an interrupt signal 16a through the interrupt generation circuit 13 of FIG. This interrupt request signal 16a
Is also input to the power consumption control circuit 31, so that the power consumption control signal 31a is set to the HIGH level in response to the interrupt request signal 16a, and the clock signal 16b is supplied to the processor 15.

In the task 3, the third execution time timer counter 21c is reset and the counter is enabled to start measuring the execution time of the task 3.

When the execution of the task 3 is completed, a return instruction from the interrupt is executed to return to the task 2. Immediately before that, the values of the third execution time timer counter 21c and the third execution target register 23c of the task 3 are read. Instruction to compare.

For example, if the instruction is a CTIM instruction, the following instruction is issued.

CTIM 3 (Third execution target register 23c-third execution time timer counter 21c. If the result is positive, the third L
The value is stored in the P mode counter 28c. )

If the third LP mode counter 28c contains a value other than zero, the third LP mode counter 28c automatically decrements the value to zero, and outputs a status signal 30 as a Z3 signal indicating that the value is zero. It outputs to the block circuit 31 as a status signal of the LP mode counter 28.

Now, task 3 requires 1T time to run the main body. Further, since the register value of the third execution target register 23c is also 1T time, CTIM3 is a comparison value of 0 or less, so that the status signal 30 does not change, and the process returns to the task 2 at the position of 6T. At the position of 6T, since the Z2 signal of the second LP mode counter 28b is still at the LOW level, the state becomes the IDLE state again, and the clock supply 16b from the AND circuit 15 stops.

At the position 8T in FIG. 6, the value of the second LP mode counter 28b becomes 0, so that the signal Z2 from the second LP mode counter 28b becomes HIGH, the status signal 30 becomes HIGH, and the power consumption control. Control signal 3 from block circuit 31
1a becomes HIGH, the clock supply 16b is started from the AND circuit 15, the return instruction from the task 2 to the task 1 runs, and the running returns to the task 1.

At the position 11T, the task 1 terminates the processing of the task 1 and returns to the task waiting state. Immediately before that, the first execution time timer counter 21a of the task 1 and the first execution target register An instruction to compare the value of 23a is performed.

For example, if the instruction is a CTIM instruction, the following instruction is executed.

CTIM 1 (First execution target register 21a-first execution time timer counter 23a. If the result is positive, the first L
The value is stored in the P mode counter 28a. )

If the first LP mode counter 28a contains a value other than zero, the first LP mode counter 28a automatically decrements the value to zero and sends a Z1 signal indicating a value of zero to the power consumption control block circuit 31. This is output as a status signal of the 1LP mode counter 28a.

In the example of FIG. 6, at the position of 11T, the first execution time timer counter value 21a has already counted 10T, and the value of 8T of the first execution target register 23a is 8T.
Because it is larger, the status Z1 signal remains at the HIGH level and returns to the task waiting state without stopping the clock supply. 12T to 20T perform almost the same operation as 0 to 11T.

As described above, in the example of FIG. 6 using the present invention, the power consumption is as follows.

The power consumption is 1 / in the case of the IDLE state.
Since it is 10 W, it is as follows.

1/10 W × 10 T + 1 W × 10 T = 11.0 TW

The throughput becomes a total of 10, which is lower than the total running of FIGS.
Task 3 is throughput 2, task 2 is throughput 4
And the processing is the same as in FIGS.

Further, as compared with FIG. 5, the operating frequencies of all the tasks are not reduced. For this reason, since the vehicle travels fully in the 1T period as in the task 3, the throughput does not decrease in the processing that expects a high speed.

Further, by changing the value of the execution time target register 23, it is possible to easily change the power-off and high-speed operation tray-off.

Another operation example using the present invention will be described with reference to FIG. In FIG. 7, as in FIG.
2 shows an example of processing 2 and 3 each two times.

For task 1, the first task is requested at time 1T, and after 3T time after the end of task 1,
Assume that the request comes in the second time of task 1. As for task 2, task requests are received at fixed time intervals of 2T and 12T.
It is assumed that a task request comes at regular time intervals such as T and 15T.

In FIG. 7, the time until all the tasks are processed twice is 22T. Of which IDL
The E state is 8T and the RUN state is 14T.

The power consumption is 1 / in the case of the IDLE state.
Since it is 10 W, it is as follows.

1/10 W × 8 T + 1 W × 14 T = 14.8 TW

From the above, the average power consumption per unit time is 14.8 TW / 22T = 0.672 W.

On the other hand, in FIG. 4 of the conventional example, the time until all the tasks are processed twice is 18T.
The IDLE state is 4T and the RUN state is 14T.

The power consumption is 1 / in the case of the IDLE state.
Since it is 10 W, it is as follows.

1 / 10W × 4T + 1W × 14T = 14.4TW

The average power consumption per unit time is 14.
4TW / 18T = 0.8W.

As can be seen from a comparison between FIG. 4 and FIG. 7, when the same task processing is performed, the power consumption (original energy consumption) is 14.4 TW in FIG.
4.8 TW, which is slightly larger under this condition. However, the power consumption, which is the energy consumption per unit time, is 0.678 W, which is lower than that in FIG. Therefore, it can be said that there is an advantage that power consumption can be made more controllable and a response to a task with a high priority can be controlled.

FIG. 2 shows a second embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted individually to avoid duplication of description.

The second embodiment shown in FIG. 2 has an LP mode counter stack 42. This stack
As shown in FIG. 2, in the N-level stack, the value to be put on the stack pushes the value of the execution target register 41 onto the stack. The LP mode counter of each stack has a function of counting down independently. In addition, when the count value becomes 0 and further counts down, the counter reaches the maximum value. In this example, the countdown is stopped when the count value reaches the maximum value. That is, each LP mode counter counts down when the value is other than the maximum value. Each LP mode counter has a Z status output that is output when each counter value is zero, and an asynchronous reset signal R. The Z status output of the lower level stack enters an OR gate 44, and
The output of gate 44 is connected to the R signal, thus
When the lower level counter value becomes zero, the upper level counter value also becomes zero.

The Z status output 32a of the first LP mode counter stack at the top of the stack is
, And applied to the AND gate 47 together with the output of the flip-flop 46. The output signal 47 of the AND circuit 47
a enters the power consumption control block circuit 31.

It is assumed that the input of the flip-flop 46 is controlled by the signal line 48 from the processor 11.

In the second embodiment, similarly to the embodiment of FIG. 1, when the processor 11 reaches a start portion of the program of each task where the execution time is to be controlled, the value of the execution target register 41 is changed to the LP mode counter. Stack 4
2 is performed.

For example, when the processor 11 has a PUSH control instruction and a PTIM instruction, the following instructions are implemented in a start portion for which execution time is to be controlled, for example, a task start portion.

PTIM 3 (Push the value of the third execution target register to the third LP mode counter stack.)

Since the LP mode counter stack 42 decrements to a value other than the maximum value, it starts measuring the execution time while decrementing.

On the other hand, when the execution of the task is completed and an instruction to return from the interrupt is executed, immediately before that, an instruction to notify the end of the execution of the task is issued.

For example, when the instruction is an FTASK instruction, the processor 11 sets the flip-flop 46. This setting means that if the value at the top of the LP mode counter stack 42 is not zero, the signal 45a
Is at the HIGH level, the signal 47a is set to the HI level.
GH level, and the power consumption control block circuit 31 controls the clock supply to the processor 11 according to the HIGH level.

When the value of the first LP mode counter becomes 0, the signal 45a becomes zero, the flip-flop 46 is made zero, and control for supplying a clock to the processor 11 is performed.

At the time of the return instruction, the LP mode counter value is POP.

In the second embodiment, unlike the first embodiment, since the execution time is measured not by the execution time timer counter but by the LP mode counter stack 42, the execution time timer counter is not required. . Also,
Since the value of the execution target register 41 is loaded into the LP mode counter stack 42, the subtractor 27 of the first embodiment is not required.

Further, since the LP mode counter stack 42 has a stack configuration, it has a feature that it can completely cope with the nest execution of the same task.

When the counter value at the lower level is zero, that is, when the target execution time of the previously executed task has passed, the task executed later by the nesting process is set to I
The DLE state is not created, and the accuracy with respect to the target time can be improved as compared with the first embodiment.

FIGS. 8A and 8B using the first embodiment of the present invention and FIGS.
This effect will be described with reference to FIG. 9 using the embodiment.

In FIG. 8, although the target time of the task is 5T, the task 2 with a higher priority enters and the target time is 6T, and the execution of the task 1 is waited until the task is completed. Regarding 1, it is necessary to process the target 5T time for 10T time, and the deviation from the target time is large.

On the other hand, in the second embodiment, since the function of clearing the wait state of task 2 is activated after 5T time of task 1, the task is completed at 8T with respect to the target execution time of 5T of task 1, and the target time is set at 8T. Is smaller.

The lower level counter value is zero, ie,
If the target execution time of the task executed earlier has passed, the task executed later in the nesting process will be
There is no need to create a state, and it is possible to improve the accuracy with respect to the target time as compared with the first embodiment.

The execution target register shown in the first and second embodiments is a storage element for storing the execution target, and the present invention can be implemented as long as the storage element is a register, a register file, a memory, or the like. It is.

[0115]

As described above, according to the present invention, the storage device for setting the execution target value for each program in the processor, the counter means for simultaneously measuring the execution time of the program, the execution time of the program, Means for stopping the supply of the clock of the processor until the target execution time is reached when the target execution time is less than the target execution time. Therefore, the target execution time can be controlled for each program. In addition, by rewriting the storage device for setting the execution target value for each program, there is a means for controlling the execution time and power consumption for each program. For programs that run at lower power consumption, and for programs with higher priorities that need to be processed within the time limit, and for programs that expect faster response, faster Control means that can be run can be provided.

Further, according to the present invention, since the counter stack device for measuring whether the execution target value has been reached is provided,
Even when the same program is nested, it is possible to control the execution time and power consumption of each program. In addition, when the lower-level counter value reaches the target execution time, a function for setting the higher-level counter to a value indicating that the target execution time has been reached is provided. Since the clock supply to the processor has been stopped because the target value has not been reached and the previously executed program has reached the execution target value, it is possible to cause the processor to start supplying the clock, Even for the nested program, it is possible to execute the program in a more accurate time with respect to the execution target value.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system configuration of a processor according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a system configuration of a processor according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a normal task operation in which a processor does not perform a low power consumption operation.

FIG. 4 is a diagram for explaining the operation of the conventional system in which the clock supply of the processor is stopped and the system enters the IDLE state in the case of the task waiting time.

FIG. 5 is a diagram for explaining an operation when the operating frequency is set to 通常 of the normal frequency in addition to the conventional method shown in FIG. 4;

FIG. 6 is a diagram illustrating the operation of the processor according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating the operation of the processor according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating the operation of the processor according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating the operation of the processor according to the first embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 Processor 13 Interrupt generator 14 Clock generator 15 AND circuit 21 Execution time timer counter 23 Execution target register 27 Subtractor 28 LP mode counter 31 Power consumption control block circuit

Claims (4)

[Claims] 1. A processor for executing a program, a storage device for setting an execution target value for each program,
A counter for measuring the execution time of the program; and a means for stopping the supply of the clock of the processor until the execution time of the program is less than the execution target value. A low power consumption processor characterized in that execution time and power consumption of each program are controlled by rewriting a storage device for setting an execution target value. 2. A processor for executing a program, a plurality of timer counter devices capable of resetting and counting enable from the processor for measuring the execution time of the program, and a plurality of storage devices for storing a target value of the execution time for each program. An arithmetic unit for comparing an execution target value and an execution time, a weight counter device for storing an operation result,
A control device for controlling clock supply to a processor based on an output signal of the wait counter device,
A low-power processor comprising: 3. A means for resetting the timer counter for measuring the execution time at a desired position of the program according to an instruction of the processor and enabling the counter, and at a desired position of the program according to the instruction of the program. Means for calculating a difference between an execution target time and an execution time by the arithmetic unit, and storing the value in the wait counter device; and, when the value of the wait counter device is 1 or more, the wait counter device is clocked. Means for decrementing in synchronization with
3. The low power consumption processor according to claim 2, further comprising control means for stopping clock supply to the processor in the above case. 4. A processor for executing a program, a plurality of storage devices for storing a target value of the execution time of the program, and a means connected to the target value of the execution time and for pushing the target value of the execution time from the processor. A counter stack device; and means for controlling clock supply to a processor from a status output signal from the counter stack. The counter stack device has a counting function for simultaneously operating counters of each level, and has a lower level. When the counter value reaches the execution target time, the counter has a function of setting the upper level counter to a value indicating that the execution target time has been reached. Output a status signal when the time has expired. Sessa.