JP2005243152A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the element separation voltage resistance of a block switching section without reducing the writing efficiency of an LSB system or an EASB system. <P>SOLUTION: This device is provided with a plurality of memory cell transistors, a memory cell unit 12 including a memory cell transistor and a selection gate transistor serially connected thereto, a memory cell array section 100 in which memory cell units are arranged in a matrix, and a block switching section 102 including a word line 20 and a selection gate line to which the gates of the memory cell transistor and the selection gate transistor arranged in the row direction of the memory cell array are connected in common, and a block selection transistor 22 to which the word line is connected. During data writing, an intermediate voltage V<SB>pass</SB>which boosts the channel of the memory cell transistor but which is not cut off is applied to the word line at two kinds of potentials. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to element isolation of a nonvolatile semiconductor memory device, and more particularly to improvement of element isolation width and element isolation breakdown voltage of a block selection transistor in a block switching unit.

  As a channel voltage control method at the time of writing, a self-boost (SB) writing method (for example, refer to Non-Patent Document 1) and a local self-boost method (LSB) are known (for example, refer to Patent Document 2). Further, an erase area self-boost method (EASB) has been proposed (see, for example, Patent Document 3).

In an electrically erasable / rewritable programmable read-only memory (EEPROM), that is, a NAND flash memory, the memory cell transistor adjacent to the selected memory cell transistor for writing data “1” is cut off, Data “1” is written in the selected memory cell transistor by self-boosting the channel and diffusion layer region by a high potential write voltage V _pgm applied to the word line of the selected memory cell transistor (electrons are stored in the charge storage layer). The “LSB (local self-boost) writing method” is a method that does not inject into the above.

Further, the memory cell transistor adjacent to the source side of the selected memory cell transistor for writing data “1” is cut off, and a high potential write voltage V _{pgm is} applied to the word line of the selected memory cell transistor, and By applying a slightly higher potential intermediate voltage V _pass to the word lines of the memory cell transistors other than the selected memory cell transistor, the channel and the diffusion layer region are self-boosted, and data “1” is written to the selected memory cell transistor. A method (which does not inject electrons into the charge storage layer) is an “erased area (erased area) self-boost (EASB) writing method”.

  In selective self-boosting, an adjacent voltage is applied to a word line of a memory cell transistor adjacent to the selected memory cell transistor so that the memory cell transistor is normally turned on, so that the adjacent memory cell transistor is normally off. There has been proposed a nonvolatile semiconductor memory device configured to transmit the bit line potential even in the state and to reduce the absolute value of the erase voltage applied to the word line by using self-boosting even at the time of erasing. (Patent Document 1).

In the nonvolatile semiconductor memory device according to Patent Document 1, 20 V is applied to the memory cell transistor selected at the time of write boost, 2.0 V to 8.7 V is applied to the memory cell transistor adjacent to the bit line side, and further to the next. 11V is applied to adjacent memory cell transistors. 0 V is applied to the memory cell transistor adjacent to the source of the selected memory cell transistor. At the time of boost, the cut-off voltage V _cutoff and two kinds of intermediate voltages V _pass are applied.

In the nonvolatile semiconductor device according to Patent Document 1, in the NAND type EEPROM adopting the selective self-boosting method, the reliability of the write inhibition in the non-selected NAND type memory cell column is improved and the selected NAND type memory cell In the column, it is possible to randomly write to a plurality of memory cell transistors, and further, it is possible to erase data of a NAND-type EEPROM using an erase voltage lower than that in the past, miniaturization of elements, improvement of reliability, and yield. Can be improved.
JP-A-10-302488 JP-A-8-279297 Japanese Patent Laid-Open No. 10-283788 KD Suh et al., “A 3.3V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme” by the Incremental Step Pulse Programming Scheme, American Institute of Electrical and Electronics Engineers (IEEE), JOURNAL OF SOLID-STATE CIRCUITS, Vol. 30, November 1995, p. 1149-1156

  The configuration of the block switching unit 102 in the conventional nonvolatile semiconductor memory device includes a plurality of block selection circuit units 14 as shown in FIG. 10, for example, and each block selection circuit unit 14 is arranged in two columns in the column direction. A plurality of block selection transistors 22 are provided. Further, each block selection circuit section 14 includes an activation region 16 of the block selection transistor 22, a gate electrode 18 of the block selection transistor 22, an element isolation region 28, a word line contact 24, a word line 20, and a peripheral circuit. 30 and electrode wiring 32.

In the LSB writing method, a high potential write voltage V _pgm for writing is applied to the word line WLk of the memory cell transistor to be written, and the potential for cutting off the memory cell transistor to the adjacent word lines WLk−1 and WLk + 1. That is, a cutoff voltage V _cutoff is given. Further, the word line WLk of the memory cell transistor to be written and the word lines other than the adjacent word lines WLk−1 and WLk + 1 have a _cutoff voltage V _cutoff and a write voltage for the purpose of boosting the diffusion layer region of the memory cell transistor. An intermediate voltage V _pass which is a potential between V _pgm is applied.

Usually, the word line 20 drawn from the memory cell array unit is connected to the block selection transistor 22 in the block selection circuit unit 14 of the block switching unit (core unit) 102. In general, the cutoff voltage V _cutoff gives 0 V. Therefore, when the areas of the block switching unit 102 and the block selection circuit unit 14 are reduced, the activation region 16 to which the _cutoff voltage V _cutoff is applied, Isolation tolerance (reverse breakdown voltage) in the element isolation region 28 where the activation region 16 to which the voltage V _pass is applied faces and the gate wiring of the gate electrode 18 of the block selection transistor 22 of the block switching unit 102 is disposed above. ) Becomes severe.

In FIG. 10, for example, the write voltage V _pgm is about 25 V, the intermediate voltage V _pass is about 10 V, and the cut-off voltage V _cutoff is about 0 V. Therefore, in particular in the region indicated by arrows A to D in FIG. Isolation resistance (inversion withstand voltage) in the element isolation region 28 where the gate wiring of the electrode 18 is disposed above becomes strict.

In this LSB writing method, the activation region 16 to which the cut-off voltage V _cutoff is applied and the activation region 16 to which the intermediate voltage V _pass is applied face each other. Furthermore, since the element isolation tolerance (inversion breakdown voltage) on which the gate of the transistor of the block switching unit is mounted becomes severe (FIG. 10), it is extremely difficult to reduce the element isolation width of the block switching unit.

The present invention solves the problem of the block switching unit of the nonvolatile semiconductor memory device when the LSB method and the EASB method have become prominent along with miniaturization. By using two intermediate voltages V _pass of high potential and low potential for V _pass and further optimizing the arrangement of the block selection transistors in the block switching unit, the write efficiency is not reduced from the LSB method or EASB method, An object of the present invention is to provide a nonvolatile semiconductor memory device having a writing method for improving the element isolation withstand voltage of a block switching unit.

In order to achieve the above object, the present invention is characterized in that (a) a plurality of memory cell transistors including a charge storage layer and a control gate stacked via an insulating film, (b) a memory cell transistor, and a memory cell A memory cell unit including a select gate transistor connected in series to the transistor; (c) a memory cell array in which the memory cell units are arranged in a matrix; and (d) a memory cell transistor and a select gate transistor arranged in the row direction of the memory cell array. (E) a block switching unit including a block selection transistor to which a word line is connected, and (e) a block selection transistor to which the word line is connected, and (f) boosting the channel of the memory cell transistor when writing data. word line an intermediate voltage V _pass in two potential to And summarized in that a non-volatile semiconductor memory device that provides for.

While maintaining the write efficiency of LSB and EASB by using two intermediate voltages V _pass of high potential and low potential as the intermediate voltage V _pass and further optimizing the arrangement and writing method of the transistors in the block switching unit, The element isolation withstand voltage of the block switching unit can be improved and the element isolation width can be reduced.

In a NAND nonvolatile semiconductor memory device in which a charge storage layer and a control gate are stacked, an intermediate voltage V _pass is applied as two potentials as a potential for boosting the diffusion layer at the time of writing. Further, no cut-off _occurs at any intermediate voltage V _pass during the boost operation.

Alternatively, it is not cut off during the initial write potential setting period under one (lower) intermediate voltage V _pass , but is cut off during the boost operation. Under the other (higher) intermediate voltage V _pass , there is no cut-off even during boost operation.

 Alternatively, the block selection transistor 22 to which the word line WLk is connected corresponds to the K + 1 and K−1th word lines WLk + 1 and WLk−1 next to the block selection transistor 22 corresponding to the Kth word line WLk. The block selection transistor 22 is not arranged.

Alternatively, when the k-th word line WLk is a selection target, the _cutoff voltage V _cutoff is applied to the (k + 1) -th word line WLk + 1 and the (k-1) -th word line WLk-1, and the k + 2-th word line WLk + 2 and k- -A second word line WLk-2 by applying an intermediate voltage V _passh the high level to apply the intermediate voltage V _PassL the low level to one of the other word lines.

Alternatively, when the Kth word line WLk is a selection target, the _cutoff voltage V _cutoff is applied to the K + 1th word line WLk + 1 near the source line SL, and k−1 near the k + 2nd word line WLk + 2 and the bit line BL. th intermediate voltage V _passh high level is applied to the word line WLk-1, applying an intermediate voltage V _PassL the low level to one of the other word lines.

In the embodiment of the present invention, a low-level intermediate voltage V _passL is connected next to the activation region 16 of the block selection transistor 22 to which the _cutoff voltage V _cutoff is connected in the block selection circuit unit 14. The isolation breakdown voltage is improved by arranging the activation region 16.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
(Overall block configuration)
As shown in FIG. 1, the nonvolatile semiconductor memory device according to the first embodiment of the present invention includes a memory cell array unit 100 and a block switching unit 102. The memory cell array unit 100 is divided into a plurality of memory cell blocks 10-1, 10-2, 10-3,..., 10-j, and each of the memory cell blocks 10-1, 10-2, 10-3, .., 10-j have memory cell units 12 arranged in parallel in the row direction. Between the memory cell blocks 10-1, 10-2, 10-3,..., 10-j of the memory cell array unit 100 and the block switching unit 102, word lines 20-1, 20-2, 20-3,. , 20-j, and relatively high voltage pulses such as the write voltage V _pgm generated in the block switching unit 102 are applied to the word lines 20-1, 20-2, 20-3,. And transferred to the gate of the memory cell transistor in the memory cell unit 12.

  In the block switching unit 102, corresponding to the memory cell blocks 10-1, 10-2, 10-3,..., 10-j, block selection circuit units 14-1, 14-2, 14-3, .., 14-j are arranged, and in each block selection circuit unit 14-1, 14-2, 14-3,..., 14-j, as shown in FIG. Block selection transistors 22-1, 22-2, 22-3, ..., 22-k; 23-1, 23-2, 23-3, ..., 23-k activation regions 16-1, 16-2, 16-3,..., 16-k; 17-1, 17-2, 17-3,..., 17-k, and a plurality of block selection transistors 22-1, 22-2, 22-3,. A gate electrode 18a connected in common is arranged on the k activation regions 16-1, 16-2, 16-3,..., 16-k. A common connection is made on the activation regions 17-1, 17-2, 17-3,..., 17-k of the plurality of block selection transistors 23-1, 23-2, 23-3,. A gate electrode 18b is disposed.

  In FIG. 1, a plurality of block selection transistors 22-1, 22-2, 22-3, ..., 22-k; 23-1, 23-2, 23-3, ..., 23-k are activated. , 16-k; 17-1, 17-2, 17-3,..., 17-k, word line contacts 24 and word lines 20- formed in the regions 16-1, 16-2, 16-3,. 1, 20-2, 20-3,..., 20-j are not shown, but this state is configured as shown in FIG. The configuration of one memory cell block 10-i and the corresponding block selection circuit unit 14-i is, for example, as shown in FIG. 2, a plurality of block selection transistors 22-1 and 22-2 arranged in two columns. , 22-3, ..., 22-k; 23-1, 23-2, 23-3, ..., 23-k, and a plurality of block selection transistors 22-1, 22-2, 22-3, ..., 22 -K; 23-1, 23-2, 23-3, ..., 23-k activation regions 16-1, 16-2, 16-3, ..., 16-k; 17-1, 17-2, 17-3,..., 17-k and the activation regions 16-1, 16-2, 16-3,..., 16-k; 17-1, 17-2, 17-3,. , And a plurality of block selection transistors 22-1, 22-2, 22-3,..., 22-k; 23-1, 23-2, 23-3 arranged in the column direction. , , 23-k are commonly connected to gate electrodes 18a, 18b, and a word line 20-i wired in common to the memory cell unit 12 constituting the memory cell block 10-i. The In FIG. 2, a plurality of block selection transistors 22-1, 22-2, 22-3,..., 22-k; 23-1, 23-2, 23-3,. , 16-k; 17-1, 17-2, 17-3,..., 17-k electrode wiring 32 and the like are described. Is omitted.

  In FIG. 1 or FIG. 2, the circuit configuration of the memory cell unit 12 is, for example, as shown in FIG. 3, a NAND string of memory cell transistors M0 to M7 having a stack gate structure connected in series, and a bit line BL, source line SL, bit line side select gate transistor SGD connecting NAND strings of memory cell transistors M0 to M7 to bit line BL, and NAND string of memory cell transistors M0 to M7 to source line SL Are connected to the source line side select gate transistor SGS. The memory cell transistors M0 to M7 are provided with word lines WL0 to WL7, the bit line side selection gate transistor SGD is a bit line side selection gate line SGU, and the source line side selection gate transistor SGS is a source line side selection gate. Line SGL is arranged. The number of memory cell transistors connected in series is not limited to eight, and may be 16, 32, 64 or more.

  Further, in FIG. 1, the activation regions of the plurality of block selection transistors 22-1, 22-2, 22-3, ..., 22-k; 23-1, 23-2, 23-3, ..., 23-k 16-1, 16-2, 16-3, ..., 16-k; 17-1, 17-2, 17-3, ..., 17-k are isolated from each other by the element isolation region 28. It is omitted from the drawing. In FIG. 2, for example, as shown in FIG. 4, a typical element cross-sectional structure along the II line shows a semiconductor substrate or well region 1, an element isolation region 28, and activation regions 17-2, 17-. 3 and a gate electrode 18b. In the semiconductor substrate or well region 1, the region immediately below the gate electrode 18b corresponds to the channel region 19 through the gate insulating film 2 of the block selection transistors 23-2 and 23-3.

Channel inversion in the element isolation region 28 will be described with reference to FIG. When a high voltage such as the write voltage V _pgm is applied to the word line, the common gate electrode of the block select transistors 23-1, 23-2, 23-3,..., 23-k arranged in the row direction A voltage higher than the write voltage V _pgm by about 4V, that is, about 24V + 4V = 28V is applied to 18b. When such a high voltage is applied to the gate electrode 18b, the interface between the semiconductor substrate or the well region 1 and a relatively thick oxide film such as shallow trench isolation (STI) constituting the element isolation region 28. In some cases, an inversion layer is formed to form a carrier conduction channel. Therefore, in the nonvolatile semiconductor memory device according to the embodiment of the present invention, the block selection transistors 22-1 and 22- to which the word lines 20-1, 20-2, 20-3,. 2, 22-3,..., 22-k; 23-1, 23-2, 23-3,.

  In the NAND flash EEPROM, the word lines 20-1, 20-2, 20-3,..., 20-j drawn from the memory cell array unit 100 are block selections in the block selection circuit unit 14 of the block switching unit 102. Connected to transistor 22. Usually, in the arrangement in the block selection circuit units 14-1, 14-2, 14-3,..., 14-j of the block switching unit 102, the block selection transistor 22 to which the selected word line WLk is connected, The block selection transistors 22 connected to the adjacent word lines WLk + 1 and WLk−1 are arranged so as not to be adjacent to each other with the element isolation region 28 interposed therebetween.

When the local self-boost (LSB) writing method is used, a high-potential write voltage V _pgm for writing is applied to the word line WLk of the memory cell transistor to be written, and the memory is applied to the adjacent word lines WLk + 1 and WLk−1. A cut-off voltage V _cutoff (for example, 0 V) for cutting off the cell transistor is applied. Further, the word line WLk of the memory cell transistor to be written and the word lines other than the adjacent word lines WLk + 1 and WLk−1 have a cutoff voltage for the purpose of boosting the diffusion layer region of the memory cell transistor at the time of writing “1”. An intermediate voltage V _pass having an intermediate potential between V _cutoff and the write voltage V _pgm is applied.

(Configuration of block switching unit)
In the nonvolatile semiconductor memory device according to the first embodiment of the present invention, the NAND flash EEPROM having 16 NAND cells is taken as an example, and the block selection transistors 22-1, 22-2, and 22 in the block selection circuit unit 14-i. -3,..., 22-8; 23-1, 23-2, 23-3,..., 23-8 are allocated to the word lines WL1 to WL16 (see FIG. 6) as shown in FIG.

  In the nonvolatile semiconductor memory device according to the first embodiment of the present invention, taking the NAND flash EEPROM of 16 NAND cells as an example, the potential applied to each word line WL1 to WL16 at the time of writing “1” at the time of LSB writing The relationship is shown in FIG.

The intermediate voltage V _pass includes a high level intermediate voltage V _passH for the purpose of boosting the diffusion layer region of a normal memory cell transistor when “1” is _written , and a lower potential for a low level intermediate voltage. _Give as V _passL .

The low-level intermediate voltage V _passL is lower than the high-level intermediate voltage V _passH , and the low-level intermediate voltage V _passL is applied to the boosted channel when writing “1”. This is a potential at which the memory cell transistor is not cut off.

By applying the potential in this way, for example, when writing to the word line WL5, the transistors arranged in the block switching unit have a potential relationship as shown in FIG. Since a low-level intermediate voltage V _passL is input to a transistor to which both the cut-off voltage V _cutoff is input and the adjacent gate having a common gate, the element isolation resistance between the transistors should be higher than that of the prior art. Can do. For example, in the regions indicated by arrows E to H and I to L in FIG. 7, the isolation breakdown voltage (reverse breakdown voltage) in the element isolation region 28 in which the gate wirings of the gate electrodes 18 a and 18 b are disposed above can be improved. it can.

FIG. 7 shows the potential relationship at the time of writing to the word line WL5, but the low-level intermediate voltage V _passL can be _similarly applied to word lines other than the word line WL5.

(Second Embodiment)
In the nonvolatile semiconductor memory device according to the second embodiment of the present invention, the block selection transistors 22-1, 22-2, and 22 in the block selection circuit unit 14-i are exemplified using a NAND flash EEPROM having 16 NAND cells. -3,..., 22-8; 23-1, 23-2, 23-3,..., 23-8 are assigned to the word lines WL1 to WL16 (see FIG. 8) as shown in FIG.

  In the nonvolatile semiconductor memory device according to the second embodiment of the present invention, taking NAND flash EEPROM of 16 NAND cells as an example, the potential applied to each word line WL1 to WL16 at the time of “1” writing at the time of EASB writing The relationship is shown in FIG.

In the nonvolatile semiconductor memory device according to the second embodiment of the present invention, a block in the block selection circuit unit 14-i is used when writing the word line WL5 during EASB writing, taking a NAND flash EEPROM of 16 NAND cells as an example. Each of the word lines WL1 to WL16 connected to the selection transistors 22-1, 22-2, 22-3,..., 22-8; 23-1, 23-2, 23-3,. FIG. 9 shows the relationship of potentials applied to the reference.

  In the NAND flash EEPROM of 16 NAND cells, the block selection transistors 22-1, 22-2, 22-3,..., 22-8 in the block selection circuit section 14-i of the block switching section 102; .., 23-3,..., 23-8 are assigned to the respective word lines WL1 to WL16 in FIG. 8 as shown in FIG. A potential is applied to each of the word lines WL1 to WL16 as shown in FIG.

The potential of the intermediate voltage V _pass is a high level intermediate voltage V _passH for the purpose of boosting the diffusion layer region of a normal memory cell transistor when “1” is _written , and a lower potential is set to a low level. It is given as an intermediate voltage V _passL .

The potential of the intermediate voltage V _PassL the low level, lower than the intermediate voltage V _passh high level, yet, in the boosted channel potential, the memory cell transistors gave low level intermediate voltage V _PassL is not cut-off potential It is.

By applying the potential in this way, for example, when writing to the word line WL5, the transistors arranged in the block switching unit have a potential relationship as shown in FIG. Since a low-level intermediate voltage V _passL is input to a transistor to which both the cut-off voltage V _cutoff is input and the adjacent gate having a common gate, the element isolation resistance between the transistors should be higher than that of the prior art. Can do.

FIG. 9 shows the potential relationship at the time of writing to the word line WL5, but the low-level intermediate voltage V _passL can be _similarly applied to word lines other than the word line WL5.

(Third embodiment)
In the nonvolatile semiconductor memory device according to the third embodiment of the present invention, the block selection transistors 22-1, 22-2, and 22 in the block selection circuit unit 14-i are exemplified by using a NAND flash EEPROM having 16 NAND cells. -3,..., 22-8; 23-1, 23-2, 23-3,..., 23-8 are allocated to the word lines WL1 to WL16 (see FIG. 6) as shown in FIG.

  In the nonvolatile semiconductor memory device according to the third embodiment of the present invention, the potential applied to each word line WL1 to WL16 at the time of “1” writing at the time of LSB writing, using a NAND flash EEPROM of 16 NAND cells as an example The relationship is shown in FIG.

  In the nonvolatile semiconductor memory device according to the third embodiment of the present invention, taking a NAND flash EEPROM of 16 NAND cells as an example, when writing the word line WL5 during LSB writing, the block in the block selection circuit unit 14-i Each of the word lines WL1 to WL16 connected to the selection transistors 22-1, 22-2, 22-3,..., 22-8; 23-1, 23-2, 23-3,. FIG. 7 shows the relationship of potentials applied to the reference.

In the nonvolatile semiconductor memory device according to the first embodiment of the present invention, in order to perform conventional LSB writing, the potential of the low-level intermediate voltage V _passL is high for each of the word lines WL1 to WL16. Even in a channel that is lower than the intermediate voltage V _passH at the level and boosted at the time of writing “1”, the memory cell transistor to which the intermediate voltage V _passL at the low level is applied has a potential that is not cut off.

A writing method in which writing is performed with this greatly reduced is also possible. By greatly lowering the low level intermediate voltage V _passL , it is possible to narrow the element isolation width L _STI in the region where the element isolation tolerance is most severe in the block selection circuit unit 14-i of the block switching unit 102 shown in FIG. 10. It becomes.

Usually, for example, the write voltage V _pgm = 20 V, the high level intermediate voltage V _passH = 10 V, the power supply voltage Vcc = 3 V, and the cut-off voltage V _cutoff = 0V. In addition, the low-level intermediate voltage V _passL can be reduced to about _1-2V . In the LSB method, since writing is performed from the memory cell transistor on the source side, writing is performed from the word line WL16 to the word lines WL15, WL14,.

  All memory cell transistors arranged on the drain side of the memory cell transistor to be written are depletion mode memory cell transistors. In the LSB system, an initial potential transferred from the bit line BL is required to sufficiently boost the channel on which “1” is written.

All of the memory cell transistors arranged on the drain side of the memory cell transistor to be written are depletion mode memory cell transistors, and even if the low level intermediate voltage V _passL is _lowered to about 1 to 2 V, the memory cell transistor to be written to The potential is sufficiently transferred to the memory cell transistor.

Further, when the channel is boosted at the time of writing “1”, when a low potential of about 1 to 2 V is _applied as the low level intermediate voltage V _passL , the memory cell transistor that provides the low level intermediate voltage V _passL is Cut off. Since the word line WL adjacent to the word line WL to which the _cutoff voltage V _cutoff is applied is always _supplied with the high-level intermediate voltage V _passH , the memory cell transistor to which the _cutoff voltage V _cutoff is applied is boosted by the adjacent channel. Cut off.

Therefore, channel boost similar to that of the conventional LSB method can be obtained for the memory cell transistor to be written. By greatly lowering the low level intermediate voltage V _passL , the activation regions of the _cutoff voltage V _cutoff and the intermediate voltage V _pass face each other as shown in FIG. 10, and further, in the block selection circuit unit 14 of the block switching unit 102. The element isolation tolerance (inversion withstand voltage) of the element isolation region 28 in which the gate wiring of the gate electrode 18 of the block selection transistor 22 is arranged can be greatly improved, and the element isolation width L _STI can be reduced.

(Fourth embodiment)
In the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention, the block selection transistors 22-1, 22-2, and 22 in the block selection circuit section 14-i are exemplified by using a NAND flash EEPROM having 16 NAND cells. -3,..., 22-8; 23-1, 23-2, 23-3,..., 23-8 are assigned to the word lines WL1 to WL16 (see FIG. 8) as shown in FIG.

  In the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention, taking a NAND flash EEPROM of 16 NAND cells as an example, the potential applied to each word line WL1 to WL16 at the time of writing “1” at the time of EASB writing The relationship is shown in FIG.

  In the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention, taking a NAND flash EEPROM of 16 NAND cells as an example, when writing word line WL5 during EASB writing, the block in block selection circuit unit 14-i Each of the word lines WL1 to WL16 connected to the selection transistors 22-1, 22-2, 22-3,..., 22-8; 23-1, 23-2, 23-3,. FIG. 9 shows the relationship of potentials applied to the reference.

In the nonvolatile semiconductor memory device according to the second embodiment of the present invention, in order to perform the conventional EASB write method, the potential of the low-level intermediate voltage V _passL for each of the word lines WL1 to _WL16 is: Even in a channel that is lower than the high-level intermediate voltage V _passH and boosted at the time of writing “1”, the memory cell transistor to which the low-level intermediate voltage V _passL is applied gives a potential that is not cut off.

A writing method in which writing is performed with this greatly reduced is also possible. By greatly lowering the low-level intermediate voltage V _passL , the gate wiring of the gate electrode 18 of the block selection transistor 22 arranged in the block selection circuit unit 14 of the block switching unit 102 shown in FIG. The element isolation tolerance (inversion breakdown voltage) of the element isolation region 28 can be greatly improved, and the element isolation width L _STI can be reduced. That is, in the block switching unit 102, it is possible to narrow the element isolation width L _STI in the region where the element isolation tolerance is most severe.

Normally, V _pgm = 20V, V _passH = 10V, V _cc = 3V, V _cutoff = 0V, but the low level intermediate voltage V _passL is _reduced to about 1 to 2V. In the EASB method, since writing is performed from the memory cell transistor on the source side, writing is performed from WL16 to 15, 14,.

All the memory cell transistors arranged on the drain side of the memory cell transistor to be written are depletion mode transistors. In the EASB system, in order to sufficiently boost the channel for writing “1”, an initial potential transferred from the bit line BL is required. However, the memory cell arranged on the drain side of the memory cell transistor to be written All the transistors are depletion mode transistors, and the potential is sufficiently transferred to the memory cell to be written even if the low level intermediate voltage V _passL is _lowered to about 1 to 2V.

Further, when the boosted channel when "1" is written, when the low-level intermediate voltage V _PassL gave 1~2V as low as about potential memory cell transistor for applying an intermediate voltage V _PassL a low level Cut off. Cutoff word lines WL of neighboring voltage V _cutoff word line WL gave the always, since the intermediate voltage V _passh the high level is given, the memory cell transistor is boosted adjacent channels gave cutoff voltage V _cutoff Is cut off.

Therefore, channel boost similar to that of the conventional EASB system can be obtained for the memory cell transistor to be written. By greatly lowering the low level intermediate voltage V _passL , the cut-off voltage V _cutoff and the activation region 16 of the intermediate voltage V _pass face each other as shown in FIG. The element isolation tolerance (inversion breakdown voltage) on which the gate wiring of the gate electrode 18 of the block selection transistor 22 is mounted can be greatly improved.

 As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative examples, embodiments, and operational techniques will be apparent to those skilled in the art. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  In addition, various modifications can be made without departing from the scope of the present invention. The above embodiments can be implemented in combination. As described above, the present invention naturally includes various embodiments not described herein.

  According to the present invention, not only a memory card and an IC card but also a wide range of industrial applicability such as an in-vehicle system, a hard disk driver, a mobile phone, and a modem device for a high-speed network exist.

1 is an overall block configuration diagram of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 3 is a configuration diagram of one memory cell block and a corresponding block selection circuit unit in the nonvolatile semiconductor memory device according to the first embodiment of the present invention. 1 is a circuit configuration diagram of a memory cell unit used in a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 3 is a schematic element cross-sectional structure diagram taken along line II in FIG. 2. In the nonvolatile semiconductor memory devices according to the first to fourth embodiments of the present invention, the block selection transistors 22-1 and 22- in the block selection circuit unit 14-i are exemplified by using a NAND flash EEPROM having 16 NAND cells. 2, 22-3,..., 22-8; 23-1, 23-2, 23-3,..., 23-8 are assigned to the respective word lines WL1 to WL16 (see FIG. 6 or FIG. 8). . In the nonvolatile semiconductor memory device according to the first and third embodiments of the present invention, the potential applied to each of the word lines WL1 to WL16 at the time of LSB writing is shown by taking a NAND flash EEPROM of 16 NAND cells as an example. Figure. In the nonvolatile semiconductor memory device according to the first and third embodiments of the present invention, the block selection circuit unit 14-i is used when writing the word line WL5 at the time of LSB writing, taking the NAND flash EEPROM of 16 NAND cells as an example. , 22-8; 23-1, 23-2, 23-3,..., 23-8, the word lines WL1 to WL16 connected to the block selection transistors 22-1, 22-2, 22-3,. The figure which shows the electric potential relationship given with respect to (refer FIG. 6). In the nonvolatile semiconductor memory device according to the second and fourth embodiments of the present invention, “1” write is performed on each of the word lines WL1 to WL16 at the time of EASB write, using a NAND flash EEPROM of 16 NAND cells as an example. The figure which shows the electric potential relationship given sometimes. In the nonvolatile semiconductor memory device according to the second and fourth embodiments of the present invention, the block selection circuit unit 14-i is used when writing the word line WL5 during EASB writing, using a NAND flash EEPROM of 16 NAND cells as an example. , 22-8; 23-1, 23-2, 23-3,..., 23-8, the word lines WL1 to WL16 connected to the block selection transistors 22-1, 22-2, 22-3,. The figure which shows the electric potential relationship given with respect to (refer FIG. 8). 6A and 6B illustrate an example of a configuration of a block switching unit and a potential relationship in a conventional nonvolatile semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate or well area | region 2 ... Gate insulating film 10, 10-1 to 10-i, 10-j ... Memory cell block 12 ... Memory cell unit 14, 14-1 to 14-i, 14-j ... Block selection Circuit portions 16, 16-1 to 16-k, 17, 17-1 to 17-k ... activation regions 18, 18a, 18b ... gate electrodes 19 ... channel regions 20, 20-1 to 20-i, 20-j ... word lines 22, 22-1 to 22-k, 23, 23-1 to 23-k ... block selection transistor 24 ... word line contact 28 ... element isolation region 30 ... peripheral circuit 32 ... electrode wiring 100 ... memory cell array section 102 ... block switching unit V _pgm ... write voltage V _pass ... intermediate voltage V _PassL ... intermediate voltage V _passh ... intermediate voltage V _cutoff ... cutoff voltage V _cc ... supply voltage V _bl ... bit line voltage of a high level of low level L0~WL16 ... word line BL ... bit line SL ... source line SGD ... bit line side select gate transistor SGS ... source line side select gate transistor SGU ... bit line side select gate line SGL ... source line side select gate line

Claims (5)

A plurality of memory cell transistors each including a charge storage layer and a control gate stacked via an insulating film;
A memory cell unit comprising: the memory cell transistor; and a select gate transistor connected in series to the memory cell transistor;
A memory cell array in which the memory cell units are arranged in a matrix;
A word line and a selection gate line that commonly connect the gates of the memory cell transistors and the selection gate transistors arranged in the row direction of the memory cell array, respectively.
A block switching unit including a block selection transistor to which the word line is connected, and when writing data, an intermediate voltage V _pass for boosting the channel of the memory cell transistor is applied to the word line with two kinds of potentials A non-volatile semiconductor memory device. In the block switching unit, when writing to the selected word line, a potential for cutting off the channel is applied to the word line adjacent to the selected word line, and adjacent to the selected word line A word line further adjacent to the word line is given a higher intermediate potential of the two kinds of intermediate potentials V _pass for boosting the channel, and a lower intermediate potential is applied to one of the word lines other than the word line. Both of the two kinds of potentials are set to a value that does not cut off the channel even when the channel is boosted during data writing, and a block is selected that is connected to a word line that provides a potential to cut off the channel. The transistor selects a block connected to a word line that gives the lower intermediate potential of the two types of intermediate potential V _pass 2. The non-volatile semiconductor memory device according to claim 1, wherein the transistor and the gate are arranged in common and adjacent to each other. In the block switching unit, when writing to the selected word line, the word line adjacent to the selected word line near the source is given a potential for cutting off the channel, and the selected near the source is selected. The word line adjacent to the word line adjacent to the selected word line and the word line adjacent to the selected word line near the bit line are given the higher intermediate potential of the two types of intermediate potentials V _pass. A lower intermediate potential is applied to one of the word lines other than the word line, and both of the two kinds of potentials are set to values that do not cut off the channel even when the channel is boosted during data writing. The block selection transistor connected to the word line for applying the potential for cutting off the channel has the two kinds of intermediate potentials V _pass . 2. The non-volatile semiconductor memory device according to claim 1, wherein a block selection transistor connected to a word line to which the lower intermediate potential is applied and a gate are arranged in common and adjacent to each other. In the block switching unit, when writing to the selected word line, a potential for cutting off the channel is applied to the word line adjacent to the selected word line, and adjacent to the selected word line A potential that boosts the channel is applied to a word line that is further adjacent to the word line, and a gate potential that cuts off the channel when the channel is boosted is applied to one of the word lines other than the word line. The block selection transistor connected to the word line that _supplies the potential for cutting off the channel is connected to the word line that applies the lower one of the two types of intermediate potentials V _pass that cuts off the channel when boosted. The block selection transistor and the gate are arranged in common and adjacent to each other. The nonvolatile semiconductor memory device according to. In the block switching unit, when writing to the selected word line, the word line adjacent to the selected word line near the source is given a potential for cutting off the channel, and the selected near the source is selected. The word line adjacent to the word line adjacent to the selected word line and the word line adjacent to the selected word line near the bit line are given a potential for boosting the channel, and any one of the word lines other than the word line is applied. Further, when the channel is boosted, a gate potential for cutting off the channel is applied, and a block selection transistor connected to a word line for supplying a potential for cutting off the channel causes the channel to be cut off when boosted. Bro connected to the word line for providing an intermediate potential of the lower of the type of the intermediate potential V _pass Click selection transistor and a nonvolatile semiconductor memory device according to claim 1 in which the gate is characterized by being arranged commonly and such that adjacent.

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