JP2005235980A - Wiring substrate and its manufacturing method, and semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interposer in which two types of terminals for W/B bonding and FC bonding are formed at a narrow pitch with sufficient accuracy and flatly on one surface. <P>SOLUTION: A method of manufacturing a wiring substrate includes a whole surface Ni plating step of performing plating on a Cu plate 110 made into a supporting substrate, a step of electrolytically plating an Ni layer 141, an Au layer 142 and an Ni layer 143 to the first terminal by arranging a first resist 130 on the Ni plating layer 120 to a plating-proof mask, a first wiring forming step of forming first wiring 150 by arranging a second resist 135 to the plating-proof mask and precipitating Cu after the resist is removed, a wiring layer forming step of forming the multilayer wiring of desired number N of the wiring layers after the second resist is removed, a second terminal plating step of forming the Ni layer, the Au layer on a region for forming the terminal section of the N-th wiring layer with the Cu plate as a power supply layer, and an Ni etching step of removing the Cu plate by etching and further etching the exposed Ni layer to the state that the Au layer formed in the first terminal is exposed. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

  The present invention relates to a wiring board, and in particular, for connection to a semiconductor chip formed by an additive method, two types of terminals, one end of which is plated with Au and one terminal portion made of pure Cu. The wiring board is formed so that the surface of each of the terminal portions is on a single plane.

In recent years, high integration and high performance of semiconductor packages have been advanced, and small size and higher performance are required.
The semiconductor chips mounted on these semiconductor packages are also increasingly thin and small in size and have a narrow pitch and a large number of pins (multiple terminals).
Recently, in order to cope with the increase in the number of terminals of a semiconductor chip and the routing of wiring, a wiring board based on a resin as an interposer has come to be used for a semiconductor package. Wiring substrates based on resin for packaging have also been made thinner and narrow pitch connection terminals to meet the demand for smaller size and higher performance.
On the other hand, in order to make a semiconductor package higher performance, a semiconductor package called a SIP (System in Package) on which a plurality of chips are mounted or a semiconductor package having a stacked structure (stacked structure) is used. There are also many things.
A wiring board having a resin as a base material as an interposer is also used for a semiconductor package having such a structure.

In these semiconductor packages, wire bonding bonding (hereinafter referred to as W / B bonding) as shown in FIG. 6A is used for bonding a semiconductor chip having a narrow pitch connection terminal and a substrate for a semiconductor package. Alternatively, flip chip bonding (hereinafter referred to as FC bonding) as shown in FIG. 6B is used.
In the case of flip chip bonding, the surface of a connection pad on the substrate side for a semiconductor package as an interposer is exposed to a thin Au layer of about 0.1 to 0.3 μm, or the underlying Cu layer is printed on the surface. A solder layer is formed by a method or the like.
In the case of W / B bonding, the surface of the connection pad on the substrate side is an Au layer of about 0.5 to 1 μm.
In W / B bonding, the reason for increasing the Au plating thickness on the bonding pad surface on the wiring board side is that, when W / B bonding is performed, Au wire is used for the wire, and the pad surface to be bonded on the substrate side is Au plated. / B is usually performed by applying pressure and ultrasonic waves (vibration + heat) to destroy the oxide film on the surface and bonding Au-Au, and the thickness of the Au plating layer on the pad surface on the wire receiving side If the thickness is too small, the underlying Ni layer is exposed, so that a thick Au layer is required in order not to expose the underlying Ni plating of the Au plating on the pad surface during the W / B process.
In FC bonding, it is usual to thin the Au plating on the surface of the bonding pad portion on the substrate side, or to make the bonding on the substrate side pure Cu.
In FC bonding, the bonding pad portion on the substrate side is Au-plated or pure Cu, Au bump on the chip side-soldering connection on the substrate side, solder balls on the chip side, and solder pre-coating on the substrate side The joining method is general, and all use solder at the joint.
In the case of joining using Sn-Pb solder in order not to impair the soldering reliability, without using Au plating for the pads to be joined on the substrate side, the Cu is solid or the Cu is covered with a flux. There are many things to do.
The reason for thinning the Au plating of the pads to be bonded on the substrate side in the FC bonding is that when the substrate side receiving pad portion is plated with Au, Au is easily eroded by tin-based solder, and the solder and Au plating. The mechanical strength is reduced at the part of the intermetallic compound produced between the two, and peeling easily occurs. However, by reducing the thickness of the Au plating, the production rate of the aforementioned intermetallic compound is reduced, and the machine This is because the influence on the mechanical strength can be substantially eliminated.

However, in the case of SIP, for example, as shown in FIG. 6C, in order to mount a plurality of chips, terminal bonding methods of both W / B bonding and FC bonding are often used. In such a case, it is necessary to make the surface specifications of the terminals different between the substrate side terminal for W / B bonding and the substrate side terminal for FC bonding.
However, in order to connect to a semiconductor chip having a narrow pitch connection terminal, it is required that the wiring board connected to the semiconductor chip be arranged with a narrow pitch with high precision, particularly in the case of FC bonding. This demand is strong.
In addition, in the case of FC bonding, it is preferable that the entire connection terminal portion having a narrow pitch is substantially flat on one surface connected to the conductor chip.
Therefore, when two types of terminals with different surface specifications, that is, a substrate-side terminal for W / B bonding and a substrate-side terminal for FC bonding are arranged on one surface connected to the semiconductor chip, It is preferable that the terminals can be arranged at a narrow pitch, two types of terminals having different surface specifications can be arranged, and the entire surface on the side connected to the semiconductor chip is substantially flat.
As a method for manufacturing a wiring board in which terminals are arranged with a narrow pitch with high precision for connecting to a semiconductor chip having such a narrow pitch connection terminal, it is disclosed in Japanese Patent Laid-Open No. 2003-209336. Moreover, the manufacturing method which employ | adopts the wiring formation method which does not use a core base material which shows the manufacturing process in FIGS. 3-4 is known.
However, in the case of this manufacturing method, as will be described below, it is possible to obtain a wiring board in which terminals for connecting to a semiconductor chip are arranged on one surface with a narrow pitch with high accuracy. It does not form one surface specification terminal.
In the case of this manufacturing method, the entire surface on the side connected to the semiconductor chip is almost flat, which is preferable in this respect.
JP 2003-209336 A

Here, a method for manufacturing a wiring substrate for a semiconductor package shown in FIGS. 3 to 4 will be briefly described.
First, a resist 320 is made on a Cu plate 310 (FIG. 3A) as a supporting base (FIG. 3B), and an Ni layer, an Au layer, An Ni layer and a Cu layer are formed (FIG. 3C), and the resist 320 is peeled off to form a terminal portion 330 as a first layer wiring. (Fig. 3 (d))
Here, the terminal portion is referred to as a first layer wiring.
In some cases, instead of the Ni layer, Au layer, Ni layer, and Cu layer, a Ni layer and a Cu layer may be provided in this order.
Next, after laminating insulating resin 340 and opening holes 345 for forming blind vias by laser (FIG. 3 (e)), desmear treatment is performed as necessary, and in order, Cu electroless plating, resist plate-making, Circuit formation by Cu electrolytic plating, resist stripping, and unnecessary Cu electroless plating etching are performed to form a blind via 318 and a second-layer wiring 315. (Fig. 4 (f))
In addition, a method of forming a circuit by forming a wiring portion and performing a process involving etching in this way is called a semi-additive construction method. On the other hand, a wiring portion is formed only by selective plating without performing etching. The method is referred to as an additive method, and the method of forming a wiring portion by selectively etching a laminated conductive layer (Cu layer) is referred to as a subtractive method.
Next, when a cover layer is required for the second layer wiring 315, a solder resist layer 360 is formed so as to cover the second layer wiring 315, and a predetermined terminal formation region of the second layer wiring 315 is formed. An opening 365 of the solder resist layer 360 is formed so as to be exposed. (FIG. 4 (g)) Next, an Ni layer and an Au layer are sequentially formed on the terminal formation region of the wiring portion 315 exposed from the opening portion 360 of the solder resist layer 360 by electrolytic plating using the Cu plate 310 as a power feeding layer. Deposit the layer. (Fig. 4 (h))
Thereafter, the Cu plate 310 as a supporting base is removed by etching, and the Ni layer exposed by the etching removal of the Cu plate 310 is removed by etching to obtain a target wiring board. (Fig. 4 (i))
Conventionally, since the wiring substrate is formed in such a manner that the plating film is formed on the terminal portion 330 and the terminal portion 380, the first layer wiring (terminal portion 330) side is used as the chip mounting surface. In this case, the surface of the terminal layer 330 of the first layer is the entire surface Au with the same thickness, and the wiring board satisfying the surface plating specifications for W / B bonding and FC bonding of the specifications in which the thickness of the Au plating layer is different. Could not get.

As described above, in the case of SIP, a wiring board based on a resin for a semiconductor package as an interposer or the like, a terminal bonding method of both W / B bonding and FC bonding may be used on one side, In the wiring board to be used, two types of terminals having different specifications, that is, a terminal for W / B bonding and a terminal for FC bonding, are provided on one side of the one side with high accuracy and a narrow pitch. However, it is not possible to form the substrate in a flat shape by the conventional method for manufacturing a wiring board shown in FIGS.
The present invention corresponds to this, and specifically, two types of terminals having different specifications, that is, a terminal for W / B bonding and a terminal for FC bonding, are accurately provided on one surface thereof. An object of the present invention is to provide a wiring board for a semiconductor package as an interposer which is arranged with a narrow pitch and is formed with the one side being flat, and a method for manufacturing the same.

The method for manufacturing a wiring board according to the present invention has two types of connection to a semiconductor chip, one side having a first terminal portion plated with Au and the second terminal portion having pure Cu. Of a wiring board having a terminal portion for use, and including the terminal portion region, the one side being formed in a planar shape, and a terminal portion for connecting to the wiring substrate on the other surface It is a method, Comprising: (a) Ni plating process which forms Ni plating layer by giving Ni plating to the whole one surface on Cu board used as a support base material, (b) It forms on the formed Ni plating layer A first resist is arranged in accordance with the shape of the first terminal portion to be processed, and electroplating is performed using the first resist as a plating-resistant mask, and a Ni layer, an Au layer, and a Ni layer are formed in this order. A first terminal plating step for forming a plating layer for the first terminal portion; and (c). After the resist 1 is peeled off, a second resist is disposed in accordance with the shape of the wiring including the solid Cu terminal portion to be formed on the Cu plate side, and electrolytic plating is performed using the second resist as a plating-resistant mask. A first wiring forming step of depositing Cu by a method and forming a first wiring including a second terminal portion made of pure Cu; and (d) after removing the second resist, an additive method and a semi-additive method. The wiring layer is formed in a state where one or more wiring layers, including the first wiring, are connected between the wiring layers by a subtractive method or the like, and a desired number of wiring layers N (where N is an integer of 2 or more) A wiring layer forming step for wiring; and (e) performing electrolytic plating using a Cu plate as a power feeding layer, and selectively forming a terminal portion (coated with an Au plating layer) of the Nth wiring layer, Second layer to form Ni layer and Au layer in order A terminal plating step; and (f) an Au layer formed by the first terminal plating step by etching the Ni plate exposed by etching and removing the Cu plate, and further forming a first wiring. A Ni etching step is performed in which the Cu layer formed in the step and formed on the entire surface of the Ni plating is exposed.
Then, in the above method for manufacturing a wiring board, after the wiring layer forming step, an area for forming a terminal portion (coated with an Au plating layer) of the Nth wiring layer is opened and exposed, and the N layer A solder resist layer is formed so as to cover the eye wiring layer, and further, electrolytic plating is performed using the Cu plate as a power feeding layer, and a terminal portion of the Nth wiring layer (coated with an Au plating layer) is formed, A second terminal plating step for forming a Ni layer and an Au layer in order is selectively performed. Also, in any one of the above wiring board manufacturing methods, N = 2, and the second wiring layer and the blind via are formed after the second resist is peeled off, Laminate resin, open holes for blind via formation by laser, perform Cu electroless plating on the whole surface, perform resist plate making according to the shape of wiring to be formed and blind via, and use Cu electroless plating layer as current-carrying layer It is characterized by a semi-additive process in which Cu electrolytic plating is performed, resist stripping, unnecessary Cu electroless plating layer etching is performed, and blind via formation and second-layer wiring are formed. .
In addition, any one of the above-described methods for manufacturing a wiring substrate, which is a method for manufacturing a wiring substrate for a semiconductor package as an interposer.
Here, the Nth wiring layer is a wiring layer which is the Nth layer from the first wiring layer where the first wiring is present.

The wiring board of the present invention has, on one side, two types of terminal portions for connection with a semiconductor chip, a terminal portion plated with Au and a terminal portion made of Cu, and these The surface of the one side including the terminal portion region is formed in a planar shape.
And it is said wiring board, Comprising: At least one part of the terminal part which gave Au plating and the terminal part of pure Cu are for connection along the surface of said one side in said one side It is connected by wiring.
Further, in any one of the above wiring boards, the wiring layer has two or more layers, the adjacent wiring layers are connected by blind vias, and the other side facing the one side is connected to the wiring board. The terminal part for carrying out is provided, It is characterized by the above-mentioned.
Also, in any one of the above wiring boards, the one-side-side plated terminal portion and the pure Cu terminal portion, or the plated gold portion and the pure Cu terminal portion And the connection wiring are both formed by an additive method.
In addition, any of the above wiring boards is a wiring board for a semiconductor package as an interposer.

  A semiconductor package according to the present invention uses the wiring board according to claim 8.

(Function)
The manufacturing method of the wiring board according to the present invention has different specifications such as a terminal portion subjected to Au plating for W / B bonding and a pure Cu terminal portion for FC bonding by adopting such a configuration. A method of manufacturing a wiring board for manufacturing a wiring board for a semiconductor package as an interposer in which types of terminals are arranged on one surface with high precision and at a narrow pitch and the one side is formed flat. It is possible to provide.
In the present invention, the first wiring layer including the terminal portion made of pure Cu is formed on the Ni layer by performing Ni plating on the entire surface of the Cu plate as the supporting base material by the Ni plating process. In this case, after the second terminal plating step, the Cu plate can be removed selectively without damaging the wiring portion including the terminal portion where Cu is innocent.
According to the present invention, the wiring composed of the first Cu layer (the first wiring) has a shape completely embedded in the insulating layer, is firmly fixed, and further, Cu and the insulating layer. Since no step is produced at the boundary between the two, the surface flatness can be realized in the portion where the Cu conductor is exposed.
In FC bonding, when underfiller adhesion (adhesion with an underfill resin) is used, if flatness is poor, bubbles may be generated and peeling may occur. However, in the manufacturing method of the present invention, a semiconductor chip is used. Flatness can be improved on the mounting side, and peeling can hardly occur.
Moreover, since the surface of the terminal part which gave Au plating for W / B joining by the side of the 1st wiring is also arrange | positioned inside an insulating layer, it can hold | maintain firmly.
If a cover layer is required for the Nth wiring layer, after the wiring layer forming step, the Nth wiring layer is exposed by opening a region for forming a terminal portion coated with an Au plating layer on the surface. Then, an insulating resin layer (solder resist layer or the like) is formed so as to cover the Nth wiring layer, and further, electrolytic plating is performed using a Cu plate as a power feeding layer, and the surface of the Nth wiring layer Alternatively, a second terminal plating step in which a Ni layer and an Au layer are selectively formed in order in a region where a terminal portion coated with an Au plating layer is formed may be used.
When N = 2, the second wiring layer and the blind via are formed by peeling the second resist, laminating an insulating resin, opening a hole for forming a blind via with a laser, and removing Cu. Electrolytic plating is performed on the entire surface, resist plate making is performed according to the shape of the wiring to be formed and blind vias, Cu electrolytic plating is performed using the Cu electroless plating layer as a current-carrying layer, resist peeling, and unnecessary Cu electroless plating layer is etched After that, by adopting the semi-additive method of forming the second layer wiring along with the blind via formation, the second layer wiring can be formed finely and the whole can be formed thin. It is said.

By adopting such a configuration, the wiring board of the present invention has two types of terminals having different specifications such as a terminal portion plated with Au for W / B bonding and a solid copper terminal portion for FC bonding. Can be provided on one surface of the semiconductor package with high precision and at a narrow pitch, and the wiring substrate for a semiconductor package can be provided as an interposer formed by flattening the one side. At least partially, a terminal portion plated with Au and a solid Cu terminal portion are connected on one side by connection wiring along the surface on the one side. If
Since the solid Cu terminal portion and the connection wiring in the structure can be formed in the same processing step (see the steps shown in FIGS. 1 and 2 described later),
The number of blind vias can be reduced and the fabrication can be simplified compared to a structure in which a blind via is formed separately for each of a pure Cu terminal portion and a terminal portion plated with Au.
The wiring board of the present invention has two or more wiring layers, the adjacent wiring layers are connected by blind vias, and a terminal portion for connecting to the wiring board is provided on the other side facing the one side. The thing of the form which is mentioned is mentioned.
Specifically, both the terminal portion plated with Au and the terminal portion made of pure Cu are formed by an additive method on the one surface, but in this case, a narrow pitch is used. Can be formed with high accuracy.
More specifically, it can be used for a wiring board for a semiconductor package as a multi-terminal interposer.

As described above, the present invention has two types of terminals with different specifications on one side: a terminal portion plated with Au for W / B bonding and a solid Cu terminal portion for FC bonding. Therefore, it is possible to provide a wiring substrate for a semiconductor package as an interposer which is arranged with high accuracy and at a narrow pitch and is formed so that the one side is flat, and a manufacturing method thereof.
Thereby, in the SIP in which a plurality of chips are mounted, options for joining the semiconductor chip and the wiring board substrate are widened, and assembling property and joining reliability are improved.
In addition, high integration, high performance, and thinning of the semiconductor package are possible, and a semiconductor device suitable for high integration can be realized.
In addition, in the SIP in which a plurality of chips are mounted, options for joining the semiconductor chip and the wiring board are widened, so that the degree of freedom in wiring design at the time of designing the wiring board is increased and the design cost is reduced.
In addition, the wiring made of the Cu conductor of the first layer has a shape completely embedded in the insulating layer, and there is no step at the boundary between Cu and the insulating layer, so that the surface is flat in the portion where the Cu conductor is exposed. This is advantageous in terms of mounting a semiconductor chip.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a partial manufacturing process diagram of an example of an embodiment of a method for manufacturing a wiring board according to the present invention, FIG. 2 is a manufacturing process diagram following FIG. 1, and FIG. FIG. 4 is a manufacturing process diagram subsequent to FIG. 3, and FIG. 5 shows a bonding form of the wiring board of the present invention and the semiconductor chip in the semiconductor package.
1 to 5, 110 is a Cu plate (also called a support substrate), 120 is a Ni layer (also called a Ni plating layer), 130 is a resist (also called a first resist), 131 is an opening, and 135 is a resist ( (Also referred to as a second resist) 136 is an opening, 140 is a terminal portion, 141 is a Ni layer, 142 is an Au layer, 143 is a Ni layer, and 150 is a wiring (also referred to as a wiring of the first wiring layer or simply a Cu layer) , 150A is a terminal portion, 155 is a wiring (also referred to as the wiring of the second wiring layer or simply Cu layer), 158 is a blind via, 160 is an insulating resin layer, 170 is an insulating resin layer (solder resist, etc.), 175 is an opening (of an insulating resin layer), 180 is a terminal portion, 181 is a Ni layer, 182 is an Au layer, 510 is a wiring board, 520 is an insulating resin layer, 530 is a terminal, and 531 is a wiring (first wiring) Wiring layer (Also referred to as wiring) 531A is a terminal, 532 is an Ni layer, 533 is an Au layer, 535 is a wiring (also referred to as wiring of the second wiring layer), 536 is an Ni layer, 537 is an Au layer, 538 is a blind via, 550 Is an insulating resin layer (solder resist, etc.), 560 and 565 are semiconductor chips, 561 and 562 are terminals (also called pads) 563 are solder balls, 564 is an under filler, 567 is a bonding wire, 568 is an adhesive layer, Reference numeral 570 denotes a solder ball.

First, an example of an embodiment of a wiring board according to the present invention will be described with reference to FIGS. The manufacturing method of the wiring board of this example includes two types of semiconductor chips, a terminal portion that is plated with Au for W / B bonding and a solid Cu terminal portion for FC bonding on one side. As an interposer having a terminal portion for connection and including these terminal portion regions, the one side is formed in a planar shape, and a terminal portion for connecting to the wiring board is provided on the other surface. A wiring board for a semiconductor package, which has only two wiring layers on the front and back, is manufactured.
First, Ni plating is performed on the entire surface of the Cu plate 110 serving as a supporting base to form the Ni layer 120. (Fig. 1 (a))
Next, a first resist 130 is provided in accordance with the shape of the terminal portion to be formed on the formed Ni layer 120 (FIG. 1B), and electrolysis is performed using the first resist 130 as a plating-resistant mask. Plating is performed to sequentially form a Ni layer 141, an Au layer 142, and a Ni layer 143. (Fig. 1 (c))
As the first resist, a resist having a desired resolution and withstanding Ni plating and Au plating to be performed and having good processability is preferable.
By providing the Ni layer 141, the Au layer can be accommodated in the opening 135 of the resist 130. As a result, when the Ni layer 141 is removed later and the Au layer is exposed on the surface of the terminal, The region can be formed with high accuracy.
In the case where the Au layer is provided directly on the Ni layer 120 without providing the Ni layer 141, the Au layer may penetrate between the resist 130 and the Ni layer 120, and thereby the Au layer is formed on the surface of the terminal. When exposed, the region may not be formed with high accuracy.
In this example, the thickness of the Ni layer 141 may be any thickness that can achieve such a purpose.
The thickness of the Au layer 142 is a thickness that can withstand W / B bonding, and is usually 0.5 μm to 1.0 μm.
The Ni layer 143 is a base for forming the Cu layer, and is usually 5 μm to 10 μm.

Next, after the first resist 130 is peeled off, a second resist 135 is provided in accordance with the shape of the wiring portion including the solid Cu terminal portion to be formed on the Cu plate 110 side. Cu is deposited by an electroplating method using 135 as an anti-plating mask to form a wiring 150 made of a Cu layer including a pure Cu terminal portion. (Fig. 1 (d))
The wiring portion including the terminal portion and the wiring (Cu layer) 150 is collectively referred to as a first wiring layer here.
The wiring 150 preferably has a thickness of about 5 μm to 30 μm from the conductive surface (the surface of the Ni layer 120).
On the Ni layer 120 side of the first wiring layer, both of the second resist 135 formed by photolithography on the Ni layer 120 that is formed by plating on the entire surface of the Cu plate 110 that is the supporting substrate. It is selectively plated on the region exposed from the opening, and can be finely formed with high accuracy.
As the second resist 135, a resist having a desired resolution, having resistance to Cu plating to be performed, and having good processability is preferable.

Next, after removing the second resist 135, in this example, the wiring 155 and the second wiring layer 155 and the second wiring layer are formed on the first wiring layer via the insulating resin layer 160 by a semi-additive method. A blind via 158 for connecting the wiring of the first wiring layer and the wiring of the second wiring layer is formed. (Fig. 2 (h))
The formation of the wiring 155 of the second wiring layer and the formation of the blind via 158 are simply performed by removing the second resist 135, laminating the insulating resin layer 160, and forming a blind via by laser. Open holes, perform desmear treatment as necessary, perform Cu electroless plating over the entire surface, perform resist platemaking according to the shape of the wiring and blind via to be formed, and use Cu electroless plating layer as a current-carrying layer for Cu electroplating Then, the second layer wiring 155 is formed along with the formation of the blind via 158 through an etching process for removing the resist and removing the exposed electroless Cu plating layer by unnecessary flash electroless plating by flash etching.
Etching solutions for flash etching here include hydrogen peroxide, sulfuric acid, ammonium persulfate, sodium persulfate, hydrochloric acid, nitric acid, ferric chloride, copper chloride, cyanide, organic etchants, and mixtures thereof. Is used.
The wiring portion 155 preferably has a thickness of about 5 μm to 30 μm from the viewpoint of conductivity, etc. However, in order to reliably form blind vias in its production, for example, the insulating resin layer 160 has a thickness of 85 μm and the laser irradiation side When the hole diameter is 100 μm and the opposite hole diameter is 70 μm, the thickness is usually about 10 μm to 30 μm.
The electroless Cu plating layer is formed by a known method, and has a thickness that becomes an energization layer when performing electrolytic Cu plating for forming the conductive portion of the wiring 155 and the blind via. It is sufficient that the Cu layer by unnecessary electroless Cu plating has a thickness that can be easily removed without damaging others.
Examples of the insulating resin layer 160 include cyanate resins, BT resins (resins composed of bismaleimide and triazine), epoxy resins, PPE (polyphenylene ether), and the like.
As the laser light, a CO ₂ laser or a UV laser is used according to the material of the insulating resin layer 160.

Next, this example is a case where a cover layer is required for the wiring 155 of the second wiring layer, and the region for forming the terminal portion of the second wiring layer is opened and exposed to form a second layer. An insulating resin layer (solder resist layer or the like) 170 is formed so as to cover the wiring of the wiring layer (FIG. 2 (i)), electrolytic plating is performed using the Cu plate 110 as a power feeding layer, and a second wiring layer The Ni layer 181 and the Au layer 182 are selectively formed in this order in the region where the terminal portion is formed. (Fig. 2 (j))
Usually, a photosensitive insulating resin layer (solder resist layer, etc.) is subjected to mask masking exposure using a predetermined photomask, etc., and further developed to form an insulating resin layer (solder). Resist layer etc.) 170 is formed.
The thickness of the insulating resin layer (solder resist layer, etc.) 170 is normally about 25 μm.
The thickness of the Au layer 182 is usually about 0.1 μm to 0.3 μm for solder ball connection.
The thickness of the Ni layer 181 is about 2 μm.
Next, the Cu plate 110 is removed by etching (FIG. 2 (k)), and the Ni layer 141 exposed by removing the Cu plate 110 is removed by etching, so that the Au layer 142 is exposed. (Fig. 2 (l))
Etching of the Cu plate 110 is usually performed with an alkaline etching solution containing a Cu chelating agent.
Etching of the Ni layer 141 is performed with an acidic etching solution containing a Cu inhibitor (forbidden material), sulfuric acid, hydrogen peroxide, and the like.
Thus, on one side, there are two types of terminal portions for connection to the semiconductor chip, that is, a terminal portion plated with Au and a terminal portion made of pure Cu, and these terminal portions A wiring board for a semiconductor package as an interposer having a terminal portion for connecting to a wiring board on the other side, wherein the wiring layer is composed of two layers on the front and back sides. Only a wiring board can be manufactured.

  In this example, the second wiring layer is formed on the first wiring layer by a semi-additive method to form a wiring board having two wiring layers. After peeling off, connect one or more wiring layers on the wiring 150 of the first wiring layer by an additive method, a semi-additive method, a subtractive method, etc., and connect each wiring layer including the first wiring. The multi-layered wiring having the desired number of wiring layers N (where N is an integer of 2 or more) is equivalent to this example, and a terminal portion with Au plating on one side and a solid Cu terminal Two terminal parts for connecting to the semiconductor chip, and including these terminal part regions, the one side is formed in a planar shape and connected to the wiring board on the other surface A wiring board having two or more wiring layers can be manufactured with a terminal portion for

Next, an example of the embodiment of the wiring board according to the present invention will be described with reference to FIG.
This example is formed by the manufacturing method shown in FIG. 1 to FIG. 2, and as shown in FIG. 2 (l), on one side, a terminal part 140 with Au plating and a pure Cu The terminal portion 150A has two types of terminal portions for connection to the semiconductor chip, the other side has a terminal portion 180 plated with Au, and includes the regions of the terminal portions 140 and 150A. One side is formed flat.
And it is a wiring board as an interposer for a semiconductor package in which the wiring 150 is formed by an additive method including the terminal portions on the terminal portions 140 and 150A side.
About each part, it replaces with description in the manufacturing method shown in said FIGS. 1-2, and abbreviate | omits. By adopting such a configuration, it is possible to cope with the narrowing of the pitch of the terminal portion with high accuracy and to perform the FC junction and the W / B junction with the semiconductor chip without problems on the side where the terminal portions 140 and 150A are formed. Yes.
In this example, the Au-plated terminal portion 140 and the solid Cu terminal portion 150A are connected on one side by connection wiring (wiring 150) along the surface of the one side. Yes.
As a modification of the wiring board of this example, a wiring board having three or more wiring layers can be cited.
Such a wiring board is formed by forming a second wiring layer on the first wiring layer by a semi-additive method in the manufacturing method of the wiring board shown in FIGS. Although the wiring substrate having the wiring layer is formed, one or more wiring layers are formed on the wiring 150 of the first wiring layer after the second resist 135 is removed by an additive method, a semi-additive method, a subtractive method, or the like. In this case, the wiring layers including the first wiring are formed in a connected state to form a multilayer wiring having a desired number of wiring layers N (where N is an integer of 2 or more).

  In the wiring board of this example or at least a part of the above-described modification, without providing the connecting wiring (wiring 150) for connecting the terminal portion 140 plated with Au and the terminal portion 150A made of pure Cu, On the side where the solid Cu terminal portion 150A is formed, the Au-plated terminal portion 140 and the solid Cu terminal portion 150A are separated, and the wiring 155 and the solid Cu terminal facing the solid Cu terminal portion forming side are separated. The thing of the form which performs the connection with 150A with a blind via different from the terminal part 140 which gave Au plating is also mentioned.

The wiring board of this example (510 corresponds to this in FIG. 5) is provided as, for example, a semiconductor package shown in FIG.
The semiconductor package shown in FIG. 5 has, on the wiring substrate 510, on one side having two terminal parts for connection with a semiconductor chip, a terminal part plated with Au and a terminal part made of Cu. The semiconductor chip 560 is mounted while being held by the underfiller 564, the semiconductor chip 565 is mounted on the semiconductor chip 560 with an adhesive layer, and the semiconductor chip 560 is electrically connected to the wiring substrate 510 by FC bonding, The semiconductor chip 565 is electrically connected to the wiring substrate 510 by W / B bonding, and solder balls 570 are mounted on the terminals having the Au coating on the other side of the wiring substrate 510 facing the one side. Used as a semiconductor package.

It is a partial manufacturing process figure of one example of embodiment of the manufacturing method of the wiring board of this invention. FIG. 2 is a manufacturing process diagram following FIG. 1. It is a partial manufacturing process figure of the manufacturing method of the conventional wiring board. FIG. 4 is a manufacturing process diagram following FIG. 3. 1 shows a bonding form of a wiring board of the present invention and a semiconductor chip in a semiconductor package.

Explanation of symbols

110 Cu plate (also called support substrate)
120 Ni layer (also called Ni plating layer)
130 resist (also referred to as first resist)
131 (resist) opening 135 resist (also referred to as second resist)
136 (Resist) opening 140 Terminal portion 141 Ni layer 142 Au layer 143 Ni layer 150 Wiring (also referred to as wiring of the first wiring layer or simply Cu layer)
150A terminal portion 155 wiring (also referred to as wiring of the second wiring layer or simply Cu layer)
158 Blind via 160 Insulating resin layer 170 Insulating resin (solder resist, etc.)
175 Opening 180 (of insulating resin) Terminal portion 181 Ni layer 182 Au layer 310 Cu plate (also called support substrate)
320 Resist 325 Resist opening 330 Terminal portion 331 Ni layer 332 Au layer 333 Ni layer 340 Insulating resin layer 345 Blind via hole 318 Blind via 315 Cu wiring 360 Insulating resin layer (solder resist)
365 Opening of insulating resin layer (solder resist opening)
380 Terminal portion 381 Ni layer 382 Au layer 510 Wiring substrate 520 Insulating resin layer 530 Terminal 531 Wiring (also referred to as wiring of the first wiring layer)
531A Terminal 532 Ni layer 533 Au layer 535 Wiring (also referred to as wiring of the second wiring layer)
536 Ni layer 537 Au layer 538, 539 Blind via 550 Insulating resin layer (solder resist layer, etc.)
560, 565 Semiconductor chips 561, 562 Terminals (also referred to as pads)
563 Solder ball 564 Under filler 567 Bonding wire 568 Adhesive layer 570 Solder ball 610 Wiring board 611, 612 Terminal portion 620, 625 Semiconductor chip 621, 626 Terminal portion (also referred to as pad or bump)
630 Bonding wire 635 Solder ball 637 Under filler 640 Solder ball

Claims (10)

  On one side, there are two types of terminal portions for connection to a semiconductor chip, a first terminal portion whose surface is plated with Au and a second terminal portion made of pure Cu, and A method of manufacturing a wiring board including these terminal part regions, wherein one side is formed in a planar shape, and a terminal part for connecting to the wiring board is provided on the other side. A Ni plating step for forming a Ni plating layer by performing Ni plating on the entire surface of a Cu plate as a supporting substrate; and (b) the shape of the first terminal portion to be formed on the formed Ni plating layer. In accordance with the above, a first resist is disposed, electrolytic plating is performed using the first resist as a plating-resistant mask, a Ni layer, an Au layer, and a Ni layer are formed in this order, and a plating layer for the first terminal portion A first terminal plating step for forming the substrate, and (c) after removing the first resist, C A second resist is disposed in accordance with the shape of the wiring including the solid Cu terminal portion to be formed on the plate side, Cu is deposited by electrolytic plating using the second resist as a plating-resistant mask, and the pure Cu is formed. A first wiring forming step for forming the first wiring including the second terminal portion; and (d) after the second resist is removed, the wiring layer is formed by an additive method, a semi-additive method, a subtractive method, or the like. A wiring layer forming step in which one or more layers including the first wiring are formed in a state where the wiring layers are connected to each other to form a multilayer wiring having a desired number of wiring layers N (where N is an integer of 2 or more); (E) Electroplating is performed using a Cu plate as a power feeding layer, and a Ni layer and an Au layer are selectively formed in order in a region where a terminal portion (coated with an Au plating layer) of the Nth wiring layer is formed. A second terminal plating step; and (f) Cu. And etching the Ni layer exposed by etching away the Cu plate to form an Au layer formed in the first terminal plating process, and on the entire surface of the Ni plating formed in the first wiring formation process. A method of manufacturing a wiring board, comprising performing an Ni etching step in which a formed Cu layer is exposed.   2. The method for manufacturing a wiring board according to claim 1, wherein after the wiring layer forming step, an area for forming a terminal portion coated with an Au plating layer of the Nth wiring layer is opened and exposed to form an N layer. An insulating resin layer (solder resist layer, etc.) is formed so as to cover the wiring layer, and further, electrolytic plating is performed using a Cu plate as a power feeding layer, and the Au plating layer of the Nth wiring layer is coated. A method of manufacturing a wiring board, comprising performing a second terminal plating step of selectively forming a Ni layer and an Au layer in order in a region where the film is formed.   3. The method of manufacturing a wiring board according to claim 1, wherein N = 2, and the second wiring layer and the blind via are formed after the second resist is removed. , Laminating insulating resin, opening holes for forming blind vias by laser, performing Cu electroless plating over the entire surface, performing resist engraving according to the shape of the wiring and blind vias to be formed, Cu electroless plating layer It is based on a semi-additive method in which Cu electroplating is used as a current-carrying layer, resist stripping, unnecessary Cu electroless plating layer etching, and blind via formation and second-layer wiring are formed. A method of manufacturing a wiring board.   4. The method for manufacturing a wiring board according to claim 1, wherein the wiring board is a manufacturing method for a semiconductor package as an interposer.   On one side, there are two types of terminal parts for connection to a semiconductor chip, a terminal part plated with Au and a terminal part made of pure Cu, and includes these terminal part regions. A wiring board characterized in that the surface on one side is formed in a planar shape.   The wiring board according to claim 5, wherein at least a part of the Au plated terminal portion and the pure Cu terminal portion are along the surface of the one side on the one side. A wiring board characterized by being connected by connection wiring.   The wiring board according to any one of claims 5 to 7, wherein there are two or more wiring layers, adjacent wiring layers are connected by a blind via, and the other side facing the one side is disposed on the other side. A wiring board comprising a terminal portion for connection to the wiring board.   The wiring board according to any one of claims 5 to 8, wherein the one-sided Au-plated terminal portion and the pure Cu terminal portion, or the Au-plated terminal portion; Both of the solid copper terminal portion and the connection wiring are formed by an additive method.   9. The wiring board according to claim 5, wherein the wiring board is a semiconductor package wiring board as an interposer. A semiconductor package comprising the wiring board according to claim 9.

Images