JP2005234914A - Circuit simulation apparatus and debug apparatus for semiconductor tester program using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit simulation apparatus, which reduces time required for simulations and maintains high precision features with signal paths necessary for detailed verification, and a debug apparatus for semiconductor tester programs using the apparatus. <P>SOLUTION: The circuit simulation apparatus has an analysis condition setting part 1, which sets analysis conditions necessary for simulation execution, and a related function block search part 3, which is composed of a plurality of function blocks and retrieves function blocks related to signal paths specified by the analysis condition setting part using circuit information on verified circuits that are created so as to be mutually converted between element and function description language levels. In addition, the circuit simulation apparatus also has a simulation level setting part 4 for function blocks, which sets simulation levels for function blocks related to the signal paths and for ones not related to them to information described at an element level and to information described at a function description language level respectively. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a circuit simulation apparatus for a semiconductor integrated circuit corresponding to a large-scale circuit, and a debugging apparatus for a program for a semiconductor tester using the circuit simulation apparatus.

  As the scale of semiconductor integrated circuits increases, the time required for simulation at the circuit design verification stage has also increased significantly. In particular, in the simulation of the entire integrated circuit, it is desirable that the entire function verification, variation analysis, and the like are performed when the detailed design of each functional block is completed. However, conventionally, in the case of an analog circuit, it is common to perform analysis at the element level using a SPICE-based simulator, and the time required for the analysis requires enormous calculation time for a large-scale circuit. . Therefore, at present, almost no simulation of the entire integrated circuit is performed. As a breakthrough, analog HDL is used to express analog behavior in a description language (Reference: DESIGN WAVE MAGAZINE No.8 “Analog HDL Design Method” P68-75, Naoya Toyama, CQ Publishing Co.) It is conceivable to reduce the simulation time of the analog / digital MIX circuit.

In recent years, at the test design verification stage, a semiconductor tester for testing an IC is virtually realized on a computer, and an integrated circuit test program or tester board (jig ”Can be debugged, and is disclosed in, for example, Japanese Patent Laid-Open No. 9-185519. This debug device requires information on a virtual IC under test, that is, simulation information for the entire integrated circuit, and normally uses circuit information used in the circuit design verification stage.
JP-A-9-185519 DESIGN WAVE MAGAZINE No.8 P68 ~ 75 “Analog HDL Design Method”

  As shown in the above document, the simulation time can be shortened by expressing analog operations in the description language in the circuit design verification stage. However, in the simulation using such a function description language, Since the functional block is treated as an ideal model, the accuracy may be low and satisfactory results may not be obtained.

  For this reason, when simulating multiple functional blocks in an integrated circuit, the functional block that has a direct effect on the results by the circuit designer himself is a functional model that has little influence on the element level model. As in the description language model, the simulation levels of all the functional blocks in the integrated circuit are set to increase the accuracy and to shorten the simulation time. However, in the overall verification of a large-scale semiconductor integrated circuit, the operation of setting the simulation level for each functional block takes a lot of man-hours and setting errors are likely to occur.

  In the test design using the semiconductor tester program debugging device disclosed in the above publication, a plurality of different test measurement conditions are continuously set and verified using circuit information used in the circuit design stage. ing. That is, the simulation level of all the functional blocks in the integrated circuit must be manually set for each inspection measurement condition, which is very inefficient. Moreover, test design is usually designed by a tester different from the circuit designer and may not know the details of the integrated circuit, resulting in increased simulation time and design errors. Cheap.

  The present invention was made paying attention to the above viewpoint, and by automatically setting the simulation level of each functional block, while reducing the time required for simulation, in the signal path that requires detailed verification, A circuit simulation device capable of maintaining high-precision characteristics, and a semiconductor that can be easily used by a test designer who is not familiar with internal circuits by using the circuit simulation device and can shorten the time required for verification An object is to provide a debugging apparatus for a test program.

  In order to solve the above problems, the invention according to claim 1 is composed of an analysis condition setting means for setting an analysis condition necessary for executing the simulation and a plurality of functional blocks, and between the element level and the function description language level. Related function block search means for searching for a function block related to the signal path determined by the analysis condition setting means from circuit information related to the circuit to be verified created so as to be convertible with each other, and a function block related to the signal path Is a circuit simulation device comprising functional block simulation level setting means for setting the simulation level to the information described at the element level and the unrelated function blocks to the information described at the function description language level. is there.

  The invention according to claim 2 is the circuit simulation apparatus according to claim 1, wherein the related function block search means sets a route search label so that input / output of each terminal of the function block can be determined. Block terminal label setting means, functional block connection information extracting means for extracting connection information of each terminal between the functional blocks, and an input signal section for inputting an application signal defined by the analysis condition setting means to the circuit to be verified A function block through which the applied signal passes with the output measuring unit that measures the output of the circuit to be verified with respect to the applied signal is searched using information from the functional block terminal label setting means and the functional block connection information extracting means. Signal path search means and functional block specifying means for specifying related functional blocks from the search result of the signal path search means It is characterized in that it has a.

  According to a third aspect of the present invention, in the circuit simulation apparatus according to the first or second aspect of the present invention, the circuit simulation device includes an output unit that displays a simulation level state of each functional block set by the functional block simulation level setting unit. It is characterized by.

  The invention according to claim 4 is characterized in that the circuit simulation apparatus according to claim 1 or 2 further comprises continuous analysis means for continuously analyzing a plurality of different analysis items.

  The invention according to claim 5 is the circuit simulation apparatus according to claim 4, further comprising output means for displaying a simulation level state of each functional block set for each of the plurality of different analysis items. It is what.

  According to a sixth aspect of the present invention, there is provided a semiconductor tester program debugging device using the circuit simulation device according to any one of the first to fifth aspects.

  According to the circuit simulation device of the first and second aspects, the simulation level of each functional block can be set automatically so that no man-hours are required and no setting mistakes are made. On the other hand, a circuit simulation apparatus that can maintain highly accurate characteristics can be realized in a signal path that requires detailed verification. According to the circuit simulation apparatus of the third aspect, it is possible to realize a circuit simulation apparatus that can easily check the simulation level of the automatically set function block. According to the circuit simulation apparatus of the fourth aspect, the simulation level of each functional block can be automatically set for each inspection / measurement condition so that no man-hours are required and there is no setting error. A circuit simulation device capable of maintaining high-precision characteristics can be realized in a signal path that requires detailed verification while shortening. According to the circuit simulation apparatus of the fifth aspect, it is possible to realize a circuit simulation apparatus that can easily check the simulation level of each functional block set automatically for each measurement item. According to the semiconductor tester program debugging apparatus according to claim 6, a semiconductor tester program debugging apparatus that can be easily used by a test designer who is not familiar with the internal circuit and that can shorten the time required for verification is realized. it can.

  Next, the best mode for carrying out the invention will be described.

  FIG. 1 is a block diagram showing a first embodiment of a circuit simulation apparatus according to the present invention. The first embodiment corresponds to the inventions according to claims 1 and 3. As shown in FIG. 1, the circuit simulation apparatus according to the first embodiment includes an analysis condition setting unit 1, a circuit information unit 2 that reads circuit connection information related to a circuit to be verified, and a plurality of functional blocks. Function blocks related to signal paths determined from information in the analysis condition setting unit 1 based on circuit information in the circuit information unit 2 related to the circuit to be verified, which is created so as to be convertible between the function description language level and the function description language level. The function level search unit 3 searches for the function level, the function block related to the signal path sets information at the element level, and the non-related function block sets information at the function description language level. Function block simulation level setting section 4, simulation level display section 5 of each function block, simulation A down execution unit 6, and a simulation result output section 7. The operation of each unit is executed by control by a control unit such as a CPU (not shown) having an external input operation unit.

  Next, the operation of the circuit simulation apparatus configured as described above will be described. FIG. 2 is a flowchart for explaining the outline of the operation of the circuit simulation apparatus according to the first embodiment. FIG. 3 shows an example of the functional block configuration, which has a circuit model at the element level such as a transistor and a model at the function description language level. The function description language level model is a function description language such as Verilog-HDL, VHDL, VHDL-A, or Verilog-A. Also, a digital circuit such as a logic unit does not necessarily have element level circuit information.

  The operation of the circuit simulation apparatus according to the first embodiment will be described with reference to the flowchart of FIG. In reading the circuit diagram information in step S1, circuit connection information of the circuit to be verified described at the function description language level is read into the circuit information unit 2. In reading the analysis conditions in step S2, the analysis conditions are read into the analysis condition setting unit 1 in order to set conditions necessary for the analysis of the circuit to be verified. Next, in step S3, the related function block search unit 3 searches for a signal path to search for a function block related to the signal path. In the function block simulation level setting in step S4, the function block related to the signal path in the function block simulation level setting unit 4 is described at the element level, and the function block not related is described at the function description language level. The simulation level is set for each of the function blocks, and the simulation level of each functional block is displayed on the simulation level display unit 5. In step S5, the simulation execution unit 6 executes a simulation in the state of each function level set by the simulation level setting unit 4, that is, in a mixed level state, and outputs the result to the result output unit 7 (step S6). .

  FIG. 4 is an explanatory diagram showing a specific example of setting one analysis condition. As shown in FIG. 4, first, connection information between the functional blocks A to H as shown in the circuit to be verified 12 is read into the circuit information section 2. In addition, the analysis condition setting unit 1 performs necessary analysis condition setting for each input / output terminal of the circuit 12 to be verified, and an input signal unit 11-1 for inputting the application signal of the AC signal in the application signal input / output unit 11; The output measuring unit 11-2 for measuring the output of the circuit to be verified is set. Next, the related function block search unit 3 extracts the function block A, the function block E, and the function block H existing in the signal path between the input signal unit 11-1 and the output measurement unit 11-2. The function block A, function block E, and function block H extracted by the related function block search unit 3 are used as element level models, and the other function blocks B, C, D, F, and G are used as function description language level models. Set. The simulation level display unit 5 has a function of displaying the simulation level of each functional block set automatically, so that the designer can check the state.

  In this way, the simulation level of each functional block can be set automatically so that no man-hours are required and no setting mistakes are made, so the time required for simulation can be reduced even in the overall verification of large-scale semiconductor integrated circuits. On the other hand, a circuit simulation apparatus that can maintain highly accurate characteristics can be realized in a signal path that requires detailed verification.

  Next, Example 2 will be described. FIG. 5 is a block diagram illustrating a configuration of a related function block search unit in the circuit simulation apparatus according to the second embodiment. The second embodiment corresponds to the invention according to claim 2. The related function block search unit in the second embodiment includes a function block terminal label setting unit 3-1 for setting a route search label to each terminal of the function block, and a function block for extracting connection information of each terminal between the function blocks. An applied signal passes between the connection information extracting unit 3-2, an input signal unit that inputs an application signal specified by the analysis condition to the circuit to be verified, and an output measurement unit that measures the output of the circuit to be verified with respect to the applied signal. The function block is composed of a signal route search unit 3-3 for searching using the route search label and the connection information, and a function block specifying unit 3-4 for specifying a related function block from the search result. ing. As the route search label, if the input / output of each terminal of the functional block has already been distinguished in the circuit diagram information, the information is set as it is. Also, if the symbol that distinguishes each terminal of the functional block is different from the table that defines whether the symbol is input or output, the definition of this table is set for each terminal of the functional block. .

  Next, the operation of the related function block search unit configured as described above will be described. FIG. 6 is a flowchart for explaining the outline of the operation of the related function block search unit, and the operation will be described along this flowchart. First, the function block terminal label setting unit 3-1 reads information into each terminal of the function block, and sets a label at each terminal of the function block (step S11). As shown in FIGS. 7A and 7B, the labels set for each terminal of the functional block are, for example, IN and input terminals of the functional block A (op-amp) and functional block E (switch), respectively. Is set to OUT. Next, the function block connection information extraction unit 3-2 reads and extracts connection information of each terminal between the function blocks (step S12). Next, in the signal path search unit 3-3, an input signal unit that inputs the applied signal to the circuit to be verified and an output measuring unit that measures the output of the circuit to be verified with respect to the applied signal are extracted from the analysis conditions (step S13). Next, the signal path is searched. That is, first, (1) a functional block having an IN label connected to the input signal unit is extracted (step S14). Next, (2) a functional block in which the IN label is connected to the OUT label of the extracted functional block is extracted (step S15). Next, the search in (2) above is repeated for all connection information (step S16), and it is extracted whether the output measurement unit is connected to the OUT label of any functional block, and the signal that has not reached the output measurement unit The route is omitted (step S17). Then, each functional block existing in the remaining signal path without being omitted is specified as a functional block related to the signal path (step S18).

  More specifically, referring to FIG. 4, first, (1) a functional block A (op-amp) having an IN label connected to the input signal unit 11-1 is extracted, and (2) OUT of the functional block A is extracted. The function block E (switch) and the function block F (comparator) in which the IN label is connected to the label are extracted. Next, (3) the function block H (buffer) in which the IN label is connected to the OUT label of the function block E is extracted. Since there is nothing connected to the OUT label of the functional block F, this signal path search is ended. It is extracted that the output measuring unit 11-2 is connected to the OUT label of the function block H. Next, (4) the signal path that did not reach the output measuring unit 11-2, that is, the signal path other than the path of the function block A → the function block E → the function block H is omitted. (5) The function block A, function block E, and function block H in the remaining signal path are specified as function blocks related to the signal path. In the present embodiment, a method for searching for connection information from the input signal unit has been described. However, there is no problem as long as a route can be identified, such as a reverse search from the output measurement unit to the input signal unit.

  In this way, by automatically searching for signal paths that require detailed verification and identifying the function blocks included in the paths, it is not necessary to manually set the simulation level for each function block, and there is a setting error. It is possible to set the simulation level of each functional block without any.

  Next, Example 3 will be described. The third embodiment corresponds to the inventions according to claims 4 and 5. In this embodiment, in the first embodiment shown in FIG. 1, a function for continuously analyzing a plurality of different measurement items, and an output for displaying a level state of each functional block of a simulation set for each measurement item. The part is added. In other words, the simulation level of each functional block is set according to a certain analysis condition, and after executing the simulation, another measurement condition is newly read and a signal path search is performed according to that information. Set according to the number of measurement items. Specifically, after the setting under the analysis conditions shown in FIG. 4, the simulation is executed, and then the setting is performed under the analysis conditions as shown in FIG. To analyze. This continuous analysis operation is also executed under the control of a control unit such as a CPU (not shown). In the setting under the analysis conditions shown in FIG. 8, the functional block B (op-amp) having the IN label connected to the input signal unit 11-1 is extracted, and the IN label is connected to the OUT label of the functional block B. The function block G (comparator) is extracted, the fact that the output measuring unit 11-2 is connected to the OUT label of the function block G is extracted, and the function block B and the function block G are specified as function blocks related to the signal path. To do. Note that the simulation level setting of each functional block corresponding to each measurement item may be performed in a lump instead of being performed for each simulation.

  According to the circuit simulation apparatus configured as described above, it is not necessary to manually set the simulation level of each functional block for each inspection measurement condition, and so that there is no setting mistake, each functional block is automatically set. Since the simulation level can be set, it is possible to realize a circuit simulation apparatus that can maintain high-accuracy characteristics in a signal path that requires detailed verification while shortening the time required for the simulation.

  Next, Example 4 will be described. FIG. 9 is a block diagram showing a fourth embodiment according to the present invention. This embodiment corresponds to the invention according to claim 6. In this embodiment, the circuit simulation apparatus according to the first to third embodiments is used as a debugging apparatus for a semiconductor tester program. In FIG. 9, the information part 2 ′ of the virtual IC under test, which is the circuit to be verified, corresponds to the circuit information part 2 in the first embodiment shown in FIG. The test condition setting unit 1 ′ of the pseudo IC tester corresponds to the simulation analysis condition setting unit 1 in the first embodiment shown in FIG.

  The test conditions of the pseudo IC tester may be extracted from a test program or input from a test item table or the like. Usually, the number of IC test items is several hundred or more, and the ability to automatically set the simulation level of each functional block is very effective in terms of man-hours. The semiconductor tester program debugging apparatus configured as described above realizes a semiconductor tester program debugging apparatus that can be easily used by a test designer who is not familiar with the internal circuit and can shorten the time required for verification. it can.

It is a block diagram which shows the structure of Example 1 of the circuit simulation apparatus which concerns on this invention. It is a flowchart for demonstrating the operation | movement of FIG. It is a figure which shows the functional block searched by the related functional block search part of Example 1 shown in FIG. It is explanatory drawing which shows the specific example of the setting of the analysis condition by the analysis condition setting part in Example 1 shown in FIG. It is a block diagram which shows the structure of the related function block search part in the circuit simulation apparatus which concerns on Example 2 of this invention. It is a flowchart for demonstrating operation | movement of Example 2 shown in FIG. It is a figure which illustrates the label which the functional block terminal label setting part in Example 2 shown in FIG. 5 sets. It is explanatory drawing which shows the specific example of the setting of the analysis condition following the setting of the analysis condition shown in FIG. 4 in the case of performing analysis continuously in Example 3 of the present invention. It is a block diagram which shows the structure of the debugging apparatus of the program for semiconductor testers which concerns on Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Analysis condition setting part 2 Circuit information part 3 Related function block search part 4 Simulation level setting part of related function block 5 Simulation level display part of related function block 6 Simulation execution part 7 Result output part
11 Applied signal input / output section
11-1 Input signal section
11-2 Output measurement section
12 Circuit to be verified 3-1 Function block terminal label setting section 3-2 Function block connection information extraction section 3-3 Signal path search section 3-4 Function block identification section in signal path 1 'Pseudo IC tester test condition setting section 2 'Information section of virtual IC under test

Claims (6)

  Analysis condition setting means for setting analysis conditions necessary for simulation execution, and circuit information related to the circuit to be verified, which consists of a plurality of functional blocks and can be converted between the element level and the function description language level. A function block search means for searching for a function block related to a signal path determined from the analysis condition setting means; a function block related to the signal path is information described at an element level; A circuit simulation apparatus comprising: function level simulation level setting means for setting a simulation level to information described at a language level.   The related function block search means extracts function block terminal label setting means for setting a route search label so that input / output of each terminal of the function block can be discriminated, and connection information of each terminal between the function blocks. An application signal between the functional block connection information extracting means, an input signal section for inputting the application signal defined by the analysis condition setting means to the circuit to be verified, and an output measurement section for measuring the output of the circuit to be verified with respect to the application signal Signal path search means for searching for function blocks using the information from the function block terminal label setting means and the function block connection information extraction means, and related function blocks from the search result of the signal path search means. The circuit simulation apparatus according to claim 1, further comprising a function block specifying unit that specifies the function block.   3. The circuit simulation apparatus according to claim 1, further comprising an output unit that displays a simulation level state of each functional block set by the simulation level setting unit of the functional block.   The circuit simulation apparatus according to claim 1, wherein the circuit simulation apparatus includes continuous analysis means for continuously analyzing a plurality of different analysis items.   5. The circuit simulation apparatus according to claim 4, further comprising output means for displaying a simulation level state of each functional block set for each of the plurality of different analysis items.   A debugging device for a program for a semiconductor tester using the circuit simulation device according to any one of claims 1 to 5.

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