JP2005229225A - Analog/digital converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure a sufficient comparing period for AD conversion processing even for a change in an operation timing of another component, in an analog/digital converter comprising an AD conversion portion shared in time division. <P>SOLUTION: A first amplifier circuit 11 samples and holds an input analog signal Vin and outputs the signal to a subtracting circuit 14. An AD conversion circuit 12 converts an analog signal to be entered into a digital value and takes out a predetermined bit. A DA conversion circuit 13 converts the digital value converted by the circuit 12 into an analog value. A subtracting circuit 14 subtracts an output analog signal of the circuit 13 from an analog signal inputted via a first switch SW1 and the circuit 11. A second amplifier circuit 15 amplifies an output analog signal of the circuit 14 to be doubled and outputs the signal to a poststage. An input switching circuit 16 controls an order of entering the input analog signal Vin and a reference voltage Vref into a voltage comparing element constituting the circuit 12. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an analog-digital converter. In particular, the present invention relates to an analog-to-digital converter including an analog-to-digital portion that is time-shared.

In recent years, various additional functions such as an image photographing function, an image reproducing function, a moving image photographing function, and a moving image reproducing function have been installed in portable devices such as mobile phones. Accordingly, there is an increasing demand for miniaturization and power saving of analog-digital converters (hereinafter referred to as “AD converters”). As a form of such an AD converter, a cyclic AD converter configured in a circulation type is known (see, for example, Patent Document 1). Patent Document 1 discloses an AD converter having two stages including a cyclic conversion portion. Patent Document 1 discloses a pipeline AD converter including two stages including a cyclic conversion portion.
JP-A-4-26229

  In the first stage of the AD converter shown in FIG. 1 of Patent Document 1, a sample and hold circuit S / H1 is provided in parallel with a system comprising a parallel A / D converter AD1 and a D / A converter DA1. Is provided. The analog input signal of this circuit is held for a predetermined period by this sample and hold circuit S / H1.

  However, since an operational amplifier is included in the constituent elements of the sample-and-hold circuit, the output voltage range of the sample-and-hold circuit tends to narrow when the voltage is low. There is a problem that characteristic degradation such as distortion due to narrowing of the output voltage range of the sample-and-hold circuit becomes large at low voltage, and the characteristics of the entire AD converter deteriorate. On the other hand, if the sample and hold circuit is removed, the comparison period between the voltage value of the input signal of the AD conversion circuit and the reference voltage value is shortened due to the timing shift, or the amplification period of the amplifier circuit is shortened. There's a problem. If the amplification period of the amplifier circuit is shortened, the settling time may not be ensured.

  The present invention has been made in view of such circumstances, and an object of the present invention is to perform AD conversion even when the operation timing of other components is changed in an analog-to-digital converter including an AD conversion portion shared in time division. This is to ensure a sufficient comparison period for processing.

  One embodiment of the present invention is an analog-digital converter. This analog-digital converter includes an AD conversion circuit that converts an input analog signal into a digital value having a predetermined number of bits, and a voltage comparison element that constitutes the AD conversion circuit. An input switching circuit that switches between values and inputs, and the input switching circuit switches between the voltage value of the analog signal and the reference voltage value in accordance with the operation timing of other components.

  According to this aspect, the voltage input to the AD conversion circuit is not always in the order of the input voltage value and the reference voltage value, and the reverse input order can also be performed. By properly using these input orders corresponding to the operation timing of other constituent elements, for example, the sampling order of input voltage values, it is possible to ensure the comparison period of the voltage comparison elements constituting the AD converter circuit. . Therefore, each component element operates regularly, and the generation of the clock signal is facilitated.

  Another aspect of the present invention is also an analog-digital converter. The analog-digital converter includes an AD conversion circuit that converts an input analog signal into a digital value having a predetermined number of bits, a DA conversion circuit that converts an output of the AD conversion circuit into an analog signal, and an output from the input analog signal to the DA conversion circuit. The voltage value of the input analog signal and the predetermined reference voltage value are switched and input to the subtractor circuit that subtracts the analog signal, the amplifier circuit that amplifies the output of the subtractor circuit, and the voltage comparison element that constitutes the AD converter circuit. The input switching circuit switches between the voltage value of the analog signal and the reference voltage value according to the operation timing of the amplifier circuit.

  According to this aspect, the voltage input to the AD conversion circuit is not always in the order of the input voltage value and the reference voltage value, and the reverse input order can also be performed. By properly using these input orders corresponding to the operation timing of the amplifier circuit, that is, the order of the auto-zero period and the amplification period, it is possible to secure the comparison period of the voltage comparison elements constituting the AD converter circuit. In addition, the amplification period of the amplifier circuit can be secured. Therefore, each component element operates regularly, and the generation of the clock signal is facilitated.

  Another aspect of the present invention is also an analog-digital converter. The analog-digital converter includes an AD conversion circuit that converts an input analog signal into a digital value having a predetermined number of bits, a DA conversion circuit that converts an output of the AD conversion circuit into an analog signal, and an output from the input analog signal to the DA conversion circuit. The voltage value of the input analog signal and the predetermined reference voltage value are switched and input to the subtractor circuit that subtracts the analog signal, the amplifier circuit that amplifies the output of the subtractor circuit, and the voltage comparison element that constitutes the AD converter circuit. Provided between the input switching circuit, the input and the subtraction circuit, the sample hold circuit that samples and holds the input analog signal, and the path between the input and the subtraction circuit, either the direct path or the path via the sample hold The input switching circuit has a reference voltage value during a period in which the switch directly selects a path. Previously, it is input after the voltage value of the input analog signal.

  According to this aspect, the reference voltage value is input first and the voltage value of the input analog signal is input later to the voltage comparison element constituting the AD conversion circuit while the switch directly selects the path. As a result, it is possible to prevent the comparison period of the voltage comparison element and the useless period of the amplifier circuit, which occur when the voltage value of the input analog signal is input first.

  Another aspect of the present invention is also an analog-digital converter. This analog-digital converter is a pipeline-type or cyclic-type analog-digital converter, which converts an input analog signal into a digital value of a predetermined number of bits, and outputs the output of the AD conversion circuit as an analog signal. Voltage comparison that constitutes an AD converter circuit, a DA converter circuit that converts the signal, a subtractor circuit that subtracts the output analog signal of the DA converter circuit from the input analog signal, an amplifier circuit that amplifies the output of the subtractor circuit The element has an input switching circuit for switching and inputting a voltage value of an input analog signal and a predetermined reference voltage value, and the input switching circuit is fed back from the voltage value of the input signal from the previous stage and from the subsequent stage. The input signal voltage value and the reference voltage value are switched according to the operation timing of the amplifier circuit.

  According to this aspect, regarding the input order of a plurality of input voltage values and reference voltage values input to the AD converter circuit, depending on the type of input, the input order of the input voltage value and the reference voltage value and the reverse input order are determined. Can be used. By properly using these input orders corresponding to the operation timing of the amplifier circuit, that is, the order of the auto-zero period and the amplification period, it is possible to secure the comparison period of the voltage comparison elements constituting the AD converter circuit. In addition, the amplification period of the amplifier circuit can be secured. Therefore, each component element operates regularly, and the generation of the clock signal is facilitated.

  The input switching circuit includes the voltage value of the input signal from the previous stage, the first reference voltage value for the input signal, the voltage value of the input signal fed back from the subsequent stage, and the second reference voltage value for the input signal of the amplifier circuit. It may be switched according to the operation timing. According to this, it is possible to cope with input voltage values having different quantization levels.

  Note that any combination of the above-described constituent elements, and those in which the constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to the present invention, in an analog-to-digital converter including an AD conversion portion shared in time division, a sufficient comparison period for AD conversion processing can be ensured even with respect to a change in operation timing of other components. Can do.

  First, the basic concept of the present invention will be described. FIG. 1 is a partial circuit diagram for explaining the basic concept of the AD converter of the present invention. The input analog signal Vin is input to the first amplifier circuit 11 and the AD conversion circuit 12 when the first switch SW1 is off. The input analog signal Vin is input to the subtraction circuit 14 and the AD conversion circuit 12 via the first switch SW1 when the first switch SW1 is on.

  The first amplifier circuit 11 samples and holds the input analog signal Vin and outputs it to the subtraction circuit 14. The amplification factor of the first amplifier circuit 11 is 1 and functions as a sample hold circuit. The AD conversion circuit 12 converts an input analog signal into a digital value and extracts a predetermined bit. The extracted digital value is input to an encoder (not shown) and the DA conversion circuit 13. The DA conversion circuit 13 converts the digital value converted by the AD conversion circuit 12 into an analog value. The subtraction circuit 14 subtracts the output analog signal of the DA conversion circuit 13 from the analog signal input via the first switch SW1 and the first amplifier circuit 11. The second amplifying circuit 15 amplifies the output analog signal of the subtracting circuit 14 by a factor of 2 and outputs it to the subsequent stage. The amplification factor of the second amplifier circuit 15 is arbitrary and is not limited to twice.

  The AD conversion circuit 12 is provided with a plurality of voltage comparison elements corresponding to the number of bits to be converted. An input analog signal Vin and a reference voltage Vref are selectively input to the voltage comparison element. The voltage comparison element outputs a digital value depending on whether the input analog signal Vin is larger or smaller than the reference voltage Vref. The input switching circuit 16 controls the input timing of the input analog signal Vin and the reference voltage Vref to the voltage comparison element.

  As described above, both the input analog signal Vin via the first switch SW1 and the output analog signal of the first amplifier circuit 11 can be input to the subtracting circuit 14 of the AD converter of FIG. The operational amplifier constituting the first amplifier circuit 11 has an output voltage range, and the range becomes narrower when the voltage is lowered. If the first amplifier circuit 11 is not inserted, a signal error does not occur, but if it is removed as it is, there is a possibility that the timing will be out of order. Such a circuit can be used in a prototype or the like, and the characteristics of both the case where the first amplifier circuit 11 is provided and the case where the first amplifier circuit 11 is not provided can be compared. More specifically, it can be used for test mode and application switching.

  Next, an operation example of the AD converter in FIG. 1 will be described. FIG. 2 is a timing chart showing an operation example of the AD converter of FIG. In the figure, the first switch SW1 is turned on / off every cycle of the clock signal CLK. When the first switch SW1 is off, the input analog signal Vin is sampled by the first amplifier circuit 11 and the AD conversion circuit 12 during a period when the clock signal CLK is high. The input switching circuit 16 selects the input analog signal Vin and inputs it to the AD conversion circuit 12. The first amplifier circuit 11 and the AD conversion circuit 12 are in an auto-zero state while the clock signal CLK is high. There is no output during the auto-zero period. The second amplifier circuit 15 amplifies and outputs the previous clock signal. During this period, the reference voltage Vref is input.

  Next, when the first switch SW1 is off, the first amplifier circuit 11 samples and holds the input analog signal Vin during a period in which the clock signal CLK is low. The AD conversion circuit 12 compares the input analog signal Vin with the reference voltage Vref and performs a conversion operation. The input switching circuit 16 selects the reference voltage Vref and inputs it to the AD conversion circuit 12. The second amplifier circuit 15 is in an auto-zero state, and the output of the first amplifier circuit 11 is input.

  When the first switch SW1 is on, the first amplifier circuit 11 is off. During the period when the clock signal CLK is high, the AD conversion circuit 12 is in the auto-zero state, and the reference voltage Vref is input. The input switching circuit 16 selects the reference voltage Vref and inputs it to the AD conversion circuit 12. The second amplifier circuit 15 amplifies and outputs the signal input to the previous clock. During this period, the reference voltage Vref is input.

  Next, when the first switch SW1 is on, the input analog signal Vin is sampled by the second amplifier circuit 15 and the AD conversion circuit 12 during a period when the clock signal CLK is low. The AD conversion circuit 12 compares the reference voltage Vref with the input analog signal Vin and performs a conversion operation. The input switching circuit 16 selects the input analog signal Vin and inputs it to the AD conversion circuit 12. The second amplifier circuit 15 is in an auto-zero state, and the input analog signal Vin is input.

  FIG. 3 is a timing chart showing a comparative operation example of the AD converter of FIG. In the figure, the first switch SW1 is turned on / off every cycle of the clock signal CLK. The operation when the first switch SW1 is OFF is the same as described in FIG.

  When the first switch SW1 is on, the first amplifier circuit 11 is off. While the clock signal CLK is high, the second amplifier circuit 15 amplifies and outputs the signal input to the previous clock. During this period, the reference voltage Vref is input. The AD conversion circuit 12 is in an auto-zero state, and the input analog signal Vin is input. The input switching circuit 16 selects the input analog signal Vin and inputs it to the AD conversion circuit 12.

  Next, when the first switch SW1 is on, the input analog signal Vin must be input to the second amplifier circuit 15 while the clock signal CLK is low. Accordingly, the input analog signal Vin is also input to the AD conversion circuit 12 during this period. However, the reference voltage Vref must be input to the AD conversion circuit 12 during this period. Therefore, the input switching circuit 16 switches from the input analog signal Vin to the reference voltage Vref during this period. The AD conversion circuit 12 performs a comparison operation after the input is switched to the reference voltage Vref. The input analog signal Vin is not input to the second amplifier circuit 15 from the period when the reference voltage Vref is switched, and the second amplifier circuit 15 enters a non-operation period.

  In this comparative operation example, the input switching circuit 16 inputs only the input analog signal Vin when the AD conversion circuit 12 is in the auto-zero state. On the other hand, in the operation example of FIG. 2, the input switching circuit 16 may receive the input analog signal Vin or the reference voltage Vref when the AD conversion circuit 12 is in the auto-zero state. Due to this difference, the second amplifier circuit 15 in FIG. 3 is wasted during the period T1 in the figure. Further, the AD conversion circuit 12 has a correspondingly shorter comparison time. Furthermore, a plurality of clock signals having different periods are required. On the other hand, the first amplifier circuit 11, the second amplifier circuit 15, and the AD converter circuit 12 of FIG. 2 perform a regular operation on the first switch SW1. Therefore, it is easy to create a clock.

  Next, an example of an AD converter using the basic configuration described above will be described. FIG. 4 is a diagram illustrating a configuration of the AD converter according to the embodiment. The present embodiment is an example of a pipeline type AD converter including a two-stage cyclic AD conversion portion. In the first stage, the upper 4 bits (D9 to D6) and the least significant 2 bits (D1 to D0) are converted, and in the second stage, the intermediate bits (D5 to D2) are converted.

  In this AD converter, the input analog signal Vin is input to the first AD conversion circuit 22 via the first switch SW21. The first AD conversion circuit 22 converts the input analog signal into a digital value of a maximum of 4 bits and outputs it to an encoder (not shown) and the first DA conversion circuit 23. The first DA converter circuit 23 converts the maximum 4-bit digital value output from the first AD converter circuit 22 into an analog signal.

  The first subtraction circuit 24 subtracts the output analog value of the first DA conversion circuit 23 from the input analog value. The second amplification circuit 25 amplifies the output of the first subtraction circuit 24 and outputs the amplified output to the third amplification circuit 27 and the second AD conversion circuit 28 via the third switch SW23. The amplification factor is twice. The first subtracting circuit 24 and the second amplifying circuit 25 may be an integrated subtracting amplifier circuit. The input switching circuit 26 switches between two types of analog signals and two types of reference voltages Vref, and supplies them to the voltage comparison elements constituting the first AD conversion circuit 22. The ratio between the reference voltage Vref1 supplied when the first AD converter circuit 22 converts the upper 4 bits (D9 to D6) and the reference voltage Vref2 supplied when the lowest 2 bits (D1 to D0) are converted is as follows: 2: 1. That is, when the least significant 2 bits (D1 to D0) are converted, the ½ reference voltage Vref2 is supplied.

  The second AD conversion circuit 28 converts the input analog signal into a digital value of a maximum of 2 bits and outputs it to an encoder (not shown) and the second DA conversion circuit 29. The second DA conversion circuit 29 converts the maximum 2-bit digital value output from the second AD conversion circuit 28 into an analog signal.

  The third amplifier circuit 27 amplifies the input analog signal by a factor of 2 and outputs it to the second subtraction circuit 30. The second subtraction circuit 30 subtracts the analog value output from the second DA conversion circuit 29 from the analog value output from the third amplification circuit 27. Here, the analog value output from the second DA conversion circuit 29 is substantially doubled corresponding to the amplification factor of the third amplification circuit 27. The fourth amplifier circuit 31 amplifies the output of the second subtracting circuit 30, and the first AD converter circuit via the fourth switch SW24 and the third amplifier circuit 27 and the second AD converter circuit 28, or the third switch SW23. Feedback to 22. The amplification factor is twice. The second subtracting circuit 30 and the third amplifying circuit 27 may be an integrated subtracting amplifier circuit.

  The switching control of the input switching circuit 26 will be described. FIG. 5 is a diagram illustrating a first configuration example of the input switching circuit 26. The input switching circuit 26 inputs four types of voltages to the VIN input terminal and the VREF terminal of the first AD conversion circuit 22. The input switching circuit 26 includes four switches SW61 to SW64. The Vin1 switch SW61 is a switch for turning on and off the input of the input analog signal Vin1 to the VIN terminal, and includes a NOT circuit 61b and is a switch whose logic is inverted. The Vin2 switch SW62 is a switch for turning on / off the input of the input analog signal Vin2 to the VIN terminal, and includes a NOT circuit 62b, and is a switch whose logic is inverted. The Vref1 switch SW63 is a switch for turning on and off the input of the first reference voltage Vref1 to the VREF terminal, and includes a NOT circuit 63b and is a switch that inverts the logic. The Vref2 switch SW64 is a switch for turning on and off the input of the second reference voltage Vref2 to the VREF terminal, and includes a NOT circuit 64b and is a switch that inverts the logic.

  A NAND circuit 61 is connected to the switch SW61 for Vin1. A NAND circuit 62 is connected to the Vin2 switch SW62, and a NOT circuit 62c is connected to a terminal to which the signal A of the NAND circuit 62 is input. A NAND circuit 63 is connected to the Vref1 switch SW63, and a NOT circuit 63c is connected to a terminal to which the signal B of the NAND circuit 63 is input. A NAND circuit 64 is connected to the Vref2 switch SW64, and NOT circuits 64c and d are connected to both terminals of the NAND circuit 64.

  FIG. 6 is a diagram illustrating a control signal of the first configuration example of the input switching circuit 26. When the signal A is high and the signal B is high, only the Vin1 switch SW61 is turned on, and the input analog signal Vin1 is input to the VIN terminal. When the signal A is high and the signal B is low, only the Vref1 switch SW63 is turned on, and the first reference voltage Vref1 is input to the VREF terminal. When the signal A is low and the signal B is low, only the Vref2 switch SW64 is turned on, and the second reference voltage Vref2 is input to the VREF terminal. When the signal A is low and the signal B is high, only the Vin2 switch SW62 is turned on, and the input analog signal Vin2 is input to the VIN terminal. The input switching circuit 26 inputs four types of voltages to the first AD conversion circuit 22 in this order.

  Next, another switching control of the input switching circuit 26 will be described. In this example, the reference voltage Vref is one type. If the amplification factor of the fourth amplifier circuit 31 is set to 4 times, the same reference voltage Vref can be used when converting the upper 4 bits (D9 to D6) and the lowest 2 bits (D1 to D0). . FIG. 7 is a diagram illustrating a second configuration example of the input switching circuit 26. The input switching circuit 26 inputs three types of voltages to the VIN input terminal and the VREF terminal of the first AD conversion circuit 22. The input switching circuit 26 includes three switches SW61 to SW63. The Vin1 switch SW61 is a switch for turning on and off the input of the input analog signal Vin1 to the VIN terminal, and includes a NOT circuit 61b and is a switch whose logic is inverted. The Vin2 switch SW62 is a switch for turning on and off the input of the input analog signal Vin2 to the VIN terminal, and includes a NOT circuit 62b and is a switch whose logic is inverted. The Vref switch SW63 is a switch for turning on and off the input of the reference voltage Vref to the VREF terminal, and includes a NOT circuit 63b and is a switch that inverts the logic.

  A NAND circuit 61 is connected to the switch SW61 for Vin1. A NAND circuit 62 is connected to the Vin2 switch SW62, and a NOT circuit 62c is connected to a terminal to which the signal B of the NAND circuit 62 is input. An inverted output of the signal B is input to the Vref switch SW63.

  FIG. 8 is a diagram illustrating a control signal of the second configuration example of the input switching circuit 26. When the signal A is high and the signal B is high, only the Vin1 switch SW61 is turned on, and the input analog signal Vin1 is input to the VIN terminal. When the signal A is high and the signal B is low, and when the signal A is low and the signal B is low, only the Vref switch SW63 is turned on, and the reference voltage Vref is input to the VREF terminal. When the signal A is low and the signal B is high, only the Vin2 switch SW62 is turned on, and the input analog signal Vin2 is input to the VIN terminal. The input switching circuit 26 inputs three kinds of voltages to the first AD conversion circuit 22 in this order.

  Next, the operation of the AD converter in this embodiment will be described. FIG. 9 is a timing chart illustrating the operation of the AD converter according to the embodiment. The upper three signal waveforms in the figure show the first clock signal CLK1, the second clock signal CLK2, and the switch signal CLKS. The frequency of the second clock signal CLK2 is twice the frequency of the first clock signal CLK1.

  The input analog signal Vin is sampled when the first clock signal CLK1 rises from low to high. The second amplifier circuit 25 samples and holds the input analog signal Vin when the first clock signal CLK1 and the second clock signal CLK2 are high, and performs an auto-zero operation for a half clock period. It is amplified for one period from the time when the next second clock signal CLK2 is high. During this period, the output analog signal of the first subtraction circuit 24 is input.

  The first AD converter circuit 22 performs an auto-zero operation when the second clock signal CLK2 is high, and performs a conversion operation when the second clock signal CLK2 is low. When the second clock signal CLK2 is at the first low level, the digital values D9 to D6 are output, and at the next low level, the digital values D1 to D0 are output. The input switching circuit 26 inputs the input analog signal Vin (represented as Vin1 in the figure) when the second clock signal CLK2 is first high, inputs the reference voltage Vref when the second clock signal CLK2 is next low, The reference voltage Vref is sometimes input, and the output analog signal (represented as Vin2 in the figure) of the fourth amplifier circuit 31 is input at the next low. If two reference voltages Vref1 and Vref2 are used, they are input in the order of Vin1 → Vref1 → Vref2 → Vin2. This is repeated thereafter. The first DA conversion circuit 23 performs a conversion operation when the first clock signal CLK1 is low and outputs the converted signal to the first subtraction circuit 24, and becomes indefinite when the first clock signal CLK1 is high.

  The third amplifier circuit 27 amplifies the input analog signal when the second clock signal CLK2 is high, and performs an auto-zero operation when the second clock signal CLK2 is low. The fourth amplifier circuit 31 amplifies the output of the second subtraction circuit 30 when the second clock signal CLK2 is low, and performs an auto-zero operation when the second clock signal CLK2 is high. The second AD converter circuit 28 performs a conversion operation when the second clock signal CLK2 is high, and performs an auto-zero operation when the second clock signal CLK2 is low. The second DA conversion circuit 29 performs a conversion operation when the second clock signal CLK2 is low, and becomes indefinite when the second clock signal CLK2 is high.

  The first switch SW21 is turned on when the first clock signal CLK1 is low, and is turned off when the first clock signal CLK1 is high. The second switch SW22 is turned on when the first clock signal CLK1 is high, and is turned off when the first clock signal CLK1 is low. The third switch SW23 is turned on when the switch signal CLKS is high, and is turned off when the switch signal CLKS is low. The fourth switch SW24 is turned on when the switch signal CLKS is low and turned off when the switch signal CLKS is high.

  On the other hand, when the input switching circuit 26 inputs a voltage to the first AD converter circuit 22 in the order of Vin1 → Vref1 → Vin2 → Vref2, the first AD converter circuit 22 is similar to that shown in the comparative operation example of FIG. The comparison period of the voltage comparison element which constitutes is shortened. Also, the clock signal becomes complicated.

  By such pipeline processing, the AD converter as a whole can output a 10-bit digital value once per cycle with reference to the first clock signal CLK1.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications can be made to combinations of each component and each processing process. Those skilled in the art will appreciate that such modifications are also within the scope of the present invention.

  The parameters such as the number of conversion bits of the AD conversion circuit and the distribution thereof, the amplification factor of the amplification circuit, and the like described in the above embodiment are merely examples, and other numerical values may be adopted for these parameters in the modification.

  The present invention is applicable not only to pipeline-type and cyclic-type AD converters, but also to AD-converted parts shared in a time-sharing manner, as well as pipeline-type and cyclic-type AD converters. It can be applied to the AD conversion part shared by time division.

It is a partial circuit diagram for demonstrating the basic concept of the AD converter of this invention. 2 is a timing chart illustrating an operation example of the AD converter in FIG. 1. 2 is a timing chart showing an example of comparison operation of the AD converter of FIG. 1. It is a figure which shows the structure of the AD converter in embodiment. It is a figure which shows the 1st structural example of an input switching circuit. It is a figure which shows the control signal of the 1st structural example of an input switching circuit. It is a figure which shows the 2nd structural example of an input switching circuit. It is a figure which shows the control signal of the 2nd structural example of an input switching circuit. It is a timing chart which shows operation of an AD converter in an embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 1st amplifier circuit, 12 AD converter circuit, 13 DA converter circuit, 14 Subtraction circuit, 15, 25 2nd amplifier circuit, 16, 26 Input switching circuit, 22 1st AD converter circuit, 23 1st DA converter circuit, 24 1st Subtraction circuit, 27 3rd amplification circuit, 28 2nd AD conversion circuit, 29 2nd DA conversion circuit, 30 2nd subtraction circuit, 31 4th amplification circuit, 61a-64a NAND circuit, 61b-64b NOT circuit, 62c-64c NOT circuit 64d NOT circuit, SW1, SW2, SW21 to SW24, SW61 to SW64 switch.

Claims (5)

An AD conversion circuit for converting an input analog signal into a digital value having a predetermined number of bits;
An input switching circuit for switching and inputting the voltage value of the analog signal and a predetermined reference voltage value to the voltage comparison element constituting the AD conversion circuit;
The analog-to-digital converter, wherein the input switching circuit switches between a voltage value of the analog signal and the reference voltage value according to an operation timing of another component. An AD conversion circuit for converting an input analog signal into a digital value having a predetermined number of bits;
A DA conversion circuit for converting the output of the AD conversion circuit into an analog signal;
A subtracting circuit for subtracting the output analog signal of the DA converter circuit from the input analog signal;
An amplification circuit for amplifying the output of the subtraction circuit;
An input switching circuit for switching and inputting the voltage value of the input analog signal and a predetermined reference voltage value to the voltage comparison element constituting the AD conversion circuit;
The analog-to-digital converter, wherein the input switching circuit switches between a voltage value of the analog signal and the reference voltage value according to an operation timing of the amplifier circuit. A sample-and-hold circuit that is provided between an input and the subtracting circuit and samples and holds the input analog signal;
A switch for switching a path between the input and the subtraction circuit to either the direct path or the sample-and-hold path;
3. The analog digital signal according to claim 2, wherein the input switching circuit inputs the reference voltage value first and the voltage value of the input analog signal later while the switch directly selects a path. converter. Pipeline type or cyclic type analog-digital converter,
An AD conversion circuit for converting an input analog signal into a digital value having a predetermined number of bits;
A DA conversion circuit for converting the output of the AD conversion circuit into an analog signal;
A subtracting circuit for subtracting the output analog signal of the DA converter circuit from the input analog signal;
An amplification circuit for amplifying the output of the subtraction circuit;
An input switching circuit for switching and inputting a voltage value of the input analog signal and a predetermined reference voltage value to the voltage comparison element constituting the AD conversion circuit;
The input switching circuit switches between the voltage value of the input signal from the previous stage, the voltage value of the input signal fed back from the subsequent stage, and the reference voltage value according to the operation timing of the amplifier circuit. vessel.   The input switching circuit amplifies the voltage value of the input signal from the previous stage, the first reference voltage value for the input signal, the voltage value of the input signal fed back from the subsequent stage, and the second reference voltage value for the input signal. 5. The analog-digital converter according to claim 4, wherein switching is performed according to the operation timing of the circuit.

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