JP2005215246A - Plasma display panel driving method and device, and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel driving method with which reduction of power consumption and estimation of the power consumption, etc. can be realized by the data driver and/or the common driver of the plasma display panel, and plasma display panel driving device and the plasma display device. <P>SOLUTION: Emission ratio (turn-on ratio) in a subfield converted by a subfield conversion circuit 12 is calculated and a specification signal for specifying a writing selection method or a deletion selection method is outputted to the subfield conversion circuit 12 and a driving signal control circuit 15. The subfield conversion circuit 12 supplies a video data signal corresponding to the supplied specification signal to the data driver 14. The driving signal control circuit 15 supplies a scan driver control signal determined according to the supplied specification signal to a scan driver 16 and supplies a common driver control signal to the common driver 18. Thus, all display cells of the plasma display panel 100 are made into a non-emission or an emission state corresponding to the video signal, the scan driver control signal and the common driver control signal and after that, a display cell corresponding to the video data signal is emitted or quenched by the data driver 14. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method and apparatus for driving a plasma display panel, and a plasma display device, and more particularly to a method and apparatus for driving a plasma display panel that can achieve reduction of power consumption in a data driver and / or a common driver of the plasma display panel. The present invention relates to a device and a plasma display device.

A plasma display panel (hereinafter also referred to as PDP) is generally a display panel having a number of features such as being thin and capable of relatively large screen display, wide viewing angle, and high response speed. .
Because of these features, in recent years it has been used as a flat display, as a wall-mounted television, public display board, or the like.
Conventionally, a subfield method has been adopted for driving a plasma display panel. This subfield method is used as one means for expressing the gradation of a displayed image.
That is, in this subfield method, a field of one screen is divided into a plurality of subfields, and the number of sustain discharges in the sustain period of each subfield is set corresponding to the pixels of one screen according to the gradation to be expressed. By generating a set number of sustain discharges in the sustain period, each pixel in one screen is displayed with a desired gradation.

Hereinafter, a time division gradation display method of the plasma display panel using the subfield method will be described with reference to FIGS.
First, a writing selection method in time division gradation display will be described.
FIG. 15 is a view schematically showing the plasma display panel 100 and a driving device 110 thereof.
The plasma display panel 100 shown in FIG. 15 includes a predetermined number of scanning electrodes 102 _i (i = 1, 2,..., M) arranged in the horizontal direction and the same number of common electrodes 104 that are parallel to the scanning electrodes 102 _{i. i} and data electrodes 106 _j (j = 1, 2,..., N) orthogonal to each scanning electrode 102 _i and each common electrode 104 _i , that is, arranged in the vertical direction. Yes.
One display cell 108 _ij is formed at each intersection of the scanning electrode 102 _i and the common electrode 104 _i and the data electrode 106 _j .

As shown in FIG. 16, the driving device 110 of the plasma display panel 100 connects a subfield conversion circuit 112 to which a video signal of one field is supplied and an input to the output of the subfield conversion circuit 102, and outputs each of the outputs. A data driver 114 connected to each corresponding data electrode 106 _j , a scan driver 116 connected to each scan electrode 102 _i , and a common driver 118 connected in common to each common electrode 104 _i The driving signal control circuit 120 is connected to the scanning driver 116 and the common driver 118.

The subfield conversion circuit 112 is a circuit that converts a video signal of one field into a predetermined number of, for example, video data signals of each subfield of eight subfields, for example, 0 or 1 of a binary signal.
The data driver 114 is a driver that receives the video data signal of each subfield and sequentially applies the data pulse corresponding to each video data signal to the corresponding data electrode 106 _j ((3) in FIG. 17).

  The drive signal control circuit 120 has a scan driver control signal (hereinafter referred to as a scan driver control signal for address selection) for causing address selection in any subfield (the number of discharges within the sustain period for each subfield is determined). A common driver control signal (hereinafter referred to as a common driver control signal for writing selection) (hereinafter referred to as a common driver control signal for writing selection) for supplying write selection to the scan driver 116 and generating write selection (within a sustain period for each subfield). (Including a discharge number signal indicating the number of discharges) to the common driver 118.

The scan driver 116 _i receives the scan driver control signal for address selection, applies the preliminary discharge pulse and the preliminary discharge erase pulse to all the scan electrodes 102 _i in the reset period, and responds to the scan pulse line-sequentially in the address period. scanning electrodes is applied to 102 _i, is a driver for applying all of the number of sustain pulses shown in discharge frequency signal in the scan driver control signal for the write select the scanning electrodes 102 _i, and a sustain erase pulse in the sustain period to ((2-1), (2-2),..., (2-M) in FIG. 17).
The common driver 118 receives a common driver control signal for address selection, applies a preliminary discharge pulse to all the common drivers 104 _i in the reset period, and applies a predetermined voltage (high level) to all the common electrodes 104 _i in the address period. And a sustain pulse of the number indicated by the discharge frequency signal in the scan driver control signal for address selection and a voltage for erasure are applied to all the common electrodes 104 _i in the sustain period. ((1) in FIG. 4).

A case where the plasma display panel 100 is driven in the write selection type address drive mode (hereinafter also referred to as a write selection method) by the drive device 110 having the above configuration will be described.
Each field of the video signal input to the PDP device is sequentially supplied to the subfield conversion circuit 112. The subfield conversion circuit 112 converts the video data signal into a predetermined number, for example, eight subfields.

The drive signal control circuit 120 converts the video signal input to the PDP device into a predetermined number of subfields for each field by the subfield conversion circuit 112, and for each subfield during the reset period, the plasma display panel All the display cells are set in a non-light emitting state, and the address selection method is set in advance so that the display cells corresponding to the pixels in one field emit light during the address period.
The drive signal control circuit 120 supplies a scanning driver control signal for writing selection to the scanning driver 116, and supplies a common driver control signal for writing selection to the common driver 118.

As shown in (2-i) of FIG. 17, the scan driver 116 applies the preliminary discharge pulse and the preliminary discharge erase pulse to all the scan electrodes 102 _i at the same time. As shown in (1), a preliminary discharge pulse is applied to all the common electrodes 104 _i simultaneously.
By applying these pulses, all the display cells 108 _ij of the plasma display panel 100 are placed in a non-light emitting state.

Each of the video data signals in each subfield converted by the subfield conversion circuit 112 (signal corresponding to the pixel data signal of the field) is line-sequentially and data driver 114 within the address period for each subfield. Supplied to.
The data driver 114 sequentially applies the data pulse corresponding to each video data signal to the corresponding data electrode 106 _j ((3) in FIG. 17).

As described above, the data driver 114 is synchronized with the application during the application period of the scan pulse in synchronization with the scan driver 116 sequentially applying the scan pulse to each of the scan electrodes 102 _i in a line sequential manner. since each corresponding data pulses in the scan line is sequentially applied to each of the data electrodes 106 _j, the scan pulse is applied, and the display cell 108 _ij which data pulse is applied is light emission (lighting).

When the operation proceeds to the sustain period, the scan driver 116 applies to all the scan electrodes 102 _i , and the common driver 118 applies to all the sustain electrodes 104 _i for each subfield. In addition, the sustain pulses having the opposite polarity are alternately applied, and the light emission is repeated the number of times in the sustain period of the subfield.
In the sustain period, the scan driver 114 applies a sustain erase pulse to all the scan electrodes 102 _i at the same time to extinguish (turn off) the continued light emission.

Next, an erase selection type address driving mode (hereinafter also referred to as an erase selection method) in time division gradation display will be described.
Also in the erasing selection method, the configuration of the plasma display panel 100 is the same as that in the writing selection method (FIG. 15), but the driving device 110A is the same except for the points described below.

  As shown in FIG. 18, the drive device 110A includes a subfield conversion circuit 112A, a data driver 114, a scan driver 116A, a common driver 18A, and a drive signal control circuit 120A. The difference is in the subfield conversion circuit 112A, the scan driver 116A, the common driver 18A, and the drive signal control circuit 120A.

The sub-field conversion circuit 112A converts the video signal of one field into a format obtained by inverting each of the video data signals constituting the sub-field for every predetermined number, for example, eight sub-fields, and outputs it to the data driver 114. Circuit.
In any subfield, the drive signal control circuit 120A has a scan driver control signal (scan driver control signal for erasure selection) for causing erasure selection (the erasure selection scan driver control signal indicates the number of discharges). A common driver control signal (common driver control signal for erasure selection) (a common driver control signal for erasure selection is discharged to supply erasure selection) to the scan driver 116A. (Including a discharge frequency signal indicating the frequency) to the common driver 118A.

Scanning driver 116A applies a preliminary discharge pulse to all the scan electrodes 102 _i in the reset period to receive the scan driver control signal for selectively erased, the corresponding scanning electrodes 102 _i scan pulse line-sequentially in the address period This is a driver that applies a sustain pulse of the number determined by the discharge frequency signal in the scan driver control signal for erasure selection and a sustain erase pulse to all the scan electrodes 102 _i in the sustain period ((2- 1), (2-2), ..., (2-M)).

Common driver 118A, the common driver control signal received by the applying a preliminary discharge pulse to all the common drivers 104 _i in the reset period, all the common electrodes 104 _i to a predetermined voltage in an address period (low level for erasing selected voltage) is applied to, are all of the common electrode 104 _i to a common driver number of sustain pulses determined by the number of discharge times signal in the control signal for selectively erased and driver for applying a voltage for erasure, in the sustain period ( FIG. 19 (1)).

A case where the plasma display panel 100 is driven by the erasure selection method by the driving device 110A having the above configuration will be described.
Each field of the video signal input to the PDP device is sequentially supplied to the subfield conversion circuit 112A. The subfield conversion circuit A converts the video signal of each field into a video data signal in an inverted format every predetermined number, for example, 8 subfields.

The drive signal control circuit 120A converts the video signal input to the PDP device into a predetermined number of subfields for each field by the subfield conversion circuit 112, and for each subfield in the reset period of the subfield, It is preset in an erasure selection method in which all the display cells of the plasma display panel 100 are made to emit light, and only the display cells to be lit in one field are left lit in the address period, and the non-light emitting target display cells are erased. Yes.
In the setting state, the drive signal control circuit 120A supplies a scan driver control signal for erasure selection to the scan driver 116A for each subfield, and supplies a common driver control signal for erasure selection to the common driver 118A.

The scanning driver 116A, as shown in (2-i) in FIG. 19, to all the scanning electrodes 102 _i and at the same time applying a preliminary discharge pulse in unison, the common driver 118, as shown in (1) in FIG. 19 In addition, a preliminary discharge pulse is applied to all the common electrodes 104 _i simultaneously.
By applying these pulses, all the display cells 108 _ij of the plasma display panel 100 are placed in a light emitting state.

Each of the inverted video data signals (signals obtained by inverting the video data signals corresponding to the pixel data signals in the field) in each subfield converted by the subfield conversion circuit 112A is within the address period for each subfield. The data is supplied to the data driver 114 in a line sequential manner.
The data driver 114 sequentially applies each video data signal in the inverted format as a data pulse to the corresponding data electrode 106 _j ((3) in FIG. 19).

As described above, the scanning driver 116A is a line-sequential, and a scanning pulse in synchronism with sequentially applied to the scanning electrodes 102 _i, the data driver 114, during the application period of the scan pulse, corresponding in the scan line Since each data pulse to be applied is sequentially applied to each data electrode 106 _j , the display cell 108 _ij to which the scanning pulse is applied and the video data pulse is applied is not extinguished (turned off).
The operation in the sustain period is the same as that in the case of writing selection.

Techniques related to the write selection method and the erase selection method described above are described in Patent Document 1 (Japanese Patent Laid-Open No. 2003-216096) and Patent Document 2 (Japanese Patent Laid-Open No. 2003-208122). A related technique is described in Patent Document 3 (Japanese Patent Laid-Open No. 2001-222252).
Japanese Patent Laid-Open No. 2003-216096 JP 2003-208122 A JP 2001-222252 A

As described above, in the driving of the conventional plasma display panel by the subfield method, either the writing selection method or the erasing selection method is fixedly set at the initial stage of the driving.
In any subfield, all display cells of the plasma display panel 100 are addressed by the address method once set.

Such a fixed address method causes the following problems.
For example, in a state in which the write selection method is initially set, when a field having pixels for which all display cells of the plasma display panel 100 are to be emitted is input to the PDP device, the addresses of all display cells of the plasma display panel 100 are Discharge occurs.
In the address discharge, as is well known, a displacement current and a discharge current flow through the data driver 114. The displacement current is larger than the discharge current.
The flow of these currents to the data driver 114 causes an increase in power consumption in the PDP device.
Such a problem also applies to the erase selection address method.

  The present invention has been made in view of the above circumstances, and a plasma display panel driving method capable of realizing reduction of power consumption, estimation of power consumption, and the like of a data driver and / or a common driver of a plasma display panel, and its An object is to provide a device and a plasma display device.

In order to solve the above-mentioned problem, the invention according to claim 1 relates to a driving method of a plasma display panel, and relates to a plasma display panel corresponding to the video pixel signal based on a video pixel signal of a field or a part of the field. The number of lighting display cells or non-lighting display cells is counted, and either one of the write selection type address driving mode and the erase selection type address driving mode is selected based on the result of the counting.
A part of the field is a plurality of scanning lines in the field. Count the number of lit display cells or non-lit display cells by converting each video pixel signal in the field into a logic signal that instructs the display cell of the plasma display panel to emit or not emit light for each field. The logic signal is counted and performed. The field may be each of the fields obtained by converting the field of the video signal into subfields.

  According to a second aspect of the present invention, there is provided the plasma display panel driving method according to the first aspect, wherein the erase-selective address driving mode is selected when the number of the lit display cells exceeds a predetermined number. It is said.

  According to a third aspect of the present invention, there is provided the plasma display panel driving method according to the first aspect, wherein the write-selective address driving mode is selected when the number of the lit display cells is less than a predetermined number. .

  According to a fourth aspect of the present invention, there is provided the method for driving a plasma display panel according to the first aspect, wherein when the number of the non-lighting display cells exceeds a predetermined number, the write selective address driving mode is selected. It is a feature.

  According to a fifth aspect of the invention, there is provided the plasma display panel driving method according to the first aspect, wherein the erasing selection type address driving mode is selected when the number of non-lighting display cells is less than a predetermined number. Yes.

  According to a sixth aspect of the present invention, there is provided a driving method of a plasma display panel, wherein the video pixel signal is displayed for each successive first scanning line and second scanning line in a field including a plurality of video pixel signals. The number of displacements between the converted display pixel signals is counted, and the write selective address driving mode or the erasure selective address driving mode is selected based on the result of the counting.

  According to a seventh aspect of the present invention, in the plasma display panel driving method according to the sixth aspect, when the number of displacements exceeds a predetermined number, the display cell row corresponding to the first scanning line is selected. An address driving mode different from the address driving mode that has been performed is selected for the display cell row corresponding to the second scanning line.

  The invention according to claim 8 relates to a method for driving a plasma display panel, converts a video pixel signal of a video signal into a display pixel signal, and counts the display pixel signal to be converted or the number of displacements between the display pixel signals. In addition, the number of times of change between the write selective address drive mode and the erase selective address drive mode is counted, and the address drive mode is selected based on the count result.

  A ninth aspect of the invention relates to the plasma display panel driving method according to the eighth aspect of the invention, wherein the display pixel signal count is a count of the number of the display pixel signals causing a discharge current to flow through the data driver. It is characterized by.

  According to a tenth aspect of the present invention, there is provided the plasma display panel driving method according to the eighth aspect, wherein the number of displacements between the display pixel signals is the number of the display pixel signals causing the data driver to flow a displacement current. It is characterized by counting.

  An eleventh aspect of the present invention relates to the driving method of the plasma display panel according to the eighth aspect, wherein the number of the display pixel signals for causing a discharge current or a displacement current to flow to the data driver is counted, and the common driver is counted. The address drive mode is selected by counting the number of changes between the address drive modes in which a displacement current is passed.

  According to a twelfth aspect of the present invention, there is provided a plasma display panel driving apparatus, a conversion circuit for converting a video pixel signal of a video signal into a display pixel signal for each field, a plasma display panel, and a lighting instruction by the display pixel signal. Count the number of all or part of the display cells in the plasma display panel or the number of non-lighted display cells, and select the write selective address drive mode or erase selective address drive mode based on the result of the counting And a drive control circuit for driving the plasma display panel in an address driving mode selected by the subfield arithmetic circuit.

  According to a thirteenth aspect of the present invention, there is provided the plasma display panel driving apparatus according to the twelfth aspect, wherein the subfield arithmetic circuit is configured to perform the erasure selective address driving mode when the number of lighting display cells exceeds a predetermined number. It is characterized by selecting.

  According to a fourteenth aspect of the present invention, there is provided the plasma display panel driving device according to the twelfth aspect, wherein the subfield arithmetic circuit selects the write selective address driving mode when the number of lighting display cells is less than a predetermined number. It is characterized by doing.

  According to a fifteenth aspect of the present invention, there is provided the plasma display panel driving apparatus according to the twelfth aspect, wherein the subfield arithmetic circuit is configured to perform the write selective address driving when the number of non-lighting display cells exceeds a predetermined number. It is characterized by selecting a mode.

  According to a sixteenth aspect of the present invention, there is provided the plasma display panel driving apparatus according to the twelfth aspect, wherein the subfield arithmetic circuit sets the erase selection type address driving mode when the number of non-lighting display cells is less than a predetermined number. It is characterized by selection.

  According to a seventeenth aspect of the present invention, there is provided a driving device for a plasma display panel, a conversion circuit for converting a video pixel signal of a video signal into a display image signal for each field, a plasma display panel, and a first continuous in the field. A subfield arithmetic circuit that counts the number of displacements between the display pixel signals for each scanning line and second scanning line, and selects a write selective address driving mode or an erasing selective address driving mode based on the result of the counting; And a drive control circuit for driving the plasma display panel according to the address drive mode selected by the subfield arithmetic circuit.

  The invention according to claim 18 relates to the driving device of the plasma display panel according to claim 17, wherein the subfield arithmetic circuit corresponds to the first scanning line when the number of displacements exceeds a predetermined number. The address driving mode different from the address driving mode selected for the display cell row of the plasma display panel is selected for the display cell row corresponding to the second scan line. Yes.

  According to a nineteenth aspect of the present invention, there is provided a plasma display panel driving apparatus, a conversion circuit for converting a video pixel signal of a video signal into a display image signal, a plasma display panel, and the display pixel signal converted by the conversion circuit. Alternatively, the number of displacements between the display pixel signals is counted, the number of changes between the write selective address driving mode and the erasing selective address driving mode is counted, and the address driving mode is selected based on the result of the counting And a drive control circuit for driving the plasma display panel in the address driving mode selected by the subfield arithmetic circuit.

  According to a twentieth aspect of the invention, there is provided the plasma display panel driving apparatus according to the nineteenth aspect, wherein the display pixel signal count in the subfield arithmetic circuit causes the data driver of the plasma display panel to flow a discharge current. It is characterized by counting the number of display pixel signals.

  According to a twenty-first aspect of the present invention, there is provided the plasma display panel driving apparatus according to the nineteenth aspect, wherein the number of displacements between the display pixel signals in the subfield arithmetic circuit is determined by a displacement current applied to the data driver of the plasma display panel. It is a count of the number of the display pixel signals that cause the current to flow.

  According to a twenty-second aspect of the invention, there is provided the plasma display panel driving apparatus according to the nineteenth aspect, wherein the subfield arithmetic circuit is configured to output the display pixel signal for causing a data driver of the plasma display panel to flow a discharge current or a displacement current. The address driving mode is selected by counting the number and counting the number of changes between the address driving modes for causing a displacement current to flow through the common driver of the plasma display panel.

  The invention described in claim 23 relates to the driving device of the plasma display panel according to claim 19, 20, 21 or 22, wherein the common driver of the plasma display panel individually drives the common electrode of the plasma display panel. It is characterized by.

  The invention described in claim 24 relates to a plasma display device, an input section for receiving an input video signal, a plasma display panel drive device according to any one of claims 12 to 22, and And an interface device that converts the video signal received by the input unit into a digital signal required by the driving device and supplies the digital signal to the driving device.

  Since the configuration is such that the change in voltage for driving the scan electrode and / or the common electrode of the plasma display panel is reduced, the power consumption of the scan driver and / or the common driver can be reduced. Simplification and shortening of the repair of the plasma display device can be achieved by modularizing the components that can achieve the above-described effects in the plasma display device.

  A configuration is adopted in which the scan driver and / or the common driver for driving the scan electrode and / or the common electrode of the plasma display panel is driven by either the write selection method or the erase selection method selected based on the light emission rate of the screen or the like. Can be realized.

FIG. 1 is a diagram showing an electrical configuration of a plasma display panel driving apparatus according to Embodiment 1 of the present invention, and FIG. 2 is a diagram showing a driving situation when there are more light emitting cells than non-light emitting cells in the driving apparatus; FIG. 3 is a diagram showing a driving situation when the number of light emitting cells of the driving device is smaller than that of non-light emitting cells.
A plasma display panel driving apparatus 10 according to this embodiment relates to an apparatus capable of reducing power consumption of a data driver in driving a plasma display panel. As shown in FIG. 1, a subfield conversion circuit 12 and a subfield arithmetic circuit are provided. 13, a data driver 14, a drive signal control circuit 15, a scan driver 16, and a common driver 18.

The subfield conversion circuit 12 converts an input video signal of one field into a predetermined number, for example, eight subfields, and for each subfield, a video data signal (for the pixel) for each pixel in the subfield. A circuit that outputs a logical value designating lighting (hereinafter also referred to as light emission) or non-lighting (hereinafter also referred to as non-light emission), for example, binary 1 or 0, to the data driver 14 in a non-inverted or inverted format It is.
Whether the video data signal is output in the non-inverted format or the inverted format depends on the address drive mode designation signal supplied from the subfield arithmetic circuit 22 (either the write selective address drive mode or the erase selective address drive mode). , Ie, one of the write selection designation signal and the erase selection designation signal (described later). For example, when it is a write selection designation signal, it outputs a non-inverted video data signal, and when it is an erase selection designation signal, it outputs an inverted video data signal.

  For each subfield converted by the subfield conversion circuit 12, the subfield arithmetic circuit 13 obtains the number of pixel signals to be emitted, and is the ratio between the number of pixel signals and the total number of pixel signals. The light emission rate is calculated, and when the light emission rate (lighting rate) is, for example, 50% or less, a write selection designation signal is output, and when the light emission rate exceeds, for example, 50%, an erase selection designation signal is output. Circuit.

  In response to the write selection designation signal or the erase selection designation signal supplied from the subfield arithmetic circuit 13, the drive signal control circuit 15 applies the scan driver control signal for write selection described in the section “Background Art” to the scan driver 16. And a common driver control signal for selecting the write is supplied to the common driver 18 or a scan driver control signal for selecting the erase is supplied to the scan driver 16 and a common driver control signal for selecting the erase is selected. Is supplied to the common driver 18.

The scan driver 16 uses each scan electrode 102 in the drive mode described in the section “Background Art” in accordance with the scan driver control signal for write selection or the scan driver control signal for selection of erase supplied from the drive signal control circuit 15. _i is driven.
Similarly, the common driver 18 uses each of the driving modes described in the section “Background Art” according to the common driver control signal for programming selection or the common driver control signal for erasing selection supplied from the driving signal control circuit 15. The common electrode 104 _i is driven.
Further, the data driver 14 supplies a data pulse corresponding to the non-inverted video data signal or the inverted video data signal supplied from the subfield conversion circuit 12 to each data electrode 106 _i .

Next, the operation of this embodiment will be described with reference to FIGS.
When one field video signal is input to the subfield conversion circuit 12, the one field video signal is converted into a predetermined number of subfield video data signals. The video data signal for each subfield is supplied to the subfield arithmetic circuit 13.
The subfield arithmetic circuit 13 obtains the number of pixel signals to be emitted in the field based on the supplied video data signal, and calculates a light emission rate that is a ratio between the number of pixel signals and the total number of pixel signals. .
For example, the write selection designation signal is output from the subfield arithmetic circuit 13 when the light emission rate is 50% or less, and the erase selection specification signal is output when the light emission rate exceeds 50%, for example.
The write selection designation signal is output as a logical value “1”, for example, and the erase selection designation signal is output as a logical value “0”, for example.

First, a case where the light emission rate calculated by the subfield arithmetic circuit 13 is 50% or less and a write selection designation signal is output from the subfield arithmetic circuit 13 will be described.
The write selection designation signal output from the subfield arithmetic circuit 13 is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.
The subfield conversion circuit 13 outputs the video data signal of each subfield to the data driver 14 in a non-inverted format in response to the write selection designation signal. The drive signal control circuit 15 outputs a scanning driver control signal for writing selection to the scanning driver 16 and outputs a common driver control signal for writing selection to the common driver 18.

The scan driver 16 that has received the scan driver control signal for address selection simultaneously applies the pre-discharge pulse and pre-discharge erase to all the scan electrodes 102 _i (FIG. 15) as described in the section “Background Art”. At the same time as applying a pulse ((2-i) in FIG. 17), the common driver 18 applies a preliminary discharge pulse to all the common electrodes 104 _i (FIG. 15) all at once ((1) in FIG. 17).
By applying these pulses, all the display cells 108 _ij (FIG. 15) of the plasma display panel 100 are placed in a non-light emitting state.

Each of the video data signals in each subfield converted by the subfield conversion circuit 12 (signal corresponding to the pixel data signal of the field) is line-sequentially and data driver 14 within the address period for each subfield. Supplied to.
The data driver 14 sequentially applies the data pulse corresponding to each video data signal to the corresponding data electrode 106 _j (FIG. 15) ((3) of FIG. 17).

As described above, in synchronization with the scanning driver 16 sequentially applying the scanning pulse to each scanning electrode 102 _i in a line sequential manner, the data driver 14 responds in the scanning line during the scanning pulse application period. Since each data pulse to be applied is sequentially applied to each data electrode 106 _j , the scan cell is applied, and the display cell 108 _ij to which the data pulse is applied emits light.

When the operation proceeds to the sustain period, the scan driver 16 applies to all the scan electrodes 102 _i , and the common driver 18 applies to all the sustain electrodes 104 _i for each subfield. In addition, the sustain pulses having the opposite polarity are alternately applied, and the light emission is repeated the number of times in the sustain period of the subfield.
In the sustain period, the scan driver 16 applies the sustain erase pulse to all the scan electrodes 102 _i at the same time to extinguish (turn off) the continued light emission.

As described above, when the write selection method (one address method) is selected, the number of discharge currents flowing from the data driver 14 to the data electrode 104 _i in the address period is determined as the erase selection, as will be described in detail later. It is reduced compared to the case where a method (another address method) is selected. The number of displacement currents flowing from the data driver 14 to the data electrode 104 _i is not different depending on the address method.

Next, a case where the light emission rate calculated by the subfield arithmetic circuit 13 exceeds 50% and an erasure selection designation signal is output from the subfield arithmetic circuit 13 will be described.
The erasure selection designation signal output from the subfield arithmetic circuit 13 is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.
The subfield conversion circuit 13 outputs the video data signal of each subfield to the data driver 14 in an inverted format in response to the erase selection designation signal. Further, the drive signal control circuit 15 outputs a scan driver control signal for erasure selection to the scan driver 16 and outputs a common driver control signal for erasure selection to the common driver 18.

The scan driver 16 that has received the scan driver control signal for erasure selection applies the preliminary discharge pulse to all the scan electrodes 102 _i at the same time as described in [Background Art] ((2- i)) At the same time, the common driver 18 applies a preliminary discharge pulse to all the common electrodes 104 _i simultaneously ((1) in FIG. 19).
By applying these pulses, all the display cells 108 _ij of the plasma display panel 100 are placed in a light emitting state.

Each of the inverted video data signals in each subfield converted by the subfield conversion circuit 12 (a signal obtained by inverting the video data signal corresponding to the pixel data signal in the field) is within the address period for each subfield. Then, the data is supplied to the data driver 14 in a line sequential manner.
The data driver 14 sequentially applies the data pulse corresponding to each video data signal in the inverted format to the corresponding data electrode 106 _j ((3) in FIG. 19).

As described above, in synchronization with the scanning driver 16 sequentially applying the scanning pulse to each scanning electrode 102 _i in a line sequential manner, the data driver 14 responds in the scanning line during the scanning pulse application period. Since the inverted data pulses are sequentially applied to the data electrodes 106 _j , the scanning pulse is applied and the display cell 108 _ij to which the inverted data pulse is applied is extinguished (extinguished).
However, the display cell 108 _op (display cell corresponding to the pixel signal) to which the inverted data pulse is not applied remains illuminated.

When the operation proceeds to the sustain period, the scan driver 16 applies to all the scan electrodes 102 _i , and the common driver 18 applies to all the sustain electrodes 104 _i for each subfield. In addition, by alternately applying sustain pulses of reverse polarity, light emission of the display cell 108 _op is repeated the above number of times in the sustain period of the subfield.
In the sustain period, the scan driver 16 applies the sustain erase pulse to all the scan electrodes 102 _i at the same time to quench the continued light emission.

As described above, when the erase selection method is selected, as will be described in detail later, the number of discharge currents flowing from the data driver 14 to the data electrode 104 _i in the address period is selected as the address selection method. Compared to Also in this case, there is no difference depending on the address method in the number of displacement currents flowing from the data driver 14 to the data electrode 104 _i .

The effect of selecting the address method described above will be specifically described.
As shown in FIG. 2, when there are many display cells to be lit in a subfield, if the addressing method of the subfield is the address selection method, the number of times the discharge current flows to the data driver 14 increases. ((2-1), (2-2) in FIG. 2), when the erasing selection method is selected under the condition of the same number of display cells, (2-3) and (2-4) in FIG. As shown, the number of times the discharge current flows to the data driver 14 is reduced.

As shown in FIG. 3, when the number of display cells to be emitted in the subfield is small, the number of times the discharge current flows to the data driver 14 increases if the addressing method of the subfield is the erasure selection method. ((3-3), (3-4) in FIG. 3), when the write selection method is selected under the condition of the same number of display cells, (3-1), (3-2) in FIG. ), The number of times the discharge current flows to the data driver 14 is reduced.
Therefore, although the number of times the displacement current flows to the data driver 14 is not changed, the number of times the discharge current flows from the data driver is reduced, so that the power consumption of the data driver is reduced.

  Thus, according to the configuration of this embodiment, each field of the video signal is converted into a predetermined number of subfields, and the plasma display panel addressing method is selected according to the light emission rate in the subfields. It is possible to reduce the number of display cells to be selected in the address period, that is, to reduce the number of discharges in the display cells, and to reduce the power consumption of the data driver that causes the display cells to discharge.

  4 is a diagram showing an electrical configuration of a plasma display panel driving apparatus according to a second embodiment of the present invention, FIG. 5 is a flowchart for selecting an addressing method in the driving apparatus, and FIG. 6 is an addressing method in the driving apparatus. FIG. 7 is a drive waveform diagram in the case of driving by the address method selected in the drive device.

  The configuration of this embodiment is greatly different from that of the first embodiment in that one field of the video signal is converted into a predetermined number of subfields, and a scan line of that subfield (also referred to as a display cell row corresponding to the scanline). For each pixel signal of the immediately preceding scan line, a logical value of a logical signal designating light emission or non-emission (hereinafter, a logical value of a logical signal designating light emission or non-emission for the pixel signal is referred to as a pixel logical value). The first mismatch number (also referred to as the displacement number) between the logical values of the corresponding pixels on the subsequent scanning line, the logical value of each pixel on the previous scanning line, and the logical value of the corresponding pixel on the subsequent scanning line are inverted. A second mismatch number (also referred to as a displacement number) between the inverted logic values (hereinafter referred to as the inverted logic values of the pixels) is obtained, and according to the magnitude relationship between the first mismatch number and the second mismatch number. Continuous scan line add Scan method is that was to determine the.

  The immediately preceding scan line is a scan line corresponding to a display cell row (immediately before display cell row) immediately before driving the plasma display panel 100, and the immediately following scan line is a scan line immediately preceding the immediately preceding scan line (immediately preceding). A scanning line corresponding to a display cell row (continuous display cell row) immediately following the display cell row). The immediately preceding scan line (first scan line) and the continuous scan line (second scan line) form a pair of scan lines in the field (converted subfield) of the video signal.

In other words, the driving device 10A of this embodiment directly converts the logical value of each pixel of the immediately preceding scanning line for each pair of scanning lines in the subfield (screen) for each subfield converted by the subfield conversion circuit. Correspondence between the first mismatch number A [N] (value calculated by the expression (1)) between the logical values of the corresponding pixels in the subsequent scanning line, the logical value of each pixel in the immediately preceding scanning line, and the continuous scanning line A second mismatch number B [N] (a value calculated by the expression (2)) between the inverted logical values of the pixels to be obtained is obtained, and when the first mismatch number A [N] is small, The same address method as the address method is selected for the continuous display cell row, and when the second mismatch number B [N] is small, the address method different from the address method of the previous display cell row is selected for the continuous display cell row. A subfield arithmetic circuit 13A is provided to Address method designation signal output from the field calculation circuit 13A, i.e., constituted by one of the write selection designation signal or erase selection designation signal to be supplied to the sub-field conversion circuit 12 and the driving signal control circuit 15.
A [N] = D [N-1] & D [N] (1)
However, A [N] is the number of mismatches, D [N−1] is the logical value of each pixel of the immediately preceding scanning line, & is the exclusive OR, and D [N] is the logical value of each pixel of the continuous scanning line. is there.
B [N] = D [N−1] & ˜D [N] (2)
Where B [N] is the number of mismatches, D [N−1] is the logical value of each pixel in the previous scan line, & is an exclusive OR, and ~ D [N] is the inverted logic of each pixel in the continuous scan line. Value.

For each subfield converted by the subfield conversion circuit 12, the subfield arithmetic circuit 13A applies either the write selection designation signal or the erase selection designation signal for the first scan line of the subfield, that is, the initial address method. Is set to an address method designating signal for designating and the address method designating signal is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.
Specifically, for example, the initial address method is selected so as to reduce the discharge current flowing through the data driver 14 in the subfield.

Further, the subfield arithmetic circuit 13A calculates the number of mismatches A [N] between the logical value of the pixel of the immediately preceding scanning line and the logical value of the corresponding pixel of the subsequent scanning line from the second scanning line, and A method of calculating the number of mismatches B [N] between the logical value of the pixel on the scanning line and the inverted logical value of the corresponding pixel on the successive scanning line, and when the number of mismatches A [N] is small, A designation signal is output, and when the mismatch number B [N] is small, an address method designation signal for designating an address method different from the address method designation signal of the immediately preceding display cell row is outputted.
Since the configuration of this embodiment other than this configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIGS.
The driving of the plasma display panel 100 in this embodiment is the same as that in the first embodiment except for the points described below. In the following, the differences will be mainly described.
When a video signal is input to the subfield conversion circuit 12 for each field, the video signal for the one field is converted into a video data signal for a predetermined number of subfields. The supply to the field arithmetic circuit 13A is the same as in the first embodiment.

  For each subfield converted by the subfield conversion circuit 12, the subfield arithmetic circuit 13A performs either the write selection method or the erase selection method for the display cell row corresponding to the first scan line of the subfield, for example, write A selection method is set (S1 in FIG. 5), and the method designation signal is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.

Upon receiving the write selection designation signal, the subfield conversion circuit 12 supplies the video data signal of the first scanning line of the subfield to the data driver 14 in a non-inverted form, while the drive signal control circuit 15 A scan driver control signal is supplied to the scan driver 16, and a common driver control signal for writing selection is supplied to the common driver 18.
Accordingly, each display cell of the first display cell row is extinguished in the reset period of the subfield, each display cell to be lit is emitted in the address period, and the light emission state is maintained for the sustain period, And it is quenched.

  Prior to entering the same drive for the display cell rows corresponding to the second and subsequent scan lines, it is determined whether or not the drive of the display cell row corresponding to the last scan line has been completed (S2 in FIG. 5). ). If the determination is affirmative (Y in S2 in FIG. 5), the processing for the field is terminated. If the above is negative (N in S2 in FIG. 5), the same processing is performed for the second and subsequent scanning lines.

  In the processing of the second and subsequent scan lines, the subfield arithmetic circuit 13A looks at whether or not the logical value of each pixel of the first scan line is the same as the logical value of the corresponding pixel of the second scan line, for example, The exclusive OR is calculated to calculate the mismatch number A [N] (S3 in FIG. 5), and the logical value of the pixel of the first scan line and the inversion of the corresponding pixel of the second scan line (drive row) Looking at whether or not the logical values are the same, for example, an exclusive logical sum is calculated to calculate the mismatch number B [N] (S4 in FIG. 5).

  Then, the subfield arithmetic circuit 13A outputs an address method designation signal, for example, a write selection designation signal for the immediately preceding display cell row (in this case, the first display cell row) when the calculated number of mismatches A [N] is small. (S5, S6 in FIG. 5), when the number of mismatches B [N] is small, an erase selection designation signal which is an address method designation signal different from that of the immediately preceding display cell row is output (S5, S7 in FIG. 5), and the output address The method designation signal is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.

For example, FIG. 6 shows a part of the plasma display panel 100, in which a display cell to emit light is indicated by a circle at the intersection of the scan electrode and the data electrode, and a non-emission display cell is indicated by the scan electrode and the data electrode. In the example shown without a circle at the intersection, the logical value of each pixel of the scanning line corresponding to the scanning electrode 102 ₁ (first display cell row) and the logical value of the corresponding pixel of the scanning line corresponding to the continuous display cell row Is the number at which the exclusive OR (A in FIG. 6) is “1”, that is, the number of mismatches described above is 3, and the logic of each pixel of the scan line corresponding to the scan electrode 102 ₁ (first display cell row) The number in which the exclusive OR (B in FIG. 6) of the value and the inverted logical value of the corresponding pixel in the scanning line corresponding to the continuous display cell row is “1”, that is, the number of mismatches described above is 2.
Therefore, the write selection designation signal is output from the subfield arithmetic circuit 13A to the scan electrode 102 ₂ (second display cell row).

For the second display cell row, the operations of the subfield conversion circuit 12 and the drive signal control circuit 15 when the write selection designation signal is output from the subfield arithmetic circuit 13A are the same as those described for the first display cell row. It is.
Accordingly, each display cell of the second display cell row is extinguished during the reset period of its subfield, and each display cell to be lit is lit during the address period, and the light emission is similar to the first display cell row. The state lasts for the maintenance period and is quenched.

Contrary to the above, when the erase selection designation signal is output from the subfield arithmetic circuit 13A for the second display cell row, unlike the case of the write selection designation signal, the subfield conversion circuit 12 The video signal signal of the second scanning line is supplied to the data driver 14 in an inverted format, while the drive signal control circuit 15 supplies the scanning driver control signal for erasing selection to the scanning driver 16 and also for erasing selection. A common driver control signal is supplied to the common driver 18.
Accordingly, the second display cell each display cell in the row is kept the subfield preliminary discharge erasing pulse in the reset period is emitted without being applied to the scanning electrodes 102 ₂ (in FIG. 7 (2-2)) In the address period, each of the display cells to be lit is left lit while each display cell other than the lit target is extinguished. The light emission state of the display cell that is emitting light is maintained for the sustain period and is extinguished (turned off).

  For any of the third and subsequent display cell rows, the above-described calculation is performed between the previous scan line and the continuous scan line (drive row), and the address method designation signal corresponding to the calculation result is the subfield calculation. The same driving as described above is performed for the continuous display cell row output from the circuit 13A.

  Thus, according to the configuration of this embodiment, the number of inconsistencies between the logical value of each pixel of the immediately preceding scan line and the logical value of the corresponding pixel of the immediately succeeding scan line, and the logical value of each pixel of the immediately preceding scan line are Depending on the number of inconsistencies with the inversion logic value of the corresponding pixel in the continuous scan line, the address method of the continuous display cell row is determined to be the same as or different from the address method of the immediately preceding display cell row. Therefore, the number of discharge currents flowing from the data driver to the data electrode in the address period is the same, but the current flowing from the data driver to the data electrode in the immediately preceding display cell row continues to flow in the continuous display cell row. The number of currents to be increased can be increased, that is, the number of times the displacement current flows to the data electrode can be reduced, and the power consumption of the data driver can be reduced.

FIG. 8 is a diagram showing an electrical configuration of a plasma display panel driving apparatus according to Embodiment 3 of the present invention, and FIG. 9 is a driving waveform diagram when driving by the addressing method selected in the driving apparatus. .
The configuration of this embodiment differs greatly from that of the second embodiment in consideration of the power consumption of the common driver that increases when the address method (address drive mode) is changed to reduce the power consumption of the data driver. The address method is selected.

The power consumption of the common driver increases due to the change of the address method. The change of the address method requires changing the voltage that must be applied from the common driver to the common electrode. This is because a displacement current flows from the common electrode to the common electrode.
Therefore, the increase in power consumption in the common driver is a function of the number of address method changes.

  In other words, the subfield arithmetic circuit 13B of the driving device 10B of this embodiment, for each subfield converted by the subfield conversion circuit 12, sets the logical value of each pixel of the immediately preceding scanning line and the corresponding pixel of the continuous scanning line. Calculate the number of discrepancies between logical values. Then, the subfield arithmetic circuit 13B selects an address method different from the address method selected for the display cell row corresponding to the immediately preceding scan line for which the number of mismatches has been calculated, for the display cell row corresponding to the continuous scan line. If the amount of reduction is greater than the amount of increase in power consumption per display cell row in the common driver, it is selected for the display cell row corresponding to the previous scan line. An address method different from the address method used is selected for the display cell row corresponding to the continuous scanning line, and the address method designation signal is output to the subfield conversion circuit 12 and the drive signal control circuit 15.

  However, if the amount of reduction in power consumption in the data driver is smaller than the amount of increase in power consumption per display cell row in the common driver, the subfield arithmetic circuit 13B performs the display cell row corresponding to the continuous scan line. The address method selected for the display cell row corresponding to the immediately preceding scan line is selected, and the address method designation signal is output to the subfield conversion circuit 12 and the drive signal control circuit 15.

For each subfield converted by the subfield conversion circuit 12, the subfield arithmetic circuit 13B applies a write selection designation signal or an erase selection designation signal to the display cell row corresponding to the first scan line of the subfield. Initially set to either one, the address method designation signal is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.
Also in this embodiment, as in the first and second embodiments, the initial address method is specifically selected so as to reduce the discharge current flowing through the data driver 14 in the subfield, for example.
Since the configuration of this embodiment other than this configuration is the same as that of the second embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIGS.
The driving of the plasma display panel 100 in this embodiment is the same as that in the second embodiment except for the points described below. In the following, the differences will be mainly described.
When the video signal is input to the subfield conversion circuit 12 for each field, the video signal for the one field is converted into video data signals for a predetermined number of subfields, and the pixels of the video data signal for each subfield are converted. The logic value is supplied to the subfield arithmetic circuit 13B as in the second embodiment.

The subfield arithmetic circuit 13B calculates the number of discrepancies (displacement number) between the logical value of each pixel in the immediately preceding scanning line and the logical value of the corresponding pixel in the subsequent scanning line for every scanning line.
Then, the subfield arithmetic circuit 13B uses an address method different from the address method selected for the display cell row corresponding to the immediately preceding scan line for which the number of mismatches has been calculated for the display cell row corresponding to the continuous scan line. When selected, the power consumption of the data driver is reduced. However, if the reduction amount is larger than the increase in power consumption per display cell row in the common driver, the display cell row corresponding to the immediately preceding scan line is used. An address method different from the selected address method is selected for the display cell row corresponding to the continuous scanning line, and the address method designation signal is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.

Conversely, if the reduction amount is smaller than the increase in power consumption per display cell row in the common driver, the subfield arithmetic circuit 13B selects the address method selected for the display cell row corresponding to the immediately preceding scan line. The display cell row corresponding to the continuous scanning line is selected and its address method designation signal is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.
In any case, for example, the above reduction amount may be calculated in consideration of B [N] described in the second embodiment in the above A [N].

For each subfield converted by the subfield conversion circuit 12, the subfield arithmetic circuit 13B uses a write selection designation signal or erase selection as an address method designation signal for the display cell row corresponding to the first scan line of the subfield. Initially set to one of the specified signals.
The address method designation signal is supplied from the subfield arithmetic circuit 13B to the subfield conversion circuit 12 and the drive signal control circuit 15.

  When the subfield conversion circuit 12 receives the address method designation signal, the video data signal of the scan line is supplied to the address method supplied to any of the scan lines sequentially from the first scan line of the subfield to be driven. The drive signal control circuit 15 supplies the scan driver control signal corresponding to the supplied address method specifying signal to the scan driver 16 and supplies it to the data driver 14 in a signal format corresponding to the specified signal. A common driver control signal is supplied to the common driver 18.

  Therefore, any display cell in the display cell row corresponding to any scan line of the plasma display panel 100 is turned off or emits light during the reset period of the subfield, as in the second embodiment. Each of the display cells emits light, or each of the display cells to be lighted remains light-emitted, and each of the other display cells is quenched.

A specific example of the selection of the address method in the subfield arithmetic circuit 13B will be described with reference to FIG.
FIG. 9 shows a case where the size of the plasma display panel is 10 × 10.
When the number of inconsistencies (displacement number) between the display cell rows from the display cell row 1 to the display cell row 10 is calculated in the subfield arithmetic circuit 13B, each of the displacement numbers of all the display cell rows is displayed at the bottom of FIG. As shown, it is assumed that they are 8, 3, 9, 6, 6, 8, 10, 5, 1.

  The power consumption of the data driver 14 when the data driver 14 applies a displacement current to one display cell is 3.5 mW, and the common driver 18 when the common driver 18 applies a displacement current to each common electrode. Assume that the power consumption per display cell row is 20 mW. The power consumption per display cell row is, for example, a value per display cell row when the power consumption consumed by the common driver 18 is 200 mW when the address method is changed for each display cell row.

As described above, for the first display cell row 1, for example, the write selection method is selected as the address method, and the number of mismatches between the display cell row 1 and the display cell row 2 is eight.
If the addressing method for the display cell row 2 is the same as that of the display cell row 1, the number of display cells in the display cell row 2 to which the data driver 14 must supply the displacement current is 8, but the display cell row 2 When the erase selection method is selected, the number of display cells in the display cell row 2 to which the data driver 14 must supply the displacement current is reduced to two.

Therefore, the reduction amount of power consumption in the data driver 14 is 21 mW, which is larger than the increase amount of power consumption 20 mW in the common driver 18, so that the subfield arithmetic circuit 13 B uses an erase selection method different from the address method for the display cell row 1. And an erase selection designation signal is supplied to the subfield conversion circuit 12 and the drive signal control circuit 15.
Similarly, the address method of display cell row 2, display cell row 4, display cell row 7 and display cell row 8 is changed, but display cell row 3, display cell row 5, display cell row 6, display cell row 9 and the address method of the display cell row 10 remain the address method designation signal of the immediately preceding display cell row and are not changed.

  Thus, according to the configuration of this embodiment, in addition to the change between the display cell rows of the voltage applied from the data driver to the data electrode (supply of displacement current), the voltage supplied from the common driver to the common electrode Display cell row addressing method taking into account changes between display cell rows (supply of displacement current), that is, taking into account the reduction in power consumption in the data driver and the increase in power consumption in the common driver Therefore, according to the determined address method, the effect of reducing the power consumption in the data driver 14 can be prevented from being canceled by the increase in the power consumption in the common driver.

10 is a diagram showing an electrical configuration of a plasma display panel driving apparatus according to Embodiment 4 of the present invention, and FIG. 11 is a diagram showing a configuration of common electrodes of the driving apparatus and a common driver for driving the common electrodes. 12 is a drive waveform diagram when the drive device is driven by the write selection method, and FIG. 13 is a drive waveform diagram when the drive device is driven by the erase selection method.
The configuration of this embodiment is greatly different from that of the second embodiment in that the operation rate of the common driver in the second embodiment is reduced.

That is, the driving device 10C of this embodiment, the common driver 18C shown in FIG. 10, as shown in FIG. 11, and the respective common electrode 104 _i of the plasma display panel 100 have to be driven separately.
Since the configuration of this embodiment other than this configuration is the same as that of the second embodiment, the same components are denoted by the same reference numerals, and the description thereof is omitted.

Next, the operation of this embodiment will be described with reference to FIGS.
The driving of the plasma display panel 100 in this embodiment is the same as that in the second embodiment except for the points described below. In the following, the differences will be mainly described.
When a video signal is input to the subfield conversion circuit 12 for each field, the video signal for that field is converted into a video data signal for a predetermined number of subfields, and each pixel of the video data signal for each subfield. Is supplied to the subfield arithmetic circuit 13A as in the second embodiment.

The method of supplying the address method designation signal from the subfield arithmetic circuit 13A to the subfield conversion circuit 12 and the drive signal control circuit 15 is the same as in the second embodiment.
The video data signal corresponding to the address method designating signal supplied by the subfield conversion circuit 12 is supplied to the data driver 14 and the scan driver control signal corresponding to the address method designating signal supplied by the drive signal control circuit 15. The method of supplying the scanning driver 16 and the method of supplying the common driver control signal corresponding to the address method designation signal to the common driver 18C are the same.

  Accordingly, each display cell in each display cell row is turned off or emits light during the reset period of the subfield, and each display cell to be emitted emits light during the address period, or emits light as in the second embodiment. Each of the target display cells is left illuminated, each of the other display cells is extinguished, and the light emitting state is maintained for the sustain period and is also extinguished.

When the plasma display panel 100 is driven by the addressing method as described above, according to whether the addressing method of the display cell row to be driven is designated by the write selection designation signal or the erase selection designation signal. The voltage applied from the common driver to the common electrode of the display cell row is different.
In the second embodiment, since the voltage is applied to each common electrode 104 _i from one common driver 18, a different voltage is applied to the common electrode even when no voltage change is required in a certain common electrode. Has been done.

However, according to this embodiment, such inconvenience can be avoided.
This will be specifically described as follows.
If the plasma display panel 100 is, for example, 10 × 10, and the addressing method of the plasma display panel 100 is as shown in FIG. 12, the write selection method is selected for the display cell row 1, the display cell row 4 address method, since specified by the write selection designation signal, the voltage of the common electrode 104 ₄ of the display cell row 4, as shown in FIG. 12, during the address period, by setting the high level voltage if good, also the voltage of the common electrode 104 ₃ of the display cell row 3, as shown in FIG. 13, during the address period, it may be set to a low level voltage.
Note that A [N] and B [N] in FIGS. 12 and 13 are the same as those in the second embodiment.

  As described above, according to the configuration of this embodiment, the common driver 18C uses the high-level voltage and the low-level voltage applied to the common electrode by changing the address method as in the common driver 18 of the second embodiment. Therefore, it is not necessary to change between the two and the operation rate of driving each common electrode by the common driver 18C. The power consumption of the PDP driving device 10C is reduced.

FIG. 14 is a diagram showing an electrical configuration of a plasma display display apparatus which is Embodiment 5 of the present invention.
The configuration of this embodiment differs greatly from that of Embodiments 1 to 4 in that the display device equipped with the plasma display panel driving device described in Embodiments 1 to 4 is configured.

  As shown in FIG. 14, the plasma display device 40 of this example is designed to have a module structure. Specifically, the plasma display device 40 includes an analog interface (hereinafter referred to as analog IF) 20 and a PDP module 30. Yes.

  As shown in FIG. 14, the analog IF 20 includes a Y / C separation circuit 21 having a chroma decoder, an A / D conversion circuit 22, a synchronization signal control circuit 23 having a PLL circuit, an image format conversion circuit 24, And an inverse γ (gamma) conversion circuit 25.

Schematically, the analog IF 20 converts the received analog video signal into a digital video signal, and then supplies the digital video signal to the PDP module 30.
This will be described in detail with reference to FIG. 14. The Y / C separation circuit 21 decomposes the analog video signal output from the TV tuner into RGB luminance signals, and the A / D conversion circuit 22 The RGB luminance signals are converted into digital signals.

When the pixel configuration of the PDP module 30 is different from the pixel configuration of the video signal, the image format conversion circuit 24 performs conversion to a required image format.
The digital signal output from the A / D conversion circuit 22 is subjected to inverse γ conversion on the digital video signal in the inverse γ conversion circuit 25. This is because the normal video signal is corrected (γ-converted) in advance according to the characteristics of the CRT, so that the original linear characteristic is given to the digital video signal.
As a result, the PDP can be matched with the fact that the display luminance characteristic with respect to the input signal to the PDP is linearly proportional.
The digital video signal whose linear characteristics are restored in this way is output to the PDP module 30 as an RGB video signal.

  A PLL circuit built in the synchronization signal control circuit 23 generates a sampling clock and a data clock signal using a horizontal synchronization signal supplied simultaneously with the analog video signal, and outputs it to the PDP module 30.

The PDP module 30 includes a digital signal processing / control circuit 31 and a panel unit 32.
The digital signal processing / control circuit 31 includes an input IF signal processing circuit 34, a subfield conversion circuit 12, a subfield arithmetic circuit 13, and a drive signal control circuit 15. The subfield conversion circuit 12, the subfield arithmetic circuit 13, and the drive signal control circuit 15 are the same as those described in the first to fourth embodiments.

The digital signal processing / control circuit 31 performs the above-described interface processing of various signals in the input IF signal processing circuit 34, and then supplies these signal circuits to the subfield conversion circuit 12.
As in the first to fourth embodiments, the subfield conversion circuit 12 converts the input digital video signal into subfields for each field, and the video data signal for each pixel in the converted subfield. Is supplied to the data driver 14 in a non-inverted or inverted format corresponding to the supplied address method designation signal.

As in the first to fourth embodiments, the subfield arithmetic circuit 13 sends an address method designation signal to the subfield conversion circuit 12 and the drive signal control circuit 15 based on the video data signal converted by the subfield conversion circuit 12. It is the circuit which supplies to.
The drive signal control circuit 15 to which the address method designation signal is supplied supplies the scan driver control signal corresponding to the address method designation signal to the scan driver 16 as in the first to fourth embodiments, and the address method. This is a circuit for supplying a common driver control signal corresponding to the designated signal to the common driver 18.

As in the first to fourth embodiments, the common driver 18 is adapted to supply a voltage signal corresponding to the reset period, address period, sustain period, and sustain erase period of the subfield period and corresponding to the supplied common driver control signal. The scan driver 16 sequentially applies to the common electrode 104 _j (FIG. 15). The scan driver 16 corresponds to the reset period, address period, sustain period, and sustain erase period of the subfield period, and corresponds to the supplied scan driver control signal. Are sequentially applied to the scanning electrode 102 _i (FIG. 15). The data driver 14 is a driver that applies a data pulse corresponding to the video data signal to the data electrode 106 _j (FIG. 15) during the reset period.

  In the panel unit 32, the PDP 100 described in FIG. 11 or FIG. 15, the data driver 14 that drives the data electrodes, the scan driver 16 that drives the scan electrodes, and the common driver 18 are arranged on one substrate. The whole is composed.

The PDP 100 is configured to have display cells arranged in, for example, 1365 × 768. In PDP 100, scan driver 16 controls the scan electrode 102 _i, the data driver 14 by controlling the data electrodes, the lighting or non-lighting of a desired display cell of the scanning electrodes 102 _i is controlled, The desired display is made.
The logic power supply supplies logic power to the digital signal processing / control circuit 31 and the panel unit 32. Further, the display power supply supplies a predetermined voltage to the panel unit 32.

Next, the operation of the plasma display device 40 of this embodiment will be schematically described.
The input analog video signal is decomposed into luminance signals of RGB colors by the Y / C separation circuit 21, and the luminance signals of RGB colors are converted into digital signals by the A / D conversion circuit 22, respectively.

When the converted digital signal has a difference between the pixel configuration of the video signal and the pixel configuration of the PDP module 30, the image format conversion circuit 24 performs necessary image format conversion.
The digital signal output in this way is subjected to inverse γ conversion on the digital video signal in the inverse γ conversion circuit 25.
The digital video signal whose linear characteristics are restored in this way is output to the PDP module 30 as an RGB video signal.

  The PLL circuit built in the synchronization signal control circuit 23 generates a sampling clock and a data clock signal using a horizontal synchronization signal supplied simultaneously with the analog video signal, and outputs it to the PDP module 30.

The input IF signal processing circuit 34 of the PDP module 30 performs the above-described interface processing of various signals, and then supplies these signals to the subfield conversion circuit 12.
The subfield conversion circuit 12 converts the input digital video signal into subfields for each field, and converts the video data signal for each pixel in the converted subfield to a corresponding address method designation signal. Supplied to the data driver 14 in an inverted format or inverted format

The subfield arithmetic circuit 13 supplied with the video data signal converted by the subfield conversion circuit 12 supplies an address method designation signal to the subfield conversion circuit 12 and the drive signal control circuit 15 based on the video data signal.
Further, the drive signal control circuit 15 supplied with the address method designation signal supplies the scan driver control signal corresponding to the address method designation signal to the scan driver 16 and also supplies the common driver control signal corresponding to the address method designation signal to the common driver 18. To supply.

The common driver 18 to which the common driver control signal is supplied corresponds to the reset period, the address period, the sustain period, and the sustain erase period of the subfield period, and supplies the voltage signal corresponding to the supplied common driver control signal to the common electrode 104 _j. The scan driver 16 to which the scan driver control signal is supplied in synchronization with the sequential application to the sub-field period corresponds to the reset period, address period, sustain period, and sustain erase period of the subfield period, and the supplied scan driver control A voltage signal corresponding to the signal is sequentially applied to the scan electrode 102 _i .
Then, the data driver 14 sequentially applies data pulses corresponding to the video data signal to the data electrode 106 _j during the reset period.

In the address period in which the PDP 100 is driven in this way, the scan driver 16 applies the scan pulse to the scan electrode 102 _i line-sequentially, and the data driver 14 sequentially applies the data pulse to the data electrode, whereby the display of the PDP 100 is performed. The display cell corresponding to the pixel of the video signal in the cell 108 _ij is turned on or off, and a desired image is displayed on the screen of the PDP 100.

  As described above, according to the configuration of this embodiment, the plasma display panel drive device that reduces the change in the voltage for driving the scan electrode and / or the common electrode of the plasma display panel is provided. Provided is a plasma display device that can reduce power consumption and can also replace a PDP module in the event of a failure of the plasma display device due to the module configuration of the plasma display panel, and can also simplify and shorten the repair. Can do.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration of the present invention is not limited to these embodiments, and the design does not depart from the gist of the present invention. These changes are included in the present invention.
For example, in the selection of either the write selection method or the erase selection method, the number of logical values instructing light emission of pixel signals in the field is the number of logical values instructing non-light emission of pixel signals in the field. When the number of logical values instructing the light emission of the pixel signal in the field is larger than the number of logical values instructing the non-light emission of the pixel signal in the field, the erase selection method is selected. You may comprise.
In the same case, the address method may be selected in the same manner for a part of the field, for example, a plurality of scanning lines, instead of the entire field.

In the third embodiment, the power consumption of the common driver 18 is shown based on the power consumption per display cell row. However, the average power consumed by the common driver 18 for the field of the video signal is shown. The address method may be selected in the same manner as in the third embodiment on the basis of power.
The drive device may be configured with a configuration in which this is combined with the fourth embodiment.
In any of the above cases, when each pixel signal in the field of the video signal other than the subfield method is converted to a logical value designating light emission or non-light emission for the pixel signal, the display cell of the plasma display panel is driven Also, it can be extended and applied.

  Further, when the increase in power consumption in the common driver is considered in the selection of the address method, the video signal of the video signal is converted into the display pixel signal, and the address method is used without using the converted display image signal. If the address method is changed, an increase in power consumption in the common driver may be taken into consideration when changing the address method.

  The method and apparatus for driving a plasma display panel disclosed herein can be used as various display devices such as an information processing device, a portable terminal device, a video camera display device, a television, and the like.

FIG. 1 is a diagram showing an electrical configuration of a plasma display panel driving apparatus according to Embodiment 1 of the present invention. It is a figure which shows the drive condition when there are more light emitting cells of the drive device than a non-light emitting cell. It is a figure which shows the drive condition in case the light emitting cell of the drive device is fewer than a non-light emitting cell. It is a figure which shows the electrical constitution of the drive device of the plasma display panel which is Example 2 of this invention. It is a selection flowchart of the address method in the drive device. It is a figure illustrating the example of selection of the address method in the drive device. It is a drive waveform diagram in the case of being driven by the address method selected in the drive device. It is a figure which shows the electrical constitution of the drive device of the plasma display panel which is Example 3 of this invention. It is a drive waveform diagram in the case of being driven by the address method selected in the drive device. It is a figure which shows the electrical constitution of the drive device of the plasma display panel which is Example 4 of this invention. It is a figure which shows the structure of the common electrode of the drive device, and the common driver which drives this. It is a drive waveform diagram in the case of driving the drive device by write selection. It is a drive waveform diagram in the case of driving the same drive device by erasure selection. It is a figure which shows the electrical constitution of the plasma display display apparatus which is Example 5 of this invention. It is the schematic of the conventional plasma display panel and its drive device. It is the schematic of the electric structure in the case of comprising the conventional drive device by the write selection method. FIG. 17 is a drive waveform diagram of the drive device shown in FIG. 16. It is the schematic of the electrical structure in the case of comprising the conventional drive device by the erasing selection method. FIG. 19 is a drive waveform diagram of the drive device shown in FIG. 18.

Explanation of symbols

10, 10A, 10B, 10C Driving device 12 Subfield conversion circuit (conversion circuit)
13, 13A, 13B Subfield operation circuit 14 Data driver (part of drive control circuit)
15 Drive signal control circuit (part of drive control circuit)
16 Scan driver (part of drive control circuit)
18, 18C, 18C _i common driver (the remainder of the drive control circuit)
20 Analog IF
30 PDP module 40 Plasma display device

Claims (24)

Count the number of lit display cells or non-lit display cells of the plasma display panel corresponding to the video pixel signal based on the video pixel signal of the field or part of the field,
A plasma display panel driving method for selecting one of a write selective address driving mode and an erasing selective address driving mode based on a result of the counting.   2. The method of driving a plasma display panel according to claim 1, wherein when the number of lit display cells exceeds a predetermined number, the erasure selection type address driving mode is selected.   2. The method of driving a plasma display panel according to claim 1, wherein when the number of the lit display cells is less than a predetermined number, the write selection type address driving mode is selected.   2. The method of driving a plasma display panel according to claim 1, wherein when the number of non-lighting display cells exceeds a predetermined number, the write selection type address driving mode is selected.   2. The method of driving a plasma display panel according to claim 1, wherein when the number of non-lighting display cells is less than a predetermined number, the erase selection type address driving mode is selected. Converting the video pixel signal into a display image signal for each successive first scan line and second scan line in a field including a plurality of video pixel signals;
Count the number of displacements between the converted display pixel signals,
A plasma display panel driving method comprising: selecting a write selective address driving mode or an erasing selective address driving mode based on a result of the counting.   When the number of displacements exceeds a predetermined number, an address drive mode different from the address drive mode selected for the display cell row corresponding to the first scan line is associated with the second scan line. 7. The method of driving a plasma display panel according to claim 6, wherein the display cell row to be selected is selected. Convert the video pixel signal of the video signal into a display pixel signal,
Counting the display pixel signals to be converted or the number of displacements between the display pixel signals, and counting the number of changes between the write selective address drive mode and the erase selective address drive mode,
A driving method of a plasma display panel, wherein the address driving mode is selected based on a result of the counting.   9. The method of driving a plasma display panel according to claim 8, wherein the display pixel signal count is a count of the number of display pixel signals causing a discharge current to flow through the data driver.   9. The method of driving a plasma display panel according to claim 8, wherein the display pixel signal count is a count of the number of the display pixel signals causing a displacement current to flow through the data driver.   Counting the number of display pixel signals that cause a discharge current or displacement current to flow to the data driver, and counting the number of changes between the address driving modes that cause displacement current to flow to the common driver. 9. The method of driving a plasma display panel according to claim 8, wherein the method is selected. A conversion circuit that converts a video pixel signal of the video signal into a display pixel signal for each field;
A plasma display panel;
Counting the number of all or part of the display cells in the plasma display panel that are instructed to be turned on by the display pixel signal, or the number of non-lighted display cells, and based on the result of the counting, A subfield arithmetic circuit for selecting an erasure selection type address driving mode;
And a driving control circuit for driving the plasma display panel according to an address driving mode selected by the subfield arithmetic circuit.   13. The apparatus of claim 12, wherein the subfield arithmetic circuit selects the erasure selection type address driving mode when the number of lit display cells exceeds a predetermined number.   13. The plasma display panel driving apparatus according to claim 12, wherein the sub-field arithmetic circuit selects the write selective address driving mode when the number of lighting display cells is less than a predetermined number.   13. The plasma display panel driving apparatus according to claim 12, wherein the subfield arithmetic circuit selects the write-selective address driving mode when the number of non-lighting display cells exceeds a predetermined number.   13. The plasma display panel driving apparatus according to claim 12, wherein the subfield arithmetic circuit selects the erasure selection type address driving mode when the number of non-lighting display cells is less than a predetermined number. A conversion circuit that converts a video pixel signal of the video signal into a display image signal for each field;
A plasma display panel;
The number of displacements between the display pixel signals is counted for each of the first scanning line and the second scanning line that are continuous in the field, and the write selective address driving mode or the erase selective address driving mode is based on the result of the counting. A sub-field arithmetic circuit for selecting
And a driving control circuit for driving the plasma display panel according to an address driving mode selected by the subfield arithmetic circuit.   The subfield arithmetic circuit is different from the address driving mode selected for the display cell row of the plasma display panel corresponding to the first scanning line when the number of displacements exceeds a predetermined number. 18. The apparatus of claim 17, wherein the address driving mode is selected for the display cell row corresponding to the second scan line. A conversion circuit for converting a video pixel signal of the video signal into a display image signal;
A plasma display panel;
The display pixel signal converted by the conversion circuit or the number of displacements between the display pixel signals is counted, and the number of changes between the write selective address driving mode and the erase selective address driving mode is counted, and the counting is performed. A subfield arithmetic circuit that selects the address driving mode based on the result of:
And a drive control circuit for driving the plasma display panel in the address drive mode selected by the subfield arithmetic circuit.   20. The plasma display panel according to claim 19, wherein the count of the display pixel signal in the subfield arithmetic circuit is a count of the number of the display pixel signal that causes a discharge current to flow to a data driver of the plasma display panel. Drive device.   20. The count of the number of displacements between the display pixel signals in the subfield arithmetic circuit is a count of the number of the display pixel signals that cause a displacement current to flow through a data driver of the plasma display panel. Plasma display panel drive device.   The subfield arithmetic circuit counts the number of display pixel signals that cause a discharge current or a displacement current to flow to a data driver of the plasma display panel, and the address that causes a displacement current to flow to a common driver of the plasma display panel 20. The driving apparatus of the plasma display panel according to claim 19, wherein the address driving mode is selected by counting the number of changes between driving modes.   23. The apparatus of claim 19, 20, 21 or 22, wherein the common driver individually drives a common electrode of the plasma display panel. An input unit that receives an input video signal, a plasma display panel driving device according to any one of claims 12 to 22, and a video signal received by the input unit required by the driving device. A plasma display device comprising: an interface device that converts the digital signal to the driving device instead of the digital signal.

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