JP2005208684A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent drop frame due to double buffering as much as possible. <P>SOLUTION: A GCL performs double buffering by two front frame buffers A and B. The GCL reads index data made to correspond to each image data two frame periods before the development timing of each image data, and executes processing to specify the development period for each image data. Then, when a development period to be specified from the index data is longer than a normal development period, the GCL starts development processing in an earlier timing than a timing when the development period is within the normal development period, and ends the development processing by the normal development end timing. Then, when the generation timing of a composite image is reached, the composite image is generated by compounding the front image and the background image, and a variation display device 6 is made to display the composite image. Thus, it is possible to execute image display without generating drop frame. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot machine provided with an image display device that displays images of a plurality of types of identification information that can identify each of them.

  In gaming machines such as pachinko machines, a variety of identification information (hereinafter referred to as special symbols) is displayed on a display device such as a liquid crystal display (LCD), and a predetermined game is displayed based on the display result. There are a number of games that are enhanced by a so-called variable display game that determines whether or not to add value.

  Among the variable display games, there is mainly a game that is performed by using the above-described display device as an image display device (hereinafter referred to as a special game). In the special game, when the game ball passing through the predetermined area is detected, the special symbol is changed and the special symbol is displayed when the special symbol change display is completely stopped. It is a game with a “big hit”. When a “big hit” is made in the special game, a special electric accessory called a big prize opening is activated to open the big prize opening door. As a result, a state in which winning of a game ball is extremely easy for a player is continuously provided for a certain period of time.

  In general, the variable display device displays a character image or the like other than the background image and the special symbol in addition to the special symbol. In that case, still images, sprite images, and movie images are used as these images. A still image is mainly used when displaying a background image. Sprite images are mainly used when displaying moving images in a simple manner, such as characters appearing or changing. The movie image is mainly used when displaying a realistic moving image by a multicolor image typified by a live-action image. A still image, a sprite image, and a movie image may be combined and displayed on a variable display device. For example, the still image portion of the background image, the sprite image of the special symbol that is variably displayed, and the movie image of the special character are combined and displayed on the variable display device.

  Usually, a microcontroller for drawing (for image processing) is mounted on a control board for controlling display of the variable display device. The control board is provided with a ROM for storing various image data and a VRAM (video RAM) for developing an image to be displayed on the variable display device. The microcontroller reads predetermined image data stored in the ROM based on an instruction from the host CPU that performs display control, expands the read image data in a predetermined area of the VRAM, and displays the image on the variable display device. Display. Note that when the image data stored in the ROM is compressed, the microcontroller performs a process of expanding the image data read from the ROM. Such a microcontroller is generally provided with a function of superposing (combining) still images, sprite images, and movie images.

  In the gaming machine described in Patent Document 1, when a drawing processor (drawing microcontroller) performs image data drawing processing, an image data development area (an area on the VRAM in which the image data is developed) is set. Provided in two places, it is configured to perform double buffering in which image data is alternately developed in two development areas.

JP 2002-210139 A

  However, according to the gaming machine described in Patent Document 1, it is double-buffered regardless of the amount of image data, and when it takes a long time to generate an image based on the image data, it was displayed last time. The screen will be displayed again. For this reason, there was a problem that frames were dropped as a result.

  In view of the above, an object of the present invention is to provide a gaming machine that can prevent dropped frames due to double buffering as much as possible.

  A gaming machine according to the present invention is a gaming machine provided with an image display device (for example, a variable display device 6) that displays images of a plurality of types of identification information (for example, special symbols and decorative symbols) that can be distinguished from each other. Image generation means for generating a display image to be displayed on the apparatus (for example, effect control means 301 including image composition means 330), and a display image storage area for storing display image data including an image of identification information (for example, CGROM 83, front image) Storage means 312), a plurality of display image frame buffers (for example, front frame buffers A and B) for reading display image data from the display image storage area by the image generation means and storing the generated display image data, and a plurality of display image frame buffers Of the display image frame buffers, the display image frame buffer for storing display image data generated by the image generation means is cut off. A buffer switching means (e.g., front buffer switching means 328) that is associated with display image data, and a development index that specifies a period until the image generation means generates a display image from the display image data and stores it in the display image frame buffer. A development index data storage area (eg, CGROM 83) for storing data (eg, development period index data), and the image generation means is determined to be Y before the period specified from the development index data (eg, Y in step S911). Specifically, for example, it means that the display image is associated with a timing that is at least a period indicated by the expansion period index data from a normal timing at which a predetermined expansion process is completed. Starting generation of a display image from data (for example, step S912 to step S921) And butterflies.

  The development index data storage area may be provided in the display image storage area (for example, the front image storage means 312).

  The image generation means executes a process (for example, step S912 to step S917) for generating a display execution image in accordance with predetermined control data (for example, front surface control program), and stores a control data storage area (for example, background control data storage). And a development index data storage area may be provided in the control data storage area.

  Before the longest period indicated by the development index data set in advance (for example, when it is determined as Y in step S911. Specifically, for example, a normal timing at which a predetermined development process is completed, for example. This means that it is the timing before the longest period among the periods indicated by all the development period index data.) Based on the target development index data, a display image is generated from the display image data and displayed. It may be configured to specify a period until it is stored in the image frame buffer (for example, step S902. Specifically, for example, a process for specifying a development period based on the development period index data is executed).

  The display image frame buffer includes three frame buffers (for example, front frame buffers A, B, and C shown in FIG. 28), and the image generation means is configured so that the period specified from the development index data does not exceed the normal development period. When the determination is made, the corresponding display image data (for example, the front images A1 to A4 shown in FIG. 28) are alternately transferred to the first or second display image frame buffer (for example, the front frame buffers A and B shown in FIG. 28). And when it is determined that the period specified from the development index data exceeds the normal development period, the corresponding display image data (for example, the front image A5 shown in FIG. 28) is stored in the third display image frame buffer ( For example, the front frame buffer C) shown in FIG. 28 may be developed.

  The development index data is associated with a display image data group (for example, a group of display image data for performing a predetermined display effect by moving image display) that includes a plurality of display image data that are continuously used. May be.

  Even if the display image data group is associated with a variation display mode of the identification information (for example, among the group of display image data, the display image data group that performs a display effect by a predetermined variation display of a special symbol by moving image display). Good. That is, the development index data may be associated with each display image data group (for each variation display effect mode of the special symbol) that performs the display effect by the predetermined variation display of the special symbol by the moving image display.

  The display image data includes character image data for displaying a character image, and the display image data group is a display mode for displaying a character image (for example, a character by moving image display is used among a group of display image data. Display image data group that performs a predetermined display effect). That is, the development index data may be associated with each display image data group that performs a predetermined display effect using a character by moving image display (for each display effect effect mode using a character).

  The image generation means combines the rear image generation means for generating the rear image to be displayed on the image display device (for example, the part that executes steps S912 to S917 in the effect control means) and the front side of the rear image displayed on the image display device. Front image generation means for generating a front image to be generated (for example, a portion of steps S912 and S918 to S919 in the effect control means), and the display image storage area stores back image data for generating a back image A plurality of display image frame buffers including a rear image storage area (for example, background image storage means 310) and a front image storage area (for example, front image storage means 312) for storing front image data for generating a front image. , A plurality of rear image frame buffers (examples) for storing rear image data generated by the rear image generating means 32) and a plurality of front image frame buffers (for example, front frame buffers A and B shown in FIG. 32) for storing front image data generated by the front image generation means. The buffer switching means includes a back buffer switching means (for example, background buffer switching means 323) for switching back image frame buffers for storing back image data generated by the back image generating means among a plurality of back image frame buffers; A front buffer switching means (for example, front buffer switching means 328) for switching a front image frame buffer for storing the front image data generated by the front image generation means among the front image frame buffers of In front of the front frame buffer on the top side of the image data Image synthesis means for synthesizing image data (for example, a part for executing step S921 in the effect control means, eg, image synthesis means) is provided, and the development index data is associated with the back image data and / or the front image data, The image generation means or the front image generation means is specified to generate a display image from the corresponding display image data before the period specified from the development index data associated with the back image data or the front image data. It may be configured to start earlier than the period.

  As described above, according to the first aspect of the present invention, the image data is expanded in advance in the frame buffer based on the expansion index data, so that the image can be displayed without dropping frames.

  According to the second aspect of the present invention, since the development index data can be read at the same time when the image data is read, the control burden can be reduced.

  According to the third aspect of the present invention, it is easy to read the development index data in advance and determine the development period before reading the image data.

  According to the fourth aspect of the present invention, since the development period of the image data can be ensured reliably, it is possible to prevent frame dropping of all the image data.

  According to the fifth aspect of the present invention, since the double buffering and the triple buffering are switched on the basis of the development index data, the image data can be efficiently developed, and the frame loss of the image data can be prevented. Can do.

  In the invention according to claim 6, it is possible to eliminate the necessity of determining the development index data for each image data, and to reduce the control burden.

  In the invention according to claim 7, since the development index data is associated with the variation display mode of the identification information, even if the variation display of the elaborate identification information that requires a long time for development is performed, the image is not dropped. Display can be made.

  In the invention according to claim 8, since the development index data is associated with the reach display mode, even if an elaborate reach display that requires a long period of time for development is performed, it can be displayed without dropping frames.

  According to the ninth aspect of the invention, the image data is expanded in advance in the frame buffer based on the expansion index data, and further, the double image buffering is performed by each of the two image generation means. The degree can be increased.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Note that the gaming machine in the present embodiment is a gaming machine that performs a special game using an image display device (variable display device) such as an LCD, and a card reader (CR: Card Reader) type that lends a ball using a prepaid card. The first type pachinko gaming machine will be described as an example. However, the gaming machine to be applied is not limited to this, and can be applied to a gaming machine such as a slot machine equipped with an LCD, for example. Further, even a ball and ball game machine such as a pachinko game machine has an image display device, for example, a game machine classified as a second type or a third type, a general electric machine, or a pachikon It may be a bullet ball game machine with a probability setting function called. Furthermore, the present invention can be applied not only to a CR-type pachinko gaming machine that lends a ball using a prepaid card (in the future, a value medium including IC coins and the like) but also to a pachinko gaming machine that lends a ball using cash. In other words, any type of gaming machine may be used as long as it has an image display device including an LCD or the like and can perform an effect display corresponding to a special game.

  First, the overall configuration of the CR type first type pachinko gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front. The pachinko gaming machine 1 is roughly divided into a gaming board 2 constituting a gaming board surface and a gaming machine frame 3 to which the gaming board 2 is detachably attached. A game area 4 is formed on the front surface of the game board 2. A handle 5 for launching a hit ball is provided on the lower right side of the front side of the gaming machine 1.

  Near the center of the game area 4, there is provided a variable display device 6 including a plurality of variable display units each displaying a symbol as identification information in a variable manner. The variable display device 6 is constituted by an LCD, and is provided with a symbol display area (variable display portion) in which three special symbols “left”, “middle”, and “right” are displayed. In the symbol display area, an effective line for specifying whether or not the display result of the variable display is a jackpot display mode is set in advance. The combination of each special symbol finally stopped on the active line specifies whether or not it is a big hit display mode, and if each special symbol is aligned with the same symbol on the active line, it may be a big hit display mode Identified. Therefore, the player can easily recognize whether or not a big hit has occurred by confirming the display mode on the active line in the variable display device 6.

  Further, a special symbol start memory display (hereinafter referred to as a start memory display) 8 comprising four LEDs for displaying the number of effective winning balls that have entered the start winning opening 7, that is, the start winning memory number, is provided at the bottom of the fluctuation display device 6. Is provided. The start memory display 8 displays a winning display corresponding to the effective starting winning when the starting winning memory number is less than four. Specifically, the number of lighting is increased by 1 each time an effective start prize is generated, and the number of lighting is decreased by 1 each time a special symbol variation display is started. In this example, a display (special symbol start memory display) 8 for displaying the number of start winning memories is provided separately from the variable display device 6, but the start winning is provided at a predetermined position in the display area of the variable display device 6. You may make it provide the start memory | storage display area for alert | reporting the number of memory | storage.

  Below the variable display device 6, there are a start winning port 7 that also serves as an ordinary electric accessory 9 that opens and closes, and a large winning port that is opened by driving a solenoid or the like in a specific gaming state (big hit state). 10 are arranged side by side, and a gate 13 is disposed on the left side of the start winning opening 7. The special winning opening 10 is opened or closed by opening and closing the special winning opening door 11. When a game ball wins the gate 13, the normal symbol display device 14 starts a variable display in which the display state changes. In the vicinity of the normal symbol display device 14, a normal symbol start memory display 15 having a display unit with four LEDs for displaying the number of normal symbol start winning memorized numbers is provided. The game board 2 is provided with a plurality of winning openings 16, 17, 18, and 19.

  Two speakers 20 </ b> L and 20 </ b> R that emit sound effects are provided at the upper left and right sides of the gaming machine frame 3. In addition, a top frame lamp 21a, a left frame lamp 21b, and a right frame lamp 21c are provided on the outer periphery of the game area 4. Further, although not shown, decorative LEDs are installed around each structure (such as a big prize opening) in the game area 4. The top frame lamp 21a, the left frame lamp 21b, the right frame lamp 21c, and the decorative LED are examples of light emitters provided in the gaming machine.

  Next, a configuration example of a characteristic part of this example in the pachinko gaming machine 1 will be described with reference to FIG. Here, the configuration of each unit shown in FIG. 2 will be described with reference to each unit described in FIG. FIG. 2 is a block diagram showing an example of the configuration of the characteristic part of this example in the gaming machine 1. FIG. 2 shows a game control unit 201, an effect control unit 301, and a variable display device 6. The game control means 201 may be configured by only the CPU 33, for example, or may be configured to include the ROM 31, RAM 32, etc. in the CPU 33. For example, the effect control unit 301 may be configured by only the CPU 101, the CPU 101 may include the ROM 102, the RAM 103, or the like, or may be configured by a part or all of the configuration included in the display control unit 80. May be.

  The game control unit 201 includes an output unit 202 (for example, an output port) that outputs an effect control command. The effect control command output from the output means 202 is input to the input means 302 (for example, input port) of the effect control means 301.

  The effect control unit 301 includes an input unit 302 to which an effect control command is input, an image generation unit 303, a background control data storage unit 309, a background image storage unit 310, a front control data storage unit 311, and a front image storage. Means 312, background frame buffer 320, front frame buffer 325, front buffer switching means 328, image composition means 330, and image signal supply means 331 are included.

  The image generation unit 303 includes a background image generation unit 304 that generates a background image, and a front image generation unit 307 that generates a front image. The background image means an image displayed as a background on the variable display device 6. The front image means an image displayed on the front side of the background, that is, on the front side in the variable display device 6. Note that an image displayed on the back side of the front image in the variable display device 6 is referred to as a back image. In this example, since the back image is composed only of the background image, the back image may be referred to as the background image. The image generation unit 303 is configured by, for example, a GCL 81 described later.

  The background image generation unit 304 executes processing for generating a background image in accordance with the background control program stored in the background control data storage unit 309 (for example, the ROM 102). Specifically, the background image generation unit 304 reads background image data from the background image storage unit 310 (for example, CGROM 83) according to the background control program. If the read background image data is compressed data, the data expansion unit 306 (for example, the moving image compression / decompression unit 89) performs data expansion. The data decompression means 306 is, for example, data decompression of moving image data compressed by a widely used encoding method such as MPEG2 (Moving Picture Experts Group phase 2), or JPEG (Joint Photographic coding Experts Group), for example. Data expansion is performed on still image data that has been compressed by a widely used encoding method. Then, the background image expansion unit 305 expands the background image data in the background frame buffer 320.

  In this example, the background image developing unit 305 expands the background image data in the single background frame buffer 320 provided. The background image development means 305 develops each background image data in order in one background frame buffer 320 when developing a plurality of background image data sequentially.

  In this example, the storage information stored in the background image storage unit 310 includes background image data and development period index data. The expansion period index data is data associated with each background image data, and indicates the time required for expansion of the associated background image data (including the time required for expansion in the case of compressed data). It is data. That is, the background image storage unit 310 stores background image data and development period index data as a set.

  The front image generation unit 307 executes a process for generating a front image in accordance with a front control program stored in the front control data storage unit 311 (for example, the ROM 102). Specifically, the front image generation unit 304 reads the front image data from the front image storage unit 312 (for example, the CGROM 83) according to the front control program. Then, the front image expansion means 308 expands the front image data in the front frame buffer 325.

  In this example, the storage information stored in the front image storage unit 312 includes front image data and development period index data. The expansion period index data is data associated with each front image data, and indicates the time required to expand the associated front image data (including the time required for expansion in the case of compressed data). It is data. That is, the front image storage means 312 stores front image data and development period index data as a set.

  The front image development unit 308 develops the front image data in the front frame buffer designated by the front buffer switching unit 328. The front buffer switching means 328 executes a switching process so that the front image data is alternately developed in the front frame buffer A and the front frame buffer B. Therefore, the front image development unit 308 develops the front image data alternately in the front frame buffer A and the front frame buffer B in order when developing a plurality of front image data sequentially.

  The image synthesizing unit 330 (for example, GCL 81) executes a process of generating a synthesized image obtained by synthesizing the background image data expanded in the background frame buffer 320 and the front image data expanded in the front frame buffer 325. In this example, when sequentially generating a plurality of synthesized images, the image synthesizing unit 330 converts the front image data as a synthesis source into the front image data expanded in the front frame buffer A and the front frame buffer B. It alternately switches to the developed front image data, and sequentially generates synthesized image data synthesized with the background image data developed in the background frame buffer 320. When the composite image data is generated, the image composition unit 330 transmits the generated composite image data to the image signal supply unit 331.

  The image signal supply unit 331 (for example, the variation display device control unit 87 and the DAC 88) outputs an image signal to the variation display device 6 based on the composite image data received from the image composition unit 330.

  FIG. 3 is a block diagram illustrating a system configuration example centering on the game control unit. The pachinko gaming machine 1 in the present embodiment mainly includes a power supply unit (power supply board) 150, a game control unit (main board) 30, an input unit 52, an output unit 53, and an effect control unit (effect control board) 100. And a payout control unit (payout control board) 40, a board external terminal board 50, and a frame external terminal board 51.

  The game control unit 30 includes a ROM 31 that stores a game control program and the like, a RAM 32 that is used as a work memory, a CPU 33 that performs control operations according to the program, and an I / O port unit 34. Since the CPU 33 executes control according to the program stored in the ROM 31, hereinafter, the execution by the CPU 33 (or processing) means that the CPU 33 executes control according to the program. The same applies to CPUs mounted on boards other than the main board 30. Although not shown, the game control unit 30 includes a switch circuit that receives a signal input from the input unit 52 and a solenoid circuit that outputs a drive signal toward the output unit 53. The game control unit 30 has a function of generating various random numbers used in the game, a function of outputting control commands to the effect control unit 100 and the payout control unit 40, and a function of outputting various information to the hall management computer. Have various functions.

  The input unit 52 includes a start port switch 7a for detecting a winning ball to the starting winning port 7, a gate switch 13a for detecting a winning ball to the gate 13, and a winning ball guided from the large winning port 10 to the back of the game board 2. Among them, a specific area switch 22 for detecting a winning ball that has entered one (V winning area), a count switch 23 for detecting a winning ball from the grand prize opening 10, and winning balls to each of the winning openings 16, 17, 18, 19 It is constituted by various detection means such as a prize opening switch 16a, 17a, 18a, 19a. Each of the above switches may be a sensor. That is, the name of the detection means is not limited as long as the detection means can perform various types of detection such as detection of a game ball.

  The output unit 53 is used for switching a path in the ordinary winning combination solenoid 9 a for opening and closing the variable winning ball apparatus 9, the large winning opening door solenoid 11 a used for opening and closing the opening / closing plate 11, and the large winning opening 10. It is comprised by various drive means, such as a winning opening guide plate solenoid 12a.

  As shown in FIG. 3, the effect control unit 100 includes a display control unit 80 that performs control related to display of the variable display device 6 and the normal symbol display device 14, and a sound control unit that performs control related to sounds such as the speakers 20 </ b> L and 20 </ b> R. 70 and a lamp control unit 60 that performs control related to a light emitter such as the ceiling lamp 21a. Based on the control command from the game control unit 30, the effect control unit 100 performs display control, voice output control, and lamp display of the fluctuation display device 6 that fluctuates and displays the special symbol and the normal symbol display device 14 that fluctuates and displays the normal symbol. Each control is executed.

  The payout control unit 40 has a function of executing payout control for gaming balls, winning balls, and the like. The board external terminal board 50 and the frame external terminal board 51 serve to output various game-related information to the outside. Further, the power supply unit 150 is provided to supply a predetermined power supply voltage to each circuit in the pachinko gaming machine 1.

  Here, the state of the game in the pachinko gaming machine 1 of this example will be described. The game balls launched from the hit ball launching device enter the game area 4 through the hit ball rail, and then descend the game area 4. If the hit ball enters the start winning opening 7 and is detected by the start opening switch 7a, the special display of the special display on the variable display device 6 starts changing (variation) if the variable display of the symbol can be started. If it is not in a state where the symbol variation display can be started, the start winning memory number is increased by one.

  The special symbol variation display in the variation display device 6 stops when a certain time has elapsed. If the combination of special symbols on the active line at the time of the stop is a jackpot display mode, the game shifts to a jackpot gaming state. Specifically, the special winning opening 10 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. If the hit ball enters the V winning area while the special winning opening 10 is opened and is detected by the specific area switch 22, a continuation right is generated and the special winning opening 10 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of special symbols in the fluctuation display device 6 at the time of stoppage is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state (special game state) for the player, which is a probable change state.

  Note that the temporary stop timing, fluctuation time, etc. of the special symbol displayed on the fluctuation display device 6 are uniquely determined according to a fluctuation pattern designation command described later. In other words, the production control unit 100 performs, in conjunction with the timing of receiving the variation pattern command, the variation of the special symbol on the variation display device 6, the sound output from the speakers 20L and 20R, and the blinking display of the lamp / LED 21a, etc. Control is performed as follows.

  FIG. 4 is a block diagram showing a circuit configuration of the effect control board 100. The effect control board 100 includes a display control unit 80, a sound control unit 70, a lamp control unit 60, an effect control CPU 101 that controls each of the control units 60, 70, and 80, an effect control program, and a symbol display A ROM 102 that stores various effect patterns such as light emission and sound output, and a RAM 103 that is used as a work memory are provided. Although not shown, the effect control board 100 is provided with a command receiving circuit used for receiving effect control commands.

  The effect control CPU 101 operates according to a program stored in the ROM 102 and receives an effect control command from the main board 30. Then, the effect control CPU 101 performs various controls such as display control of the variable display device 6, lighting-on / off control of the light emitter, sound output control, drive control of the movable effect device, and the like according to the received effect control command.

  Specifically, the display control of the variable display device 6 gives a command according to the effect control command to a GCL (Graphics Controller LSI) 81. The GCL 81 reads necessary data from the CGROM 83 or the like. The CGROM 83 stores data indicating frequently used characters. The frequently used character stored in the CGROM 83 is, for example, a person, an animal, or an image made up of characters, figures, symbols, or the like displayed on the variable display device 6. Note that the character includes a moving image or a still image obtained by actual shooting. The GCL 81 generates image data to be displayed on the variable display device 6 according to the input data, and outputs R (red), G (green), B (blue) signals and a synchronization signal to the variable display device 6. The variable display device 6 performs screen display by a dot matrix method using a large number of pixels (pixels), for example. In this example, the R, G, and B signals are each represented by 8 bits. Therefore, according to the instruction from the GCL 81, the variable display device 6 can perform multi-color display of about 16.7 million colors with each of R, G, and B having 256 gradations. The number of bits of the R, G, and B signals may be other than 8 bits, and the number of bits of the R, G, and B signals may be different from each other.

  The display control unit 80 includes various storage media such as a CGROM 83 and an SDRAM (VRAM) 84. The SDRAM 84 stores data relating to a display image such as a frame buffer, character source data, and palette data used for specifying or changing display colors. The display control unit 80 includes a GCL 81 and a normal symbol driving circuit 82 for outputting a signal to the normal symbol display device 14.

  The GCL 81 includes various storage media such as a pallet data buffer 85 used for temporarily storing predetermined pallet data and a CG data buffer 86 used for temporarily storing predetermined CG data. In addition, it includes a drawing control unit, a variable display device control unit 87 and a DAC (digital analog converter) 88 for outputting a signal to the variable display device 6, and a moving image compression / decompression unit 89 for performing moving image compression processing and expansion processing. . The drawing control unit includes an attribute analysis unit 81a, a VRAM address generation unit 81b, a clipping unit 81c, and a translucent luminance modulation unit 81d. The attribute analysis unit 81a analyzes a parameter (referred to as an attribute) used when drawing a character. In this parameter, information for designating an image drawing order, the number of colors, an enlargement / reduction ratio, a palette number, coordinates, and the like are set. The moving picture compression / decompression unit 89 may be configured to be controlled by the GCL 81 or controlled by the effect control CPU 101.

  The sound control unit 70 is for generating a sound or sound effect according to a control command from the game control unit 30, a sound ROM 72 for storing sound data, and the like, amplifying the sound signal, and outputting it to the speakers 20L and 20R. And a digital volume 74 for setting the output level of the audio signal output from the low frequency amplifier circuit 73 to a level corresponding to the set volume.

  The lamp control unit 60 outputs a signal to the game state decoration LED 24b included in the lamp / LED 24 and a lamp driving circuit 61 for outputting a signal to the game state decoration lamp 24a included in the lamp / LED 24. LED drive circuit 62.

  Next, the operation of the gaming machine will be described. FIG. 5 is a flowchart showing main processing executed by game control means (CPU 33 and peripheral circuits such as ROM and RAM) on the main board 30. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 33 starts main processing after step S1. In the main process, the CPU 33 first performs necessary initial settings.

  In the initial setting process, the CPU 33 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization (step S5) of CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits), the RAM is set in an accessible state (step S6).

  The CPU 33 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC). The CTC also includes two external clock / timer trigger inputs CLK / TRG2, 3 and two timer outputs ZC / TO0,1.

  In the CPU 33 used in this embodiment, the following three types of modes are prepared as maskable interrupt modes. When a maskable interrupt occurs, the CPU 33 automatically sets the interrupt disabled state and saves the contents of the program counter on the stack.

  Interrupt mode 0: The built-in device that issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 33 executes an instruction at an address corresponding to the RST instruction or an address specified by the CALL instruction. At reset, the CPU 33 automatically enters interrupt mode 0. Therefore, when setting to the interrupt mode 1 or the interrupt mode 2, it is necessary to perform a process for setting the interrupt mode 1 or the interrupt mode 2 in the initial setting process.

  Interrupt mode 1: This mode always jumps to address 0038 (h) when an interrupt is accepted.

  Interrupt mode 2: The address synthesized from the value (1 byte) of the specific register (I register) of the CPU 33 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is a mode indicating the interrupt address. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of transmitting an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, an interrupt request from each built-in device can be easily processed, and interrupt processing can be installed at an arbitrary position in the program. Furthermore, unlike the interrupt mode 1, it is easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 33 is set to the interrupt mode 2 in step S2 of the initial setting process.

  Next, the CPU 33 confirms whether or not a clear switch provided in the gaming machine is on (step S7). When the on-state is detected in the confirmation, the CPU 33 executes a normal initialization process (steps S10 to S12). If the clear switch is not in the on state, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) was performed when power supply to the gaming machine was stopped Confirm (step S8). If it is confirmed that such protection processing has not been performed, the CPU 33 executes initialization processing. Whether there is backup data in the backup RAM area is confirmed, for example, by the state of the backup flag set in the backup RAM area in the power supply stop process.

  If it is confirmed that there is a backup, the CPU 33 performs a game state restoration process for returning the internal state of the game control means and the control state of the electric component control means such as the effect control means to the state when the power supply is stopped (step S9). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored.

  In the initialization process, the CPU 33 first performs a RAM clear process (step S10). In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a special symbol process flag, a payout command storage pointer, a winning ball flag, a ball out flag, a payout A work area setting process for setting an initial value to a flag for selectively performing processing according to a control state such as a stop flag is performed. Furthermore, a process of transmitting an initialization command for initializing the sub board (the effect control board 100 and the payout control board 40) to the sub board is executed (step S11). As the initialization command, there are a command indicating an initial symbol displayed on the variable display device 6, a payable state designation command indicating that the payable state is available, and the like.

  Then, the CTC register set in the CPU 33 is set so that a timer interrupt is periodically generated every 2 ms (step S12). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

  When the execution of the initialization process (steps S10 to S12) is completed, the display random number update process (step S14) and the initial value random number update process (step S15) are repeatedly executed in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt is prohibited (step S13). When the display random number update process and the initial value random number update process are finished, the interrupt is permitted. (Step S16). The display random number is a random number for determining a symbol displayed on the variable display device 6, and the display random number update process is a process for updating the count value of the counter for generating the display random number. . The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value such as a counter for generating a random number for determining whether or not to make a jackpot (a jackpot determining random number generation counter). In a game control process described later, when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process is executed, the interrupt is prohibited. The display random number update process is also executed in the timer interrupt process, which will be described later, and this conflicts with the process in the timer interrupt process. Is to avoid. That is, if the timer interrupt occurs during the process of step S14 and the count value of the counter for generating the display random number is updated during the timer interrupt process, the continuity of the count value may be impaired. is there. However, such an inconvenience does not occur if the interrupt is disabled during the process of step S14.

  When the timer interrupt occurs, the CPU 33 performs the register saving process (step S20), and then executes the game control process of steps S21 to S31 shown in FIG. In the game control process, the CPU 33 first inputs detection signals of switches such as the gate switch 12a, the start port switch 7a, the count switch 23, and the winning port switch 16a via the switch circuit 58, and determines the state thereof. (Switch process: Step S21).

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S23). The CPU 33 further performs a process of updating the count value of the counter for generating the display random number (step S24).

  In this example, the jackpot determination random number used to determine whether or not to generate a big hit, the outlier design determining random number used to determine the left and right right off symbols of the special symbol, the special symbol when generating the big hit Random number for determining the big hit symbol used when determining the combination, random number for determining the fluctuation pattern used for determining the fluctuation pattern of the special symbol, judgment per normal symbol used for determining whether or not to generate a hit based on the normal symbol Various random numbers such as a random number for use and an initial value determination random number used for determining the initial value of each random number are prepared.

  In step S23, the CPU 33 counts up (adds 1) a counter for generating a jackpot determining random number, a jackpot symbol determining random number, and a normal symbol determining random number. That is, they are determination random numbers, and other random numbers are display random numbers or initial value random numbers.

  Further, the CPU 33 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display device 14 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 33 performs a process of setting an effect control command related to the special symbol in a predetermined area of the RAM 55 and sending the effect control command (special symbol command control process: step S27). Also, a process for setting the effect control command for the normal symbol in a predetermined area of the RAM 32 and sending the effect control command is performed (normal symbol command control process: step S28).

  Further, the CPU 33 performs an information output process for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer (step S29).

  The CPU 33 issues a drive command to the solenoid circuit when a predetermined condition is satisfied (step S30). In order to open or close the variable winning ball apparatus 9 or the opening / closing plate 11 or to switch the game ball passage in the big winning opening 10, the solenoid circuit included in the main board 30 is connected to the solenoid 9a according to a drive command. , 11a, 12a are driven.

  Then, the CPU 33 executes a prize ball process for setting the number of prize balls based on the detection signals from the prize opening switches 16a, 17a, 18a, and 19a (step S31). Specifically, a payout control command indicating the number of winning balls is output to the payout control board 40 in response to detection of winning based on any of the winning opening switches 16a, 17a, 18a, 19a being turned on. The payout control CPU mounted on the payout control board 40 drives the ball payout device in accordance with a payout control command indicating the number of prize balls. Thereafter, the contents of the register are restored (step S32), and the interrupt enabled state is set (step S33).

  With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed in the main process. It may be executed.

  In this embodiment, the symbols “1” to “12” are variably displayed (varied) on the variation display device 6 as the left symbol, the middle symbol, and the right symbol, respectively. Symbol numbers “0” to “11” are assigned to symbols “1” to “12”. Further, a big hit occurs when the final stop symbols (determined symbols) in the variable display device 6 are complete. Then, when there is an odd number of symbols, the state changes to a high probability state (probability change state), which is a state in which the probability of occurrence of a big hit is improved.

  FIG. 7 is a flowchart showing an example of a special symbol process processing program executed by the CPU 33. The special symbol process shown in FIG. 7 is a specific process of step S25 in the flowchart of FIG. When performing the special symbol process, the CPU 33 performs the fluctuation shortening timer subtraction process (step S310) and the winning confirmation process (step S311), and then performs one of steps S301 to S309 according to the internal state. Process. The variation shortening timer is a timer for setting the variation time when the variation time of the special symbol is shortened.

  Winning confirmation processing (step S311): A ball is won at the start winning opening 7 and the process waits for the start opening switch 7a to be turned on. When the start opening switch 7a is turned on, if the start winning memory number is not full (in the state where the maximum value of 4 in this embodiment has been reached), the start winning memory number is incremented by 1 and the jackpot determination is determined. Extract random numbers such as random numbers. Then, they are stored in a random value storage area corresponding to the value of the number of stored start winning prizes. Further, a process for transmitting a start winning memory designation command for designating the number of starting winning memories after the addition is performed.

  Special symbol normal processing (step S301): Wait until the special symbol variable display can be started (when the value of the special symbol process flag is a value indicating step S301). The case where the value of the special symbol process flag is a value indicating step S301 is a case where the symbol is not changed in the variable display device 6 and the game is not a big hit game. When the special symbol variation display can be started, the start winning memory number is confirmed. If the start winning memorization number is not 0, the internal state (special symbol process flag) is updated to shift to step S302.

  Stop symbol setting process (step S302): The value stored in the random number value storage area corresponding to the start winning memory number = 1 is read, the value of the starting winning memory number is decreased by 1, and each random number value storage area Shift value. That is, each value stored in the random number storage area corresponding to the starting winning memory number = n (n = 2, 3, 4) is stored in the random value storing area corresponding to the starting winning memory number = n−1. To do. Next, based on the value stored in the random value storage area corresponding to the number of starting winning prizes = 1 (such as the value of the random number for jackpot determination), it is determined whether the jackpot, lose, reach, etc., and the determination result The stop symbol of the left middle right symbol is determined based on the control state at the start of the variable display. When the process is finished, the internal state (special symbol process flag) is updated to shift to step S303.

  Fluctuation pattern setting process (step S303): The symbol variation pattern is determined based on the value of the stop symbol determined in the stop symbol setting process or the random number for variation pattern determination. When the process is finished, the internal state (special symbol process flag) is updated to shift to step S304.

  All symbols variation processing (step S304): Control is performed so that the variation display device 6 starts variation of all symbols. At this time, information (effect control command) for instructing the left middle right final stop symbol and the variation mode (variation pattern) is transmitted to the performance control board 100. Specifically, the game control means transmits an effect control command for designating a variation pattern when starting the variation display, and subsequently transmits an effect control command for designating a left symbol, a middle symbol, and a right symbol. . When the process is finished, the internal state (special symbol process flag) is updated to shift to step S305.

  All symbols stop processing (step S305): When a predetermined time (time corresponding to the value set in the timer in step S304) elapses, an effect of instructing stop of all symbols in order to finally stop (determine) the left and right middle symbols Send a control command. Based on the reception of the effect control command, all symbols displayed on the variable display device 6 are stopped. Then, the game control means updates the internal state (special symbol process flag) so as to shift to step S306 when the stop symbol is a combination of jackpot symbol. If not, the internal state is updated to shift to step S301.

  Preliminary winning opening opening process (step S306): Control for opening the large winning opening is started. Specifically, the counter and flag are initialized, and the special winning opening door solenoid 11a is driven to open the special winning opening. The process timer sets the execution time of the big prize opening opening process, and sets a big hit flag (a flag indicating that the big hit is being made). When the process is finished, the internal state (special symbol process flag) is updated to shift to step S307.

  Processing during opening of the special winning opening (step S307): Control for sending the presentation control command data of the big winning opening round display to the production control board 100, processing for confirming the establishment of the closing condition of the special winning opening, and the like are performed. If the final closing condition of the big prize opening is satisfied, the internal state is updated to shift to step S308.

  Specific area valid time processing (step S308): The presence / absence of passing through the specific area switch 22 is monitored, and processing for confirming that the big hit gaming state continuation condition is satisfied is performed. If the condition for continuing the big hit gaming state is satisfied and there are still remaining rounds, the internal state is updated to shift to step S306. In addition, when the big hit gaming state continuation condition is not satisfied within a predetermined effective time, or when all rounds are finished, the internal state is updated to shift to step S309.

  Big hit end processing (step S309): An effect control command is sent to instruct the player to display that the big hit gaming state has ended. When the display period ends, the internal state is updated to shift to step S301.

  In this example, information transmission such as an instruction from the game control means to each electric component control means is performed by a control command. The control command has, for example, a 2-byte structure, and the first byte represents MODE (command classification), and the second byte represents EXT (command type). The effect control means mounted on the effect control board 100 detects that the INT signal (capture signal) has risen, starts an acquisition process of 1-byte data (MODE data) by an interrupt process, and thereafter The capturing process of 1 byte data (EXT data) is started by the interrupt process.

  Next, the operation of the effect control means will be described. FIG. 8 is a flowchart showing main processing executed by the CPU 101 for effect control. In the main process, first, an initialization process is performed for clearing the RAM area, setting various initial values, and initializing a 2 ms timer for determining the start interval of effect control (step S701). Thereafter, the effect control CPU 101 shifts to a loop process for monitoring the timer interrupt flag (step S702). When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the interrupt processing. If the timer interrupt flag is set in the main process, the effect control CPU 101 clears the flag (step S703) and executes the following effect control process.

  In this embodiment, the timer interrupt takes every 2 ms. That is, the effect control process is activated every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the specific effect control process is executed in the main process, but the effect control process may be executed in the timer interrupt process.

  In the effect control process, the effect control CPU 101 first analyzes the received effect control command (command analysis execution process: step S704). Next, the effect control CPU 101 performs effect control process processing (step S705). In the effect control process, a process corresponding to the current control state is selected and executed from among the processes corresponding to the control state. And the process which updates the various random number counters used with the production control board 100 is performed (step S706). Next, the effect control CPU 101 issues a drive command to a solenoid circuit included in a movable accessory control unit (not shown) when performing an effect by a game effect device (not shown) (solenoid output processing: step S707). In order to operate the game effect device, the solenoid circuit drives the solenoid in response to the drive command.

  Then, the effect control CPU 101 returns to the process of checking the timer interrupt flag in step S702.

  Next, an effect control command reception process from the main board 31 will be described. FIG. 9 is an explanatory diagram showing a configuration example of a command reception buffer for storing the effect control command received from the main board 31. In this example, a command reception buffer of a ring buffer type capable of storing six 2-byte configuration effect control commands is used. Therefore, the command reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11. It is not always necessary to use the ring buffer format. For example, three symbol designating command storage areas (2 × 3 = 6 byte command receiving buffer) and other command storing areas for designating other variation patterns ( (2 × 1 = 2-byte command reception buffer). Similarly, the sound control means and the lamp control means may have a buffer format other than the ring buffer format.

  An INT signal for effect control from the main board 31 is input to the interrupt terminal of the CPU 101 for effect control. For example, when the INT signal from the main board 31 is turned on, the production control CPU 101 is interrupted. Then, the effect control CPU 101 executes an effect control command reception process in the interrupt process. In the reception process of the effect control command, the effect control CPU 101 stores the received effect control command data in the reception command buffer indicated by the command reception number counter.

  FIG. 10 is a flowchart illustrating a specific example of command analysis processing (step S704). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101 confirms the content of the command stored in the command reception buffer.

  In the command analysis process, the effect control CPU 101 first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101 reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by one.

  If the received effect control command is a special symbol left designation effect control command (91XX (H)) (step S613), the effect control CPU 101 uses the data indicating the left symbol indicated by "XX" as data in the left of the RAM. Store in the symbol storage area (step S614). If it is the special symbol designating control command (92XX (H)) (step S616), the production control CPU 101 stores the data indicating the middle symbol indicated by "XX" in the middle symbol storage area in the RAM. Store (step S617). If the special symbol right designation effect control command (93XX (H)) is obtained (step S618), the effect control CPU 101 stores the data indicating the right symbol indicated by "XX" in the right symbol storage area in the RAM. Store (step S619).

  If the received effect control command is an effect control command for designating a variation pattern (step S621), the effect control CPU 101 stores the EXT data of the command in the variation pattern data storage area (step S622), and the variation pattern. A reception flag is set (step S623).

  If the received effect control command is an effect control command for designating the start prize memory number (step S631), the effect control CPU 101 counts the start prize memory number of the start prize number storage area in the RAM as specified by the effect control command. (Step S632). Further, the number of start memory display areas 18 in which the display color changes in the variable display device 6 is updated (step S633). Further, the value of the notice random number counter is incremented by 1 (step S634). When the count value of the notice random number counter exceeds the maximum value, the value is returned to zero. Further, when a plurality of notice random number counters are provided, for example, the notice random number counter n (in the case where four notice random number counters are provided is provided) so that the advance of each notice random number counter is not synchronized as much as possible. When the count value of n = 1 to 3) is returned to 0, the count value of the notice random number counter n + 1 may be incremented by one.

  If the received command read in step S612 is another effect control command, a flag corresponding to the received command is set (step S635).

  FIG. 11 is a flowchart showing the effect control process (step S705) in the main process shown in FIG. In the effect control process, any one of steps S801 to S806 is performed according to the value of the effect control process flag. In each process, the following process is executed.

  Fluctuation pattern command reception waiting process (step S801): It is confirmed whether or not an effect control command (fluctuation pattern command) capable of specifying the fluctuation time has been received by the command reception interrupt process. Specifically, it is confirmed whether or not a flag (variation pattern reception flag) indicating that a variation pattern command has been received is set. The variation pattern reception flag is set when it is confirmed by command analysis processing that a variation pattern designation effect control command has been received (step S623).

  All symbol variation start processing (step S802): Control is performed so that variation of the left middle right symbol is started.

  Symbol variation processing (step S803): Controls the switching timing of each variation state (variation speed) constituting the variation pattern, and monitors the end of the variation time. In addition, stop control of the left and right symbols is performed.

  All symbol stop waiting setting process (step S804): If an effect control command (special symbol stop effect control command) for instructing stop of all symbols is received at the end of the variation time, the symbol variation is stopped and the stop symbol ( Control to display the fixed symbol).

  Big hit display process (step S805): After the end of the fluctuation time, the control of the probability variable big hit display or the normal big hit display is performed.

  Process during jackpot game (step S806): Control during jackpot game is performed. For example, when an effect control command for display before opening the big winning opening or display when opening the big winning opening is received, display control of the number of rounds is performed.

  FIG. 12 is an explanatory diagram showing a configuration example of process data set for each variation pattern table. The process data is composed of data in which a plurality of combinations of process timer set values and presentation control execution data are collected. Each production control execution data includes display control execution data in which each variation mode constituting the variation pattern of the display control of the variation display device 6 or the like is described, and each of the variation patterns of the display control such as the lamp / LED. And lamp control execution data describing the variation mode. Specifically, as the display control execution data, data indicating the display state of the variation display device 6 in each variation mode is set. More specifically, in the data indicating the display state, the types of images such as backgrounds, symbols, characters, etc. constituting each frame (one image as a unit constituting a moving image) that is variably displayed on the variability display device 6. (Still image, sprite image, movie image), data indicating position and size are included. In addition, when a predetermined image is deformed and displayed, data (reduction / enlargement ratio, rotation ratio) indicating a deformation mode (for example, reduction, enlargement, or rotation) is included. Further, when a plurality of images are displayed in a superimposed manner (multiple layers), data relating to the priority indicating which image is displayed on the front side is also included. When a movie image is included in the frame, the data indicating the position, size, and deformation mode of the image is data indicating the position, size, and deformation mode of the movie image display area in which the movie image is displayed as a moving image. In the lamp control execution data, data indicating the display state of the lamp / LED in each variation mode is set.

  Further, the process timer set value is set with a change time in each change mode of the effect control execution data (a time corresponding to the change timing of the change mode). The effect control CPU 101 refers to the process data, displays the image in a varying manner set in the effect control execution data for the time set in the process timer set value, and turns on / off the light emitter. Control.

  The process data shown in FIG. 12 is stored in the ROM of the effect control board 100, and is based on the process data set in the variation pattern table selected as the use table in the all symbol variation start processing (step S802). Control of the variation display device 6 and the lamp / LED 24 is started, and control according to the effect control execution data is sequentially executed in the symbol variation processing (step S803). Process data is prepared for each variation pattern.

  In this way, the effect control means controls the effect means based on the program and process data stored in the ROM, and controls a plurality of effect means (in this embodiment, the variable display device 6 and the lamp / LED). The related program is stored in the ROM mounted on the effect control board 80. And ROM which stores those programs can be comprised as one ROM. Therefore, the number of parts can be reduced. Of the process data stored in the ROM, the process timer set value is shared. Therefore, the ROM capacity of the effect control means can be saved. Note that the effect control execution data may be one effect control execution data as long as the display control execution data and the lamp control execution data can be shared. Thus, in this embodiment, at least a part of the data related to the control of the plurality of rendering means can be stored in the same ROM.

  FIG. 13 is a flowchart showing a variation pattern command reception waiting process (step S801) in the effect control process shown in FIG. In the variation pattern command reception waiting process, the effect control CPU 101 checks whether or not the variation pattern reception flag is set (step S871). If it is set, the flag is reset (step S872). Then, the value of the effect control process flag is changed to a value corresponding to all symbol variation start processing (step S802) (step S873).

  FIG. 14 is a flowchart showing all symbol variation start processing (step S802) in the effect control process. In the all symbol variation start processing, the effect control CPU 101 first selects process data corresponding to the variation pattern of the variation display of the special symbol (step S881). Then, the process timer corresponding to the production execution data 1 in the selected process data is started (step S882). Next, the effect control CPU 101 performs LCD control based on the display control execution data 1 in the process data (step S884). Specifically, if the data indicating that the image should be developed in the VRAM 84 is set in the display control execution data 1, the effect control CPU 101 displays the frame displayed on the variable display device 6 according to the content of the data. The GCL 81 outputs a signal instructing development of each component image (for example, an image serving as a composition source of a display image such as a background image, an identification information image, and a character image) to the VRAM 84.

  The image development instruction signal includes data indicating the development position and size of each component image. In addition, when a predetermined part image is deformed (reduced, enlarged or rotated) and displayed, data (reduction / enlargement ratio, rotation rate) indicating a deformation mode of the predetermined part image is also included. In addition, when a plurality of component images are displayed in a superimposed manner, data on priority indicating which component image is displayed on the front side is also included. The image expansion processing by the GCL 81 based on the image expansion instruction signal from the effect control CPU 101 will be described later. Note that a ROM address may be set in the display control execution data, and more detailed control data may be stored in an area starting from the address, and LCD control may be performed according to the control data.

  The effect control CPU 101 performs lamp / LED control based on the lamp control execution data 1 in the process data (step S885). For example, a signal corresponding to the content of the lamp control execution data 1 is given to the lamp control unit 60. The lamp controller 60 controls lighting / extinguishing of each lamp / LED 24 based on a signal from the CPU 101 for effect control. Note that the ROM address is set in the lamp control execution data, and more detailed control data is stored in an area starting from the address, and the lamp / LED control is performed according to the control data. Good.

  Further, the production control CPU 101 outputs sound number data corresponding to the variation pattern to the sound control unit 70 (step S886). In the sound control unit 70, the sound IC 71 reads data corresponding to the sound number data from the sound ROM 72, generates sound and sound effects according to the read data, and outputs them to the low frequency amplifier circuit 73. The low frequency amplifier circuit 73 outputs an audio signal amplified to an output level corresponding to the volume set by the digital volume 74 to the speakers 20L and 20R.

  Thereafter, a variation time timer (a timer corresponding to the variation time of the special symbol) is started (step S887), and the value of the effect control process flag is set to a value corresponding to the symbol variation process (step S888).

  FIG. 15 is a flowchart showing the symbol variation process (step S803) in the effect control process. In the process during symbol variation, when the process timer times out (step S861), the effect control CPU 101 switches the effect control execution data in the process data (step S862). That is, in the process data, the next set process timer is started (step S863), and LCD control is performed based on the next set display control execution data (step S865). Further, lamp / LED control is performed based on the lamp control execution data set next in the process data (step S866). Note that the LCD control (step S865) processing based on the display control execution data is the same as step S884 of FIG. 14 described above.

  If the variable time timer has timed out (step S867), a monitoring timer for monitoring the reception of the special symbol stop display control command is started (step S868), and the value of the effect control process flag is set to all symbol stop waits. A value corresponding to the process is set (step S869).

  FIG. 16 is a flowchart showing the all symbol stop waiting process (step S804) in the effect control process. In the all symbol stop waiting process, the effect control CPU 101 confirms whether or not an effect control command (special symbol stop effect control command) for instructing stop of all symbols has been received (step S841). If an effect control command for instructing stop of all symbols has been received, control is performed to stop the symbol with the stored stop symbol (step S842).

  If the big hit symbol is displayed in step S842, the effect control CPU 101 sets the value of the effect control process flag to a value corresponding to the big hit display process (step S805) (step S844).

  When the big hit symbol is not displayed in step S842 (when the missing symbol is displayed), the effect control CPU 101 sets the value of the effect control process flag to a value corresponding to the variation pattern command reception waiting process (step S801). (Step S844).

  If an effect control command for designating all symbols to be stopped has not been received, it is confirmed whether or not the monitoring timer has timed out (step S848). If the timeout has occurred, it is determined that some abnormality has occurred, and control is performed to display an error screen on the variable display device 6 (step S849). Then, control goes to a step S843.

  FIG. 17 is a flowchart showing an example of index data determination processing executed by the effect control means. The index data determination process is a process for setting the development start timing of the image data that is executed in step S884 or step S865 when the image display process on the variable display device 6 is executed. In the index data determination process, the effect control CPU 101 is an image of an image used as a display image after a predetermined frame period (for example, after two frame periods) to the variable display device 6 based on the display control execution data in the process data. Development period index data (hereinafter simply referred to as “index data”) associated with the data is read (step S901). Specifically, when 30 images are displayed per second, the image after 2 frame periods refers to an image displayed after 2/30 seconds. In this case, the index data is read out 2/30 seconds before the image of the associated image data is displayed.

  Next, the effect control CPU 101 determines whether or not the expansion period indicated by the read index data is longer than a predetermined normal expansion period (step S902). The normal expansion period is a period that is set in advance as an image data expansion period during which image processing can be performed smoothly. The normal expansion period is set to a period that is at least a frame update period (for example, 1/30 second when 30 images are displayed per second).

  If it is longer than the normal expansion period, the production control CPU 101 sets the expansion start timing B as the start timing of the expansion processing of the image data associated with the index data (step S903). More specifically, for example, a timer for specifying the start time of the corresponding image data expansion processing, which starts time-out at the expansion start timing B, is started. “Deployment start timing B” is a timing earlier than the normal deployment start timing. Specifically, the “development start timing B” may be, for example, a timing two and a half frames before the image display start timing.

  If the period is equal to or shorter than the normal expansion period, the CPU 101 for effect control sets the expansion start timing A as the start timing of the expansion processing of the image data associated with the index data (step S904). Specifically, for example, it is a timer for specifying the start time of the corresponding image data expansion process, and starts a measurement of a development start monitoring timer that times out when the expansion start timing A is reached. “Deployment start timing A” is a normal deployment start timing. Specifically, the “development start timing A” may be, for example, a timing two frame periods before the image display start timing.

  As described above, the development start timing of each image data is set in advance before the development process of each image data is executed.

  FIG. 18 is a flowchart illustrating an example of image control processing executed by the effect control unit. The image control process is a process that collectively shows processes related to image display on the variable display device 6 executed in step S884 or step S865. In the image control process, the effect control CPU 101 checks whether there is image data that has reached the development start timing (step S911). Specifically, it is checked whether there is a development start monitoring timer that has timed out among the development start monitoring timers corresponding to each image data. Then, it is determined that the image data corresponding to the development start monitoring timer that has timed out is the image data at the development start timing.

  If there is image data at the development start timing, the effect control CPU 101 reads the image data from the CGROM 83 (step S912).

  If the special symbol image data is included in the image data at the development start timing (Y in step S913), the effect control CPU 101 will read the special symbol image data that has been read out in the front frame if the front buffer designation flag is 0. The data is expanded in the buffer A (steps S914 and S915). On the other hand, if the front buffer designation flag is not 0, the read special symbol image data is developed in the front frame buffer B (steps S914 and S916). When the front image (here, the special symbol image) is developed, the CPU 101 for effect control switches the state of the front buffer designation flag (step S917).

  The front buffer designation flag is a flag for specifying to which front frame buffer the front image data is to be developed from among a plurality of prepared front frame buffers. In this example, when the front buffer designation flag is 0, the front frame buffer A is selected as the frame buffer to be expanded, and when the front buffer designation flag is 1, the front frame buffer B is selected as the frame buffer to be expanded. Is done.

  In addition, the effect control CPU 101 checks whether a background image is included in the image data at the development start timing (step S918). If the background image is included, the effect control CPU 101 develops the image data of the background image in the back frame buffer (step S919).

  Next, the effect control CPU 101 displays the special symbol image developed in one of the front frame buffers when the display timing on the variable display device 6 is reached (for example, the timing of arrival every 33 ms) (step S920). A process of generating a composite image obtained by combining the data and the image data of the background image developed in the back frame buffer is executed (step S921).

  In this example, the front buffer designation flag is used to determine which development data of the front frame buffers A and B is used for generating the composite image. For example, when the front buffer designation flag is 0, the front frame buffer B is selected as the frame buffer in which the image used for generating the composite image is expanded, and when the front buffer designation flag is not 0, the composite image is generated. The front frame buffer A is selected as the frame buffer in which the image to be used is developed. In addition, it is good also as a structure which provides the flag for specifying the synthetic | combination origin frame buffer separately from a front surface buffer designation | designated flag.

  Then, the effect control CPU 101 outputs an image signal to display the generated composite image (step S922).

  FIG. 19 is an explanatory diagram showing examples of a character image, a special symbol image, and a background image used in this example. As the character image, for example, an image showing a person, an animal, an imaginary animal, a vehicle or other character, or a character imitating them is used. In this example, an image showing a human character as shown in FIGS. 19A-1 to 19A-4 is used. Note that, by sequentially displaying the character images in the order of FIG. 19 (a-1) to FIG. 19 (a-4), a moving image display in which the character moves within the display screen of the variable display device 6 is performed. .

  In this example, the special symbol image is an image showing three symbols on the middle left and right. In this example, as the special symbol image, an image showing a variation display of the special symbol as shown in FIGS. 19 (b-1) to 19 (b-4) is used. In addition, by displaying the identification information image sequentially in the order of FIG. 19 (b-1) to FIG. 19 (b-4), after the stop symbol in the previous variation display is displayed, high-speed rotation is started, A moving image is displayed that stops in the order of the left symbol and the middle symbol.

  As the background image, for example, an image showing a landscape is used. In this example, landscape images as shown in FIGS. 19C-1 to 19C-4 are used as the background image. Note that the background images are sequentially displayed in the order of FIG. 19 (c-1) to FIG. 19 (c-4), thereby displaying a moving image in which the scenery changes with the passage of time.

  FIG. 20 is an explanatory diagram illustrating an example of a state of image synthesis of the background image, the character image, and the special symbol in this example. In this example, for example, as shown in FIG. 20A, image synthesis is performed by synthesizing a character image on the front side of the background image and a front image obtained by synthesizing a special symbol image on the front side of the character image. Alternatively, for example, as shown in FIG. 20B, image synthesis is performed by synthesizing a special symbol image on the front side of the background image and a front image obtained by synthesizing the character image on the front side of the special symbol image. That is, the front image synthesized on the front side of the background image includes an image obtained by synthesizing the special symbol image on the front side of the character image and an image obtained by synthesizing the character image on the front side of the special symbol image.

  FIG. 21 is an explanatory diagram illustrating an example of a display state of a composite image with a background image using a front image obtained by combining a special symbol image on the front side of the character image. FIG. 21 is an explanatory diagram illustrating an example of a display state of a synthesized image obtained by synthesizing the character image, the special symbol image, and the background image illustrated in FIG. 19 with the arrangement illustrated in FIG. .

  FIG. 21 (A-1) shows the character image of FIG. 19 (a-1), the special symbol image of FIG. 19 (b-1), and the background image of FIG. 19 (c-1). The display state of the synthesized image synthesized in the arrangement as shown in FIG.

  FIG. 21 (A-2) shows the character image of FIG. 19 (a-2), the special symbol image of FIG. 19 (b-2), and the background image of FIG. 19 (c-2). The display state of the synthesized image synthesized in the arrangement as shown in FIG.

  FIG. 21 (A-3) shows the character image of FIG. 19 (a-3), the special symbol image of FIG. 19 (b-3), and the background image of FIG. 19 (c-3). The display state of the synthesized image synthesized in the arrangement as shown in FIG.

  FIG. 21 (A-4) shows the character image of FIG. 19 (a-4), the special symbol image of FIG. 19 (b-4), and the background image of FIG. 19 (c-4). The display state of the synthesized image synthesized in the arrangement as shown in FIG.

  Therefore, in FIGS. 21A-1 to 21A-4, the character image is synthesized on the back side of the special symbol image, and when the special symbol image and the character image overlap, the special symbol is displayed. The character image is displayed so as to be hidden behind the image.

  Note that the composite image is sequentially displayed in the order of FIG. 21A-1 to FIG. 21A-4, so that it is on the back side of the special symbol that is variably displayed and on the front side of the background image. Thus, a moving image is displayed as if the character is moving.

  FIG. 22 is an explanatory diagram illustrating an example of a display state of a combined image with a background image using a front image obtained by combining a special symbol image on the back side of the character image. FIG. 22 is an explanatory diagram illustrating an example of a display state of a combined image obtained by combining the character image, the special symbol image, and the background image illustrated in FIG. 19 in an arrangement as illustrated in FIG. .

  FIG. 22B-1 shows the character image shown in FIG. 19A-1, the special symbol image shown in FIG. 19B-1, and the background image shown in FIG. The display state of the synthesized image synthesized in the arrangement as shown in FIG.

  22 (B-2) shows the character image of FIG. 19 (a-2), the special symbol image of FIG. 19 (b-2), and the background image of FIG. 19 (c-2). The display state of the synthesized image synthesized in the arrangement as shown in FIG.

  22B-3, the character image of FIG. 19A-3, the special symbol image of FIG. 19B-3, and the background image of FIG. 19C-3 are shown in FIG. The display state of the synthesized image synthesized in the arrangement as shown in FIG.

  22B-4 shows the character image shown in FIG. 19A-4, the special symbol image shown in FIG. 19B-4, and the background image shown in FIG. 19C-4. The display state of the synthesized image synthesized in the arrangement as shown in FIG.

  Accordingly, in FIGS. 22B-1 to 22B-4, the character image is synthesized on the front side of the special symbol image, and when the special symbol image and the character image overlap, the character image The special symbol image is displayed so as to be hidden behind the screen.

  Note that the composite image is displayed in the order shown in FIGS. 22B-1 to 22B-4, so that the character is moving on the front side of the special symbol that is variably displayed. A video will be displayed.

  FIG. 23 is an explanatory diagram illustrating an example of the relationship between the confirmation timing of the index data associated with the image data, the development timing of the background image and the front image, and the display timing of the composite image. Note that the front image is an image synthesized on the front side of the background image, and in this example is a generated image obtained by synthesizing the special symbol image and the character image.

  Holding two pieces of transferred image data using two frame buffers set in the VRAM (SDRAM 84) is called double buffering. In this example, double buffering is executed by the two front frame buffers A and B which are frame buffers for the front image. While the front image developed in one front frame buffer (for example, front frame buffer A) is combined with the background image and displayed on the variable display device 6, the GCL 81 displays the other front frame buffer (for example, front frame buffer). A process of expanding the front image data is executed in B).

  In addition, the GCL 81 reads index data associated with each image data two frames before the development timing of each image data, and starts reading processing from the CGROM 83 for each image data to the frame buffer. A process for specifying a period until the expansion process is completed (hereinafter referred to as “expansion period”) is executed.

  Specifically, as shown in FIG. 23, the GCL 81 specifies the development period of each image based on the index data of the front image A1 and the background image B1 that has reached the development period determination timing. Thereafter, the GCL 81 expands the front image A1 in the front frame buffer A and expands the background image B1 in the background frame buffer for the background image when the expansion processing start timing comes. Then, the GCL 81 generates a composite image G1 obtained by combining the front image A1 and the background image B1 when the composite image generation timing is reached, and displays the composite image G1 on the variable display device 6.

  In addition, the GCL 81 specifies each development period based on the index data of the front image A2 and the background image B2 that have reached the development period determination timing. Thereafter, the GCL 81 expands the front image A2 in the front frame buffer B and expands the background image B2 in the background frame buffer at the start timing of the expansion processing. Then, the GCL 81 generates a composite image G2 obtained by combining the front image A2 and the background image B2 when the composite image generation timing is reached, and causes the variable display device 6 to display the composite image G2.

  As described above, the respective development periods are sequentially identified based on the index data of the front image and background image that are the development period determination timing, and the front image and background image that are the start timing of the development process are determined. The front image and the background image that have reached the generation timing of the composite image are sequentially combined, and the generated composite images G1, G2,... Are sequentially displayed on the variable display device 6. At this time, the front image is developed alternately in the front frame buffer A and the front frame buffer B.

  FIG. 24 is an explanatory diagram illustrating another example of the relationship between the confirmation timing of the index data associated with the image data, the development timing of the background image and the front image, and the display timing of the composite image. Note that the front image is an image synthesized on the front side of the background image, and in this example is a generated image obtained by synthesizing the special symbol image and the character image. In FIG. 24, when there is index data indicating a period longer than the normal expansion period in the index data associated with the image data used for image display (index data determined as Y in step S902). An example of the processing timing is shown.

  Also in this example, double buffering is executed by the two front frame buffers A and B which are frame buffers for the front image. While the front image developed in one front frame buffer (for example, front frame buffer A) is combined with the background image and displayed on the variable display device 6, the GCL 81 displays the other front frame buffer (for example, front frame buffer). A process of expanding the front image data is executed in B).

  Further, the GCL 81 reads index data associated with each image data two frame periods before the development timing of each image data, and executes a process of specifying the development period for each image data. When the expansion period specified from the index data is longer than a predetermined normal expansion period (see step S902), the expansion process is performed at an earlier timing than when it is within the normal expansion period. To start.

  Specifically, as shown in FIG. 24, the GCL 81 specifies the development period of each image based on the index data of the front image A5 and the background image B5 that have reached the development period determination timing. As a result, when it is determined that the expansion period of the front image A5 is longer than the normal expansion period, the start timing of the expansion process is set to a timing earlier by a predetermined period (for example, a 1/2 frame period). After that, the GCL 81 develops the front image A5 in the front frame buffer A when the development processing start timing set earlier by a predetermined period is reached, and the background frame buffer for the background image at the subsequent normal development processing start timing. The background image B5 is developed. The front image A5 is large-capacity data that requires a relatively long time for the expansion process. However, since the expansion process is started earlier by a predetermined period, the normal expansion end timing (for example, 1 from the normal expansion start timing). After the frame period, that is, for example, after the expedited start timing of the development, and after the elapse of 1.5 frame periods, the expansion process has been completed. Then, the GCL 81 generates a composite image G5 obtained by combining the front image A5 and the background image B5 when the composite image generation timing is reached, and displays the composite image G5 on the variable display device 6.

  It is preferable to set a period for advancing the start timing of the development process so that all images can be handled. Specifically, for example, a game machine designer confirms in advance the longest period among the periods indicated by the respective index data, and sets the start timing of the expansion process for a predetermined period equal to or longer than a period obtained by subtracting one frame period from that period. It is only necessary to set software and the like so as to be advanced. In the example shown in FIG. 24, it is assumed that the longest period among the periods indicated by the index data is a 1.4 frame period, and that all the images can complete the expansion process within the 1.5 frame period. In the case of a long development period, the start timing of the development process is uniformly advanced by 0.5 frame periods. With this configuration, all image data can be reliably developed, and frame dropping can be reliably prevented.

  In addition, it is good also as a structure which advances the start timing of an expansion | deployment process only by a required period according to the period which index data show, rather than the structure which advances the uniform timing. For example, when the period indicated by the index data is a 1.2 frame period, the start timing of the expansion process may be advanced by 0.2 frame period minus one frame period. Further, it may be advanced by 0.3 frame period minus 0.9 frame period with a margin.

  Further, as shown in FIG. 24, when the development period of the front image A6 to be developed following the front image A5 whose development period is longer than the normal development period is longer than the normal development period. Even in such a case, the development process of the front image A6 is started earlier by a predetermined period and is developed by double buffering, so that no frame drop occurs. Further, even if the expansion period of the front image A7 that is subjected to the expansion process subsequent to the front image A6 is an image that is longer than the normal expansion period, the combining process is completed for the front image A5 two frames before. (For example, the image A5 may be completed from the completion of the expansion of the image A5 until the start of the expansion of the image A7 after the elapse of 0.5 frame period).

  That is, in this example, since two front frame buffers are used, for example, as shown in FIG. 24, the development periods (periods developed in the frame buffer) of two front images whose display order is continuous overlap. Even if you do it, there is no such thing as dropping frames. Regardless of the amount of image data, the end timing of the expansion process is regular, and the period for expediting the expansion process is a fixed period (or an upper limit period for expediting the expansion process may be set). Therefore, it is possible to secure a period required for image composition, and to control the development period of three or more front images whose display order is continuous (the period developed in the frame buffer) not to overlap. , It can be surely prevented from dropping frames.

  With the above-described configuration, errors in image data in the development process are reduced, and image display using incorrect image data can be prevented. Note that the image data need not be alternately developed in the two front frame buffers A and B, and if necessary, the image data may be developed after one of the display areas. In the example shown in FIGS. 23 and 24, the two front frame buffers A and B are provided in the VRAM. However, three or more front frame buffers may be provided.

  As described above, based on the development period index data, for image data whose development process exceeds a predetermined reference period (for example, a normal development period), the development process to the frame buffer is started in advance. Therefore, it is possible to prevent the subsequent expansion processing of other image data from being affected, and it is possible to display an image without dropping frames.

  Further, as described above, the image processing of the front image data is performed by double buffering, and the image processing of the front image data is performed separately, so that the image display can be performed without dropping frames, The processing efficiency of image processing by double buffering can be improved. Further, since the image processing of the front image is executed by double buffering, it is possible to prevent the front image from being dropped even if the data capacity of the front image data is large.

  Further, as described above, since the development period index data is stored together with the image data in the front image storage means 312 and the background image storage means 310, the development period index data can be read simultaneously with reading out the image data. (For example, not only the development period index data but also the image data can be read in step S901), and the control burden can be reduced. In addition, it becomes easy to read out the corresponding development period index data in advance at a timing before reading out the image data, and it is easy to determine the development period in advance before starting the development process of the image data. It becomes.

  The development period index data may be stored in the front control data storage unit 311 or the background control data storage unit 309 instead of the front image storage unit 312 or the background image storage unit 310. Even in such a configuration, it becomes easy to read out the corresponding development period index data in advance at a timing before reading out the image data, and the development is performed in advance before starting the development processing of the image data. It becomes easy to determine the period.

  Further, as described above, since the maximum period (for example, 1.5 frame period) among the expansion periods of each image data is secured and the expansion period is specified from the expansion period index data, the image data Can be ensured for a certain period of time, and frame loss of all image data can be prevented.

  In the above-described embodiment, the image processing of the front image data is performed by double buffering using two frame buffers, but may be performed by triple buffering using three frame buffers. The case of such a configuration will be described in detail with reference to FIGS.

  FIG. 25 is a block diagram illustrating a configuration example of a characteristic part of a pachinko gaming machine configured to perform image processing of front image data by triple buffering. A detailed description of portions having the same configuration as the configuration shown in FIG. 2 is omitted.

  In this example, the front image development unit 308 develops the front image data in the front frame buffer designated by the front buffer switching unit 328. The front buffer switching means 328 performs a switching process so that the front image data is alternately developed in the front frame buffer A and the front frame buffer B when the image data whose expansion period is equal to or less than the normal expansion period is processed. Execute. Accordingly, when image data whose expansion period is equal to or less than the normal expansion period is being processed, the front image expansion unit 308, when sequentially expanding a plurality of front image data, The front image data is developed in turn alternately.

  When the front buffer switching means 328 starts processing the image data whose development period exceeds the normal development period, the front buffer switching means 328 includes three front frame buffers including the front frame buffer C in addition to the front frame buffer A and the front frame buffer B. A switching process in which the front image data is sequentially developed is started. Accordingly, after the appearance of image data whose development period exceeds the normal development period, the front image development means 308 sequentially advances the front frame buffer A to the front frame buffer C when developing a plurality of front image data. The front image data is expanded to

  The image synthesizing unit 330 (for example, GCL 81) executes a process of generating a synthesized image obtained by synthesizing the background image data expanded in the background frame buffer 320 and the front image data expanded in the front frame buffer 325. In this example, the image compositing means 330, when image data whose development period exceeds the normal development period appears, when generating a plurality of composite images sequentially, the front image buffer as the composition source is displayed on the front frame buffer A. , The background image data developed in the front frame buffer B, the background image data developed in the front frame buffer B, and the front frame buffer C are sequentially switched. Then, the image synthesizing unit 330 sequentially generates a synthesized image obtained by synthesizing the front image data on the front side of the background image data as a synthesis source. When the composite image data is generated, the image composition unit 330 transmits the generated composite image data to the image signal supply unit 331.

  FIG. 26 is a flowchart showing another example of index data determination processing executed by the effect control means. In the index data determination process, the image data expansion period executed in step S884 or step S865 when the image display process on the variable display device 6 is performed is defined as the expansion period A (the expansion process within the normal expansion period described above). Is set to one of the expansion period B (the period during which the expansion process cannot be completed within the normal expansion period). In the index data determination process, the effect control CPU 101 is an image of an image used as a display image after a predetermined frame period (for example, after two frame periods) to the variable display device 6 based on the display control execution data in the process data. Development period index data (hereinafter simply referred to as “index data”) associated with the data is read (step S901).

  Next, the effect control CPU 101 determines whether or not the expansion period indicated by the read index data is longer than a predetermined normal expansion period (step S902).

  If it is longer than the normal expansion period, the effect control CPU 101 sets the expansion period B as the expansion period of the image data associated with the index data (step S905). Specifically, for example, a flag for specifying the type of the development period of the corresponding image data (type of development period A or development period B) is set in a state indicating the development period B.

  If the period is equal to or shorter than the normal expansion period, the effect control CPU 101 sets the expansion period A as the expansion period of the image data associated with the index data (step S906). Specifically, for example, a flag for specifying the type of the development period of the corresponding image data is set to a state indicating the development period A.

  As described above, the type of development period of each image data is set in advance before the development process of each image data is executed.

  FIG. 27 is a flowchart showing another example of the image control process executed by the effect control means. The image control process is a process that collectively shows processes related to image display on the variable display device 6 executed in step S884 or step S865. In the image control process, the effect control CPU 101 checks whether there is image data that has reached the development start timing (step S911).

  If there is image data at the development start timing, the effect control CPU 101 reads the image data from the CGROM 83 (step S912). In this example, the development start timing comes every predetermined period (for example, every one frame period), and the image data is sequentially read out in a predetermined order every predetermined period.

  When the special symbol image data is included in the image data at the development start timing (Y in step S913), the effect control CPU 101 determines that the development period type of the special symbol image data is the development period B. (Step S925), the front buffer designation counter is changed (Step S926).

  The front buffer designation counter (an example of the front buffer switching means 328) is a counter for designating one of a plurality of front frame buffers. In this example, the front buffer designation counter X used for double buffering is used. And a front buffer designation counter Y used for triple buffering. The front buffer designation counter X is a counter that takes a value in the range of 0 to 1 and alternately indicates two values of 0 and 1 by counting up. When the counter is 0, the front frame buffer A is indicated. Indicates the front frame buffer B. The front buffer designation counter Y is a counter that takes a value in the range of 0 to 2, and sequentially updates three values of 0 to 2 by counting up. When it is 0, it indicates the front frame buffer A. In this case, the front frame buffer B is indicated, and in the case of 2, the front frame buffer C is indicated.

  In step S926, a process of changing the front buffer designation counter from the front buffer designation counter X to the front buffer designation counter Y is performed. Specifically, a process of changing the range of values that can be taken by the front buffer designation counter from the range of 0 to 1 to 0 to 2 is executed. That is, the double buffering is changed to the triple buffering by changing the front buffer designation counter in step S926.

  Next, the effect control CPU 101 adds 1 to the count value of the front buffer designation counter (step S927), and develops the special symbol image data read to the front frame buffer pointed to by the front buffer designation counter. If the count value of the front buffer designation counter is 0, the read special symbol image data is expanded in the front frame buffer A. If the count value of the front buffer designation counter is 1, the read special symbol image data is displayed in the front frame buffer B. If the count value of the front buffer designation counter is 2, the read special symbol image data is developed in the front frame buffer C.

  In addition, the effect control CPU 101 checks whether a background image is included in the image data at the development start timing (step S918). If the background image is included, the effect control CPU 101 develops the image data of the background image in the back frame buffer (step S919).

  Next, when the display timing on the variable display device 6 (for example, the timing of arrival every 33 ms) is reached (step S920), the effect control CPU 101 has a special symbol developed in one of the front frame buffers. A process of generating a composite image by combining the image data and the image data of the background image developed in the back frame buffer is executed (step S921).

  Note that, regarding the determination of which development data of the front frame buffers A, B, and C is used to generate a composite image, in this example, the frame buffer that is the synthesis source is specified separately from the front buffer designation counter. The composition source buffer specifying counter may be provided, and the expanded data of the frame buffer indicated by the composition source buffer specifying counter may be used for image composition. Similar to the front buffer designation counter, the composition source buffer specifying counter is provided with double buffering and triple buffering, and may be configured to be sequentially counted up every time image composition is executed. Note that the front buffer designation counter may be used to determine which development data of the front frame buffers A, B, and C is used for generating the composite image.

  Then, the effect control CPU 101 outputs an image signal to display the generated composite image (step S922).

  FIG. 28 is an explanatory diagram illustrating another example of the relationship among the confirmation timing of the index data associated with the image data, the development timing of the background image and the front image, and the display timing of the composite image. Note that the front image is an image synthesized on the front side of the background image, and in this example is a generated image obtained by synthesizing the special symbol image and the character image.

  In this example, double buffering is executed by the two front frame buffers A and B which are frame buffers for the front image. In this example, after the predetermined condition is satisfied, triple buffering is executed by the three front frame buffers A, B, and C which are front image frame buffers.

  The GCL 81 reads the index data associated with each image data two frames before the development timing of each image data, and starts the read processing from the CGROM 83 for each image data and then develops it into the frame buffer. A period until the process is completed (hereinafter referred to as “expansion period”) is specified, and a process for setting the type of the expansion period is executed. Then, image data expansion processing is started every predetermined period.

  Specifically, as shown in FIG. 28, the GCL 81 specifies the development period of each image based on the index data of the front image A1 and the background image B1 that has reached the development period determination timing, and sets the type of the development period. Set. If the set type is the expansion period A, processing by double buffering is executed. That is, after that, when the start timing of the expansion process arrives, the GCL 81 expands the front image A1 in the front frame buffer A and expands the background image B1 in the background frame buffer for the background image. Then, the GCL 81 generates a composite image G1 obtained by combining the front image A1 and the background image B1 when the composite image generation timing is reached, and displays the composite image G1 on the variable display device 6.

  In addition, the GCL 81 specifies each development period based on the index data of the front image A2 and the background image B2 at the development period determination timing, and sets the type of the development period. If the set type is the expansion period A, processing by double buffering is continued. That is, the GCL 81 then develops the front image A2 in the front frame buffer B and the background image B2 in the background frame buffer when the development processing start timing comes. Then, the GCL 81 generates a composite image G2 obtained by combining the front image A2 and the background image B2 when the composite image generation timing is reached, and causes the variable display device 6 to display the composite image G2.

  As described above, based on the index data of the front image and the background image at the development period determination timing, the respective development periods are identified sequentially, the type of the development period is sequentially set, and the development period B is set. Until it is done, processing by double buffering is executed. That is, for the development of the front image, the front frame buffer A and the front frame buffer B are alternately developed.

  Then, the GCL 81 identifies each development period based on the index data of the front image A5 and the background image B5 that has reached the development period determination timing, and sets the type of the development period. Since the set type is the expansion period B, the GCL 81 changes the front buffer designation counter to the processing by triple buffering. That is, the GCL 81 then develops the front image A5 in the front frame buffer C and the background image B5 in the background frame buffer when the development processing start timing comes. Then, the GCL 81 generates a composite image G5 obtained by combining the front image A5 and the background image B5 when the composite image generation timing is reached, and displays the composite image G5 on the variable display device 6. Thereafter, processing by triple buffering is continuously executed. That is, for the development of the front image, the front frame buffer A to the front frame buffer C are developed in order.

  As described above, when image data whose development period exceeds the normal development period appears, the configuration is switched from double buffering to triple buffering, so that the image data can be efficiently developed and frame dropping is not caused. It can prevent more reliably that it generate | occur | produces.

  Further, as shown in FIG. 28, when the front images A6 and A7 that are subjected to the development process following the front image A5 whose development period is longer than the normal development period are longer than the normal development period. Even so, frame dropping does not occur because it is expanded by triple buffering.

  In the above example, the processing by double buffering is usually executed, and when the image data having a long development period appears, it is completely changed to triple buffering. However, the development period is long. May be temporarily changed to triple buffering when image data appears, and returned to processing by double buffering when image data having a long development period no longer appears.

  Further, as described above, based on the index data, the image data that exceeds the normal expansion period is different from the frame buffer (front frame buffers A and B in FIG. 28) that expands the image data that does not exceed the normal expansion time. Since the frame buffer (front frame buffer C in FIG. 28) is developed, image display can be performed without dropping frames.

  In the above example, after image data that exceeds the normal expansion period appears, the image data is sequentially expanded in the three front frame buffers A, B, and C. For example, as shown in FIG. 29, the normal expansion period is exceeded. Only the image data may be developed in the front frame buffer C, and only the image data not exceeding the normal development time may be alternately developed in the front frame buffers A and B. For example, as shown in FIG. 30, two front frame buffers for developing only image data exceeding the normal expansion period may be provided, and image data exceeding the normal expansion period may be processed by double buffering. Furthermore, a configuration may be used in which one front frame buffer that expands only image data that does not exceed the normal expansion period is used. For example, as shown in FIG. 31, two front frame buffers for developing only image data exceeding the normal expansion period are provided, and one front frame buffer for developing only image data not exceeding the normal expansion period is used. It is good.

  FIG. 29 shows the confirmation timing of the index data associated with the image data, the development timing of the background image and the front image, when only the image data exceeding the normal development period is developed in the front frame buffer C. FIG. 10 is an explanatory diagram showing another example of the relationship with the display timing of the composite image.

  In the example shown in FIG. 29, when the image data of the front images A1 to A4 that do not exceed the normal expansion period are alternately developed in the front frame buffers A and B, and image data of the front image A5 that exceeds the normal expansion period appears. Development is performed in a front frame buffer C (frame buffer for a large development period) provided for development of image data having a long development period. Thereafter, the image data of the front images A6 to A7 and A9 that do not exceed the normal expansion period are alternately expanded in the front frame buffers A and B, and when the image data of the front images A8 and A10 that exceed the normal expansion period appears. , Processing to expand to the front frame buffer C is performed.

  As described above, based on the development index data, if image data that exceeds the normal development period is developed in a frame buffer that is different from the frame buffer that develops image data that does not exceed the normal development time, normal development is performed. Since the image data exceeding the period can be expanded without affecting the image data not exceeding the normal expansion time, the image can be displayed without dropping frames.

  FIG. 30 shows the confirmation timing of the index data associated with the image data and the development of the background image and the front image in the case where two front frame buffers for developing only the image data exceeding the normal development period are provided. It is explanatory drawing which shows the other example of the relationship between timing and the display timing of a synthesized image.

  In the example shown in FIG. 30, the image data of the front images A1 to A4 that do not exceed the normal expansion period are alternately developed in the front frame buffers A and B, and the image data of the front images A5 to A6 that exceed the normal expansion period appears. In some cases, the image data is developed alternately in two front frame buffers C and D (frame buffers for a large development period) provided for development of image data having a long development period. Thereafter, the image data of the front images A7 to A8 and A10 that do not exceed the normal expansion period are alternately expanded in the front frame buffers A and B, and when the image data of the front image A9 that exceeds the normal expansion period appears, In order to execute the process of alternately developing in the frame buffers C and D, the process of expanding in the front image frame buffer C is performed.

  As described above, based on the development index data, the image data that exceeds the normal development period is developed in a frame buffer that is different from the frame buffer that develops the image data that does not exceed the normal development time, and the normal development period is exceeded. If the image data is expanded by double buffering, image data that exceeds the normal expansion period can be expanded without affecting the image data that does not exceed the normal expansion time, and image data that exceeds the normal expansion period. Even when the characters appear in succession, it is possible to avoid duplication of the expansion period, and it is possible to display an image without dropping frames.

  FIG. 31 shows an image in a case where two front frame buffers for expanding only image data exceeding the normal expansion period are provided and one front frame buffer for expanding only image data not exceeding the normal expansion period is used. It is explanatory drawing which shows the other example of the relationship between the confirmation timing of the index data matched with data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image.

  In the example shown in FIG. 31, the image data of the front images A1 to A4 that do not exceed the normal expansion period are sequentially expanded in the front frame buffer A, and the image data of the front images A5 to A6 that exceeds the normal expansion period appears. The two front frame buffers B and C (frame buffers for a long development period) provided for development of image data having a long period are alternately developed. Thereafter, the image data of the front images A7 to A8, A10 that do not exceed the normal expansion period are sequentially expanded in the front frame buffer A. When image data of the front image A9 that exceeds the normal expansion period appears, the front frame buffer B , C, the process of developing in the front image frame buffer B is performed.

  As described above, based on the development index data, image data that exceeds the normal development period is developed in a frame buffer that is different from one frame buffer that develops image data that does not exceed the normal development time, and the normal development period. If the image data exceeding the normal expansion period is expanded by double buffering, the image data exceeding the normal expansion period can be expanded without affecting the image data not exceeding the normal expansion time, and the normal expansion period is exceeded. Even when image data appears continuously, duplication of development periods can be avoided, and image display can be performed without dropping frames. In addition, the configuration is such that only one frame buffer is provided for developing image data that does not exceed the normal development time, and double buffering is not applied to the development of image data that does not exceed the normal development time, thus reducing the control burden. Can be made.

  In each of the embodiments described above, the image processing of the front image data is performed by double buffering or triple buffering. However, the image processing of the background image data is also performed by double buffering or triple buffering. May be. Thus, if the image processing of the background image data and the image processing of the front image data are performed by double buffering or triple buffering, respectively, it is possible to more reliably prevent frame dropping, and more An image can be displayed smoothly. Further, both the background image and the front image can take a longer image generation time, and elaborate images (for example, moving images using a three-dimensional CG image) can be generated.

  In the embodiment described above, regarding the image processing of the front image data, the development period is grasped in advance using the index data. If the development period is long, the development start timing is advanced, and double buffering is performed. Although it was configured to perform image processing, for image processing of background image data as well, the index data is used to grasp the expansion period in advance, and if the expansion period is long, the expansion start timing is advanced, and double buffering It is good also as a structure which performs image processing by.

  In FIG. 32, for the image processing of the background image data, the development period is grasped in advance using the index data. When the development period is long, the development start timing is advanced, and image processing is performed by double buffering. It is a block diagram which shows the example of a structure of the characteristic part of the game machine in the case of having made. In addition, about the part which is the structure same as the structure of FIG. 2 mentioned above, the same code | symbol is provided and the detailed description is abbreviate | omitted.

  As shown in FIG. 32, in this example, the effect control unit 301 includes a background frame buffer 320 and a background buffer switching unit 323.

  The index data is separately associated with the background image data and the front image data. In addition, the index data used in common may be associated only with either one of the background image data and the front image data (corresponding background image data and front image data combined with each other) in a correspondence relationship. . Specifically, when index data is associated only with the front image data and the development period of the background image data is determined, the index data associated with the front image data having a correspondence relationship with the background image data The determination may be made using.

  The background image expansion unit 305 expands the background image data in the background frame buffer designated by the background buffer switching unit 323. The background buffer switching unit 323 executes switching processing so that background image data is alternately developed in the background frame buffer A and the background frame buffer B. Therefore, the background image development means 305 develops the background image data in turn alternately in the background frame buffer A and the background frame buffer B when developing a plurality of background image data sequentially.

  The image synthesizing unit 330 (for example, GCL 81) executes a process of generating a synthesized image obtained by synthesizing the background image data expanded in the background frame buffer 320 and the front image data expanded in the front frame buffer 325. In this example, when the image composition means 330 sequentially generates a plurality of composite images, the background image data as the composition source is stored in the background image buffer developed in the background frame buffer A and the background frame buffer B. The image data is alternately switched to the developed background image data, and the front image data as the composition source is changed to the front image data developed in the front frame buffer A, the front image data developed in the front frame buffer B, and Are alternately switched to sequentially generate synthesized image data obtained by synthesizing the background image data and the front image data. When the composite image data is generated, the image composition unit 330 transmits the generated composite image data to the image signal supply unit 331.

  In FIG. 33, for the image processing of the background image data, the development period is grasped in advance using the index data. When the development period is long, the development start timing is advanced, and the image processing is performed by double buffering. FIG. 6 is an explanatory diagram illustrating an example of a relationship between a confirmation timing of index data associated with image data, a development timing of a background image and a front image, and a display timing of a composite image in a case where Note that the front image is an image synthesized on the front side of the background image, and in this example is a generated image obtained by synthesizing the special symbol image and the character image. In FIG. 33, when there is index data indicating a period longer than the normal expansion period in the index data associated with the image data used for image display (index data determined as Y in step S902). An example of the processing timing is shown.

  In this example, double buffering is executed by the two front frame buffers A and B, which are frame buffers for the front image. While the front image developed in one front frame buffer (for example, front frame buffer A) is combined with the background image and displayed on the variable display device 6, the GCL 81 displays the other front frame buffer (for example, front frame buffer). A process of expanding the front image data is executed in B).

  In this example, double buffering is executed by the two background frame buffers A and B which are frame buffers for the background image. While the background image developed in one background frame buffer (eg, background frame buffer A) is combined with the front image and displayed on the variable display device 6, the GCL 81 displays the other background frame buffer (eg, background frame buffer). A process of expanding the background image data is executed in B).

  Further, the GCL 81 reads index data associated with each image data two frames before the development timing of each of the front image data and the background image data, and executes a process of specifying the development period for each image data. To do. When the expansion period specified from the index data is longer than a predetermined normal expansion period (see step S902), the expansion process is performed at an earlier timing than when it is within the normal expansion period. To start.

  Specifically, as shown in FIG. 33, the GCL 81 specifies the expansion period of each image based on the index data of the front image A5 and the background image B5 that have reached the expansion period determination timing. As a result, when it is determined that the expansion period of the front image A5 and the background image B5 is longer than the normal expansion period, the start timing of the expansion process is advanced by a predetermined period (for example, a 1/2 frame period). Set. Thereafter, the GCL 81 develops the front image A5 in the front frame buffer A and the background image B5 in the background frame buffer for the background image when the development processing start timing set earlier by a predetermined period comes. The front image A5 and the background image B5 are large-capacity data that requires a relatively long time for the expansion process, but since the expansion process is started earlier by a predetermined period, a normal expansion end timing (for example, normal expansion) After one frame period from the start timing, that is, for example, after 1.5 frame periods have elapsed from the earlier development start timing, the development process has been completed. Then, the GCL 81 generates a composite image G5 obtained by combining the front image A5 and the background image B5 when the composite image generation timing is reached, and displays the composite image G5 on the variable display device 6.

  As shown in FIG. 33, the development period of the front image A6 and the background image B6 that are developed following the front image A5 and the background image B5 whose development period is longer than the normal development period is also normally developed. Even when the period is longer than the period, the expansion processing of the front image A6 and the background image B6 is started earlier by a predetermined period, and both the front image and the background image are expanded by double buffering. There will be no dropped frames. Further, even if the front image A7 and the background image B7 that are developed following the front image A6 and the background image B6 are images whose development period is longer than the normal development period, two frames before For the front image A5 and the background image B5, the synthesis process has been completed (for example, the image A5 and B5 are completed from the completion of the development until the start of the development of the images A7 and B7 after a lapse of 0.5 frame period). Therefore, frame dropping does not occur.

  That is, in this example, since two front frame buffers are used and two background frame buffers are used, for example, as shown in FIG. Even if the period (expanded in the frame buffer) overlaps, frames are not dropped, and the expansion period of two background images (expanded in the frame buffer) that overlap in display order overlaps. There is no such thing as dropping frames. Regardless of the amount of image data, the end timing of the expansion process is regular, and the period for expediting the expansion process is a fixed period (or an upper limit period for expediting the expansion process may be set). Therefore, it is possible to secure a period required for image synthesis, and control so that the development periods (periods developed in the frame buffer) of three or more front images whose display order is continuous do not overlap. At the same time, it is possible to control the development period of three or more background images in which the display order is continuous (the period developed in the frame buffer) so as not to overlap, thereby reliably preventing frame dropping.

  With the above-described configuration, errors in image data in the development process are reduced, and image display using incorrect image data can be prevented. Note that the image data need not be alternately developed in the two front frame buffers A and B, and if necessary, the image data may be developed after one of the display areas. Similarly, the image data need not be alternately developed in the two background frame buffers A and B, and if necessary, the image data may be developed following one of the display areas. In the example shown in FIG. 33, the two front frame buffers A and B and the two background frame buffers A and B are provided in the VRAM. However, three or more front frame buffers may be provided. Three or more background frame buffers may be provided.

  As described above, if the image data of the front image and the background image is developed in advance in the frame buffer based on the development index data, and both the front image and the background image are subjected to image processing by double buffering, the frame data is processed. The reliability of drop prevention can be further increased.

  Further, in each of the above-described embodiments, regarding the image processing of the front image data, the development period is grasped in advance using the index data, and the transition from double buffering to triple buffering is performed when the development period is long. However, as for the image processing of the background image data, the index data is used to grasp the expansion period in advance, and when the expansion period is long, the structure is shifted from double buffering to triple buffering. Also good.

  FIG. 34 shows a case in which the development period is grasped in advance using the index data for the image processing of the background image data, and the transition from double buffering to triple buffering is performed when the development period is long. FIG. 5 is an explanatory diagram showing an example of a relationship among a confirmation timing of index data associated with image data, a development timing of a background image and a front image, and a display timing of a composite image. Note that the front image is an image synthesized on the front side of the background image, and in this example is a generated image obtained by synthesizing the special symbol image and the character image.

  As shown in FIG. 34, in this example, double buffering is performed by two front frame buffers A and B that are front image frame buffers, and two background frame buffers that are background image frame buffers. Double buffering is executed by A and B. After the predetermined condition is established for the front image, triple buffering is executed by the three front frame buffers A, B, and C, which are frame buffers for the front image. Similarly, after a predetermined condition is established for the background image, triple buffering is executed by the three background frame buffers A, B, and C, which are frame buffers for the background image.

  The GCL 81 reads index data associated with each image data two frames before the development timing of each image data of the front image and the background image, and starts reading processing from the CGROM 83 for each image data. A period (hereinafter referred to as “development period”) from when the expansion process to the frame buffer ends is specified, and a process for setting the type of the expansion period is executed. Then, image data expansion processing is started every predetermined period.

  Specifically, as shown in FIG. 34, the GCL 81 specifies the development period of each image based on the index data of the front image A1 and the background image B1 at the development period determination timing, and sets the type of the development period. Set. If the set type is the expansion period A, processing by double buffering is executed. That is, after that, when the start timing of the expansion process arrives, the GCL 81 expands the front image A1 in the front frame buffer A and expands the background image B1 in the background frame buffer A. Then, the GCL 81 generates a composite image G1 obtained by combining the front image A1 and the background image B1 when the composite image generation timing is reached, and displays the composite image G1 on the variable display device 6.

  In addition, the GCL 81 specifies each development period based on the index data of the front image A2 and the background image B2 at the development period determination timing, and sets the type of the development period. If the set type is the expansion period A, processing by double buffering is continued. That is, the GCL 81 then develops the front image A2 in the front frame buffer B and the background image B2 in the background frame buffer B when the development processing start timing comes. Then, the GCL 81 generates a composite image G2 obtained by combining the front image A2 and the background image B2 when the composite image generation timing is reached, and causes the variable display device 6 to display the composite image G2.

  As described above, based on the index data of the front image and the background image at the development period determination timing, the respective development periods are identified sequentially, the type of the development period is sequentially set, and the development period B is set. Until it is done, processing by double buffering is executed. That is, the development of the front image is alternately developed in the front frame buffer A and the front frame buffer B, and the development of the background image is alternately developed in the background frame buffer A and the background frame buffer B.

  Then, the GCL 81 identifies each development period based on the index data of the front image A5 and the background image B5 that has reached the development period determination timing, and sets the type of the development period. Since the set type is the expansion period B, the GCL 81 changes the front buffer designation counter to the processing by triple buffering, and at the same time, the background buffer designation counter (background image processing having the same configuration as the front buffer designation counter). Change counter to triple buffering. That is, the GCL 81 then develops the front image A5 in the front frame buffer C and the background image B5 in the background frame buffer C when the development processing start timing comes. Then, the GCL 81 generates a composite image G5 obtained by combining the front image A5 and the background image B5 when the composite image generation timing is reached, and displays the composite image G5 on the variable display device 6. Thereafter, processing by triple buffering is continuously executed. That is, for the development of the front image, the front frame buffer A to the front frame buffer C are developed in order, and for the development of the background image, the background frame buffer A to the background frame buffer C are developed in order.

  As described above, for each of the front image and the background image, when image data whose development period exceeds the normal development period appears, the configuration is switched from double buffering to triple buffering, so that the image data is efficiently developed. In addition, it is possible to more reliably prevent the occurrence of frame dropping.

  In each of the embodiments described above, the front image has been described as an image including a special symbol image and a character image. However, it is assumed that only one of the images is included, and the other image is included in the background image. It is good also as a structure.

  Specifically, the background image generation unit 304 generates a back image (an image combined on the back side when generating a display image) by combining the background image and the character image, and the front image generation unit 307 A front image composed of special symbol images may be generated, and the images may be combined and displayed on the variable display device 6.

  In addition, as described above, since the frame buffer in which the background image and the character image are developed and the frame buffer in which the special symbol image is developed are separated, the image processing can be performed smoothly, and the identification information It is possible to prevent the fluctuation display of the screen from being affected.

  In the above-described embodiment, the image data used for image display is read from the CGROM 83 when the development start timing is reached in the image control process (see step S912). The specific image data may be developed in a predetermined development area in advance.

  For example, a pre-development area is provided in the front frame buffer 325 for developing and holding specific image data such as frequently used image data, and the effect control means, for example, powers on the gaming machine At this time or when a demonstration display is being performed, the image data of the front image that is frequently used in advance may be read from the CGROM 83 and developed and held in the pre-development area. When using image data developed in advance, the effect control means may copy the image data developed in the advance development area to the front frame buffer.

  By configuring as described above, it is possible to eliminate the need for processing such as expansion when using specific image data in advance by developing and storing it, thereby improving the efficiency of image processing. Can be made. In addition, you may make it expand | deploy not only a front image but a back image in advance.

  In the above-described embodiment, the index data is associated with each image data. However, one index data is added to a group of image data having the same development period (not necessarily the same value). It is good also as a structure matched. In this case, the development period is collectively determined for a group of image data, the determination result is stored, and image display processing for a plurality of corresponding image data is executed based on the stored determination result. do it. With this configuration, it is possible to eliminate the need to determine the development index data for each image data, and it is possible to collectively specify the development period based on the index data for a group of image data. The control burden can be reduced, and the development index data corresponding to each image data can be omitted, so that the data amount can be reduced.

  The group of image data associated with the one index data may be, for example, a series of image data for performing a predetermined effect display related to the game. Specifically, a group of image data associated with one index data is, for example, a special symbol variation display effect (for example, a slide effect, a return effect, a full rotation, etc.) on the variation display device 6 in a predetermined effect mode. A series of image data for performing a predetermined variable display effect using the special symbol of (1) may be used. By configuring in this way, the index data can be associated with the special symbol variation display effect, and even if the variation display of elaborate identification information that takes a long time to develop is performed, the image display can be performed without dropping frames. It can be carried out.

  In addition, a group of image data associated with one index data is, for example, an effect executed when the variable display device 6 is in a predetermined effect mode (executed when the reach state is reached). May be a series of image data for performing, for example, a reach effect in which a character appears or a reach effect by a display in which the character performs a predetermined action. If comprised in this way, index data can be matched with the display mode of reach production, and even if elaborate reach display that requires a long time for development is performed, it can be displayed without dropping frames.

  In the above-described embodiment, among the background image, character image, and special symbol image, one or two images including the background image are set as the back images, and the other images are set as the front images. In the illustrated image control process, the example of performing the image process of the front image including the character image and the special symbol image has been described. The process of step S915 in the image control process will be described in detail. Note that the processing in step S916 and step S928 is the same as the processing in step S915 shown below.

  FIG. 35 is a flowchart showing details of the process in step S915 in the image control process shown in FIG. In step S915, the effect control CPU 101 first confirms priority information between the character image data and the special symbol image data (step S915a). Each image data includes priority information that can specify whether the image data is synthesized on the front side or the image data synthesized on the back side when generating the front image data. . In this example, as the priority information, it is assumed that either the first display layer indicating synthesis on the back side or the second display layer indicating synthesis on the front side is set.

  Next, the effect control CPU 101 develops image data (for example, identification information image data) in which the second display layer is set as priority information (step S915b), and prioritizes the image data so as to overlap the developed image data. Image data (for example, character image data) in which the first display layer is set as information is developed (step S915c). In this way, front image data obtained by synthesizing the identification information image data and the character image data is generated and developed in the front frame buffer.

  As described above, the front image data synthesized by superimposing the identification information image data and the character image data is developed in the front frame buffer so that a plurality of images can be developed in an overlapping manner. Thus, it is possible to display an image with a sense of depth. In addition, when the back image is generated by a plurality of images, it may be developed by the same processing.

  Although not specifically mentioned in the above-described embodiment, in the above-described embodiment, a plurality of types of background image data are stored in the CGROM 83 in advance, and the plurality of background image data are displayed in order. Thus, background effect information indicating a combination (background image data group) of background image data set in advance so as to execute a series of moving image effects is stored in the CGROM 83. Here, for example, 10 types of background effect information 1 to 10 are prepared in advance. When the background effect information 1 is specified (for example, the background effect information 1 is specified when performing a predetermined reach effect), a combination of background image data corresponding to the specified background effect information 1 (background image data group) Is selected. Then, the background image data is sequentially read out from the selected background image data group in a predetermined order (this order is assumed to be included in the background effect information), and is displayed in the variable display device 6. By displaying, a specific moving image effect by the background image is executed. Note that the same background image data is included in the plurality of background image data specified by each background effect information. That is, the same background image data can be used for a plurality of background image effects.

  As described above, a configuration in which a plurality of background image data are combined to perform a series of displays enables various image displays and prevents an increase in the volume of image data. it can. Not only the background image data but also the identification information image data and the character image data may be similarly configured.

  In addition, although not particularly mentioned in the above-described embodiment, the effect by the synthesized image obtained by synthesizing part or all of the background image, the identification information image, and the character image is a movie image (a moving image displayed by moving image reproduction). ) Or a sprite image. Note that the movie image data that is the source of the movie image may be data for reproducing a moving image of a live-action image taken by a movie shooting device, or data for reproducing a movie by animation. Data for reproducing a CG image using computer graphics (CG) drawn by an information processing apparatus such as a computer may be used. When movie image data based on a real image is used, the movement of a person or animal can be expressed realistically. Further, in the case of using movie image data based on CG images, an image can be freely created by computer graphics, so even an image that is difficult to obtain by actual shooting can be easily created. This makes it possible to easily create movie image data including a necessary movie image. Note that movie image data may be created by combining a real image and a CG image.

  Note that the variable display effect that does not depend on the moving image displayed by moving image reproduction is an effect that does not use a movie image, and thus includes, for example, a moving image effect that uses a sprite image. That is, unless the image display is performed by moving image reproduction based on moving image data, for example, the display control unit 80 is configured to include a VDP (video display processor) and does not depend on the moving image displayed by moving image reproduction. As a display effect, the VDP may be configured to display a moving image by generating a composite image obtained by combining a sprite image with a background image and sequentially updating the sprite image. Since sprites are for generating an image to be superimposed on a background image, the screen size is generally small and suitable for use in displaying symbols and the like. Therefore, VDP generally generates identification information as a special symbol that is variably displayed as a sprite image, and generates an image in which the sprite image is superimposed on the background image.

  In addition, when the display control unit 80 is configured to include a VDP, a VDP (a CGROM storing a background image and the like, a background frame buffer, and the like are provided to execute processing of the back image synthesized on the back side. A VDP that executes processing of a front image synthesized on the front side (a CGROM that stores the front image and the like, a front frame buffer, and the like). For example, an SDRAM including two VDPs may be included. In this way, by configuring the images to be displayed on the background side and the front side with dedicated VDP, GCROM, and VRAM, it is possible to specialize in the image generation. A background image can be refined (a heavy image with a large amount of data, an image that takes time to generate an image, etc.), and even if an elaborate image is generated, frame dropping can be prevented.

  In the above-described embodiment, the variable display device 6 is configured to display the special symbols that are the three symbols of the left middle, right, and right. May be configured to display decorative symbols (for example, three symbols on the left, middle, and right similar to the special symbols that do not affect game control depending on the display result).

  In the pachinko gaming machine 1 of the above embodiment, a predetermined game value is given to a player when a special symbol stop symbol that is variably displayed on the variable display device 9 based on the start winning combination is a combination of a predetermined symbol. It was the first type pachinko machine that would be possible. That is, the variable display means displays a plurality of types of identification information in a variable manner, and a specific gaming state (for example, a big hit gaming state) advantageous to the player when the display result of the identification information becomes a specific display result (for example, a jackpot symbol). It was a gaming machine. However, if there is a prize in a predetermined area of the electric game that is released based on the start prize, a second type pachinko gaming machine that can give a player a predetermined game value or a prize in a predetermined electric game The present invention can be applied even to a third type pachinko gaming machine in which a predetermined right generation state occurs or continues if there is.

  In other words, the player plays a game by hitting a game ball into the game area, and is in a first state that is advantageous to the player (for example, an open state) and a second state that is disadvantageous to the player (for example, a closed state). A start game in which a variable winning device is provided, and the variable winning device is controlled from the second state to the first state in a predetermined starting mode based on the fact that the game ball has passed through the starting region provided in the gaming region. Variable winning in a specific manner that is more advantageous to the player than the starting mode based on the fact that the game ball that has won the variable winning device through the starting game has entered a specific region among the plurality of regions provided in the variable winning device. A second-type pachinko gaming machine that generates a specific gaming state for controlling the device from the second state to the first state, in order to notify the number of rounds that can be continued in the specific gaming state, etc. It is also possible to apply the present invention to provided a variable display means for performing variable display game of the gaming machine.

  In addition, the player enters the game area by playing the game ball and enters the right generation state on condition that the game ball is detected by the special detection means provided in the special area. Based on the detection of the game ball by the start detection means provided in the start area during the period, it is possible to perform control to change the variable winning device from a disadvantageous state for the player to a favorable state for the player. A type 3 pachinko game machine capable of displaying a variable display game of identification information in order to notify whether or not the structure of the variable prize-winning device has been determined to allow the game ball to enter the special area. The present invention can also be applied to a gaming machine provided with variable display means for performing.

  Further, the pachinko gaming machine 1 according to the above embodiment is a card reader (CR) type 1 pachinko gaming machine that lends a ball using a prepaid card, but a CR that lends a ball using a prepaid card. It can be applied not only to a pachinko machine but also to a pachinko machine that lends a ball with cash.

  Further, the present invention is not limited to pachinko gaming machines and can be applied to other gaming machines such as a slot machine provided with a variable display device and an image display device separately. That is, the game can be started by setting the number of bets to bet on one game using the game balls, and the display result of the variable display device is derived and displayed. The present invention is applied to an image display device in a slot machine capable of winning according to a display result and having an image display device such as an LCD for displaying an effect image according to a game. be able to.

  Each of the above-described gaming machines is configured to give a predetermined game value to the player when the display result of the variable display in the variable display device becomes a predetermined specific display mode. The game value means, for example, that a variable winning ball apparatus provided in a gaming area of a gaming machine is in an advantageous state for a player who is easy to win, or generates a right to be in an advantageous state for a player. Or a condition that the condition for giving out premium game media is easily established.

It is the front view which looked at the pachinko gaming machine from the front. It is a block diagram which shows the outline | summary of the feature point of a pachinko gaming machine. It is a block diagram which shows the system structural example centering on a game control part. It is a block diagram showing a circuit configuration example of an effect control board. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a special symbol process process. It is a flowchart which shows the main process which CPU for production control performs. It is explanatory drawing which shows the structure of a command reception buffer. It is a flowchart which shows a command analysis process. It is a flowchart which shows production control process processing. It is explanatory drawing which shows the example of 1 structure of process data. It is a flowchart which shows a variation pattern command command reception waiting process. It is a flowchart which shows all the symbol variation start processes. It is a flowchart which shows the process during symbol fluctuation. It is a flowchart which shows all the symbol stop waiting processes. It is a flowchart which shows the example of an index data determination process. It is a flowchart which shows the example of an image control process. It is explanatory drawing which shows the example of a character image, a special symbol image, and a background image. It is explanatory drawing which shows the example of the state of an image synthesis | combination with a background image, a character image, and a special symbol. It is explanatory drawing which shows the example of the display state of a synthesized image with the background image using the front image which synthesize | combined the special symbol image on the front side of the character image. It is explanatory drawing which shows the example of the display state of a synthesized image with the background image using the front image which synthesize | combined the special symbol image on the back side of the character image. It is explanatory drawing which shows the example of the relationship between the confirmation timing of parameter | index data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image. It is explanatory drawing which shows the other example of the relationship between the confirmation timing of parameter | index data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image. It is a block diagram which shows the outline | summary of the feature point of the pachinko game machine which performs triple buffering. It is a flowchart which shows the other example of index data determination processing. It is a flowchart which shows the other example of an image control process. It is explanatory drawing which shows the other example of the relationship between the confirmation timing of parameter | index data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image. It is explanatory drawing which shows the other example of the relationship between the confirmation timing of parameter | index data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image. It is explanatory drawing which shows the other example of the relationship between the confirmation timing of parameter | index data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image. It is explanatory drawing which shows the other example of the relationship between the confirmation timing of parameter | index data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image. It is a block diagram which shows the example of the outline | summary of the feature point of the pachinko game machine which double-buffers also about a background image. It is explanatory drawing which shows the further another example of the relationship between the confirmation timing of parameter | index data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image. It is explanatory drawing which shows the further another example of the relationship between the confirmation timing of parameter | index data, the expansion | deployment timing of a background image and a front image, and the display timing of a synthesized image. It is a flowchart which shows the detail of step S915.

Explanation of symbols

1 Pachinko machine 6 Fluctuating display device (image display device)
30 Main board 33 CPU
60 Lamp control unit 70 Sound control unit 80 Display control unit 81 GCL
83 CGROM
84 SDRAM (VRAM)
100 effect control board 101 effect control CPU
102 ROM

Claims (9)

A gaming machine including an image display device that displays images of a plurality of types of identification information that can identify each of them,
Image generating means for generating a display image to be displayed on the image display device;
A display image storage area for storing display image data including an image of the identification information;
A plurality of display image frame buffers for reading the display image data from the display image storage area and storing the generated display image data;
Buffer switching means for switching a display image frame buffer for storing display image data generated by the image generation means among the plurality of display image frame buffers;
A development index data storage area that stores development index data that is associated with the display image data and that specifies a period of time until the image generation unit generates a display image from the display image data and stores the display image in the display image frame buffer; With
The game machine, wherein the image generation means starts generating a display image from display image data associated before a period specified from the development index data. The gaming machine according to claim 1, wherein the development index data storage area is provided in the display image storage area. The image generation means executes processing for generating a display execution image according to predetermined control data,
A control data storage area for storing the control data;
The gaming machine according to claim 1, wherein the expansion index data storage area is provided in the control data storage area. The image generation means specifies a period until a display image is generated from display image data and stored in the display image frame buffer based on the target development index data before the longest period indicated by the preset development index data. The game machine according to any one of claims 1 to 3. The display image frame buffer includes three frame buffers,
The image generation means
When it is determined that the period specified from the development index data does not exceed the normal development period, the corresponding display image data is alternately developed in the first or second display image frame buffer,
5. The display image data is expanded in a third display image frame buffer when it is determined that the period specified from the expansion index data exceeds the normal expansion period. 5. The gaming machine described in Crab. The game machine according to any one of claims 1 to 5, wherein the development index data is associated with a display image data group in which a plurality of display image data that are continuously used are set as one set. The gaming machine according to claim 6, wherein the display image data group is associated with a variation display mode of identification information. The display image data includes character image data for displaying a character image.
The gaming machine according to claim 6, wherein the display image data group is associated with a display mode for displaying the character image. The image generation means includes a rear image generation means for generating a rear image to be displayed on the image display device, and a front image generation means for generating a front image synthesized on the front side of the rear image displayed on the image display device. Including
The display image storage area includes a back image storage area for storing back image data for generating the back image, and a front image storage area for storing front image data for generating the front image,
The plurality of display image frame buffers include a plurality of back image frame buffers for storing back image data generated by the back image generation means, and a plurality of front images for storing front image data generated by the front image generation means. Frame buffer, and
Buffer switching means includes a back buffer switching means for switching a back image frame buffer for storing back image data generated by the back image generation means among the plurality of back image frame buffers, and a plurality of the front image frame buffers. Front buffer switching means for switching a front image frame buffer for storing front image data generated by the front image generation means,
Image combining means for combining the front image data of the front frame buffer on the upper surface side of the rear image data of the rear image frame buffer,
The development index data is associated with the back image data or / and the front image data,
The back image generation means or the front image generation means generates a display image from the corresponding display image data before a period specified from at least one of the development index data associated with the back image data or the front image data. The gaming machine according to any one of claims 1 to 8, wherein the gaming machine is started earlier than a specified period.