JP2005203617A - Solid state imaging device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance image quality by preventing a parasitic capacitance due to repetitive pitch of dummy pattern from having an effect on the image quality of an output image. <P>SOLUTION: On the same semiconductor chip 2, an imaging region part 120 arranged with a plurality of pixels 110 in two-dimensional array, and a peripheral region part 150 arranged with various logic circuits on the periphery of the imaging region part 120 are provided. In order to make the film thickness uniform in the chip for etching or CMP planarization in the fabrication process, a dummy pattern 160 similar to the pixels of the imaging region part 120 is provided in the peripheral region part 150. Repetitive pitch of the dummy pattern 160 is formed in correspondence with the repetitive pitch of pixels 110 in the imaging region part so that generation state of parasitic capacitance at the peripheral region part is arranged with that at the imaging region part thus preventing the parasitic capacitance from having an effect on the image quality of the output image. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device in which an imaging region portion and a peripheral region portion are provided on the same semiconductor chip, and in particular, in the peripheral region portion in order to ensure in-chip uniformity during various processes such as etching and CME flattening. The present invention relates to a solid-state imaging device provided with a dummy pattern and a manufacturing method thereof.

2. Description of the Related Art Conventionally, for example, in a CMOS type image sensor, an imaging area unit in which a plurality of pixels are arranged in a two-dimensional array, and various logic circuits such as a pixel scanning circuit and a pixel signal processing circuit are arranged around the imaging area unit. The peripheral region portion thus formed is formed on the same semiconductor chip.
In such a solid-state imaging device, basically, pixels are formed in the imaging region portion and output an imaging signal. In the upper layer film forming process, for example, etching, CME flattening, etc. In order to ensure the uniformity within the chip during the processing, a method is adopted in which a dummy pattern is provided in the peripheral area portion and the film thickness with the imaging area portion is matched.

FIG. 3 is an explanatory diagram showing a conventional example of a solid-state imaging device in which a dummy pattern is provided in such a peripheral region.
As shown in the drawing, an imaging region unit 20 in which a plurality of pixels 10 are arranged in a two-dimensional array is provided on a semiconductor chip 1, and various logic circuits (a horizontal selection circuit unit 30 and a vertical selection in the illustrated example) are provided around the imaging region unit 20. A peripheral region portion 50 is provided in which the circuit portion 40 is shown). The peripheral area 50 is provided with a plurality of dummy patterns 60 formed by a process common to the pixels 10 of the imaging area 20 to ensure uniformity such as element distribution and film thickness within the same chip. It has been devised.
Conventionally, the size and pitch of the dummy pattern 60 are fixed in advance regardless of the pitch of the pixels 10 and the like. In the example shown in the drawing, the plane area substantially the same as that of each pixel 10 in the imaging region unit 20 is obtained. The dummy pattern 60 is formed with a unique repeating pattern different from that of the pixel 10.

However, in the above-described conventional solid-state imaging device, when the above-described dummy pattern pitch is generated differently from the pixel pitch, the parasitic capacitance for each column and each row in the pixel selection circuit units 30 and 40 arranged in a matrix form. There is a problem that the transmission state of the signal is distorted due to the influence of the parasitic capacitance, and band-like noise is repeatedly generated in the output image.
Accordingly, an object of the present invention is to provide a solid-state imaging device capable of preventing the parasitic capacitance due to the repetition pitch of the dummy pattern from affecting the image quality of the output image and improving the image quality, and a method for manufacturing the same. To do.

  In order to achieve the above-described object, a solid-state imaging device according to the present invention includes an imaging area unit in which a plurality of pixels are arranged in a two-dimensional array on the same semiconductor chip, and various logic circuits around the imaging area unit. A plurality of dummy patterns formed by a process common to the pixels of the imaging region unit, and a repetition pitch of the dummy patterns of the peripheral region unit. Are formed corresponding to the pitch of the repetitive pattern of the pixels in the imaging region.

  The solid-state imaging device manufacturing method according to the present invention includes an imaging area unit in which a plurality of pixels are arranged in a two-dimensional array on the same semiconductor chip, and a peripheral in which various logic circuits are arranged around the imaging area unit. A solid-state imaging device manufacturing method comprising: providing a region portion; and laminating an upper layer film thereon; and planarizing an upper surface of the upper layer film by CMP processing, wherein the peripheral region portion is shared with the pixels of the imaging region portion In the pixel forming step, the repetition pitch of the dummy pattern in the peripheral region portion is formed in correspondence with the pitch of the repetition pattern of the pixel in the imaging region portion. It is characterized by that.

  According to the solid-state imaging device and the method for manufacturing the same according to the present invention, when a dummy pattern formed in the same process as the pixels in the imaging region is provided in the peripheral region, the repetition pitch of the dummy pattern is set to the pixels in the imaging region. Therefore, the generation state of the parasitic capacitance in the peripheral region portion can be aligned with the generation state of the parasitic capacitance in the imaging region portion. Therefore, it is possible to prevent the parasitic capacitance due to the repeated pattern of the dummy pattern from affecting the image quality of the output image, to obtain an output image without band-like noise, and to improve the image quality.

  In the solid-state imaging device according to the embodiment of the present invention, an imaging region unit in which a plurality of pixels are arranged in a two-dimensional array on the same semiconductor chip, and a peripheral region unit in which various logic circuits are arranged around the imaging region unit In order to make the film thickness in the chip uniform with respect to etching and CMP flattening in the manufacturing process, a dummy pattern similar to the pixels in the imaging region is formed in the peripheral region. Provided. Then, by forming the repetition pitch of this dummy pattern corresponding to the pitch of the repetition pattern of the pixels in the imaging region portion, the parasitic capacitance generation state in the peripheral region portion is aligned with the parasitic capacitance generation state in the imaging region portion. In addition, the parasitic capacitance due to the repetition pitch of the dummy pattern prevents the output image from affecting the image quality, and prevents band noise and the like.

Here, the dummy pattern in the peripheral area is made smaller in size (planar area) than the pixels in the imaging area, and the repetition pitch of the dummy pattern is equal to the pitch of the repeating pattern of the pixels in the imaging area. With the pattern, it is possible to properly and easily align the parasitic capacitance in the imaging region portion and the generation state of the parasitic capacitance in the peripheral region portion.
Also, by making the repetition pitch of the dummy pattern in the peripheral area portion correspond to the pitch of the pixel repetition pattern in both the row direction and the column direction, both horizontal signal transmission and vertical signal transmission are possible. , Noise characteristics can be improved. In particular, by providing a dummy pattern so as to surround the periphery of the pixel selection circuit unit, the operation of the pixel selection circuit unit can be performed smoothly without distortion, and further improved noise characteristics can be achieved.

In the method of manufacturing the solid-state imaging device according to the embodiment of the present invention, the repetition pitch of the dummy pattern in the peripheral region is imaged in the pixel forming step of forming the pixel in the imaging region and the dummy pattern in the peripheral region. By forming in accordance with the pitch of the repetitive pattern of the pixels in the region portion, it is possible to produce the parasitic capacitance generation state in the peripheral region portion so as to be aligned with the parasitic capacitance generation state in the imaging region portion. A solid-state imaging device capable of preventing the parasitic capacitance from affecting the image quality of the output image and preventing band-like noise can be manufactured.
In the design process, the pitch of the repetitive pattern of the pixels in the imaging region corresponding to the repetitive pitch of the dummy pattern in the peripheral region is created as a database in advance as a design rule and incorporated in a design system such as a CAD system. At the time of layout design, by inputting predetermined design conditions on the design system, the repetition pitch of the dummy pattern in the image forming process is determined based on the above design rules. As a result, design without layout errors can be performed, and a solid-state imaging device having excellent characteristics can be easily and stably manufactured.

FIG. 1 is an explanatory diagram showing an element arrangement of a solid-state imaging device according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram showing a circuit configuration of the solid-state imaging device shown in FIG.
As shown in FIG. 1, this solid-state imaging device is an example of a CMOS image sensor. Like the conventional example described above, an imaging region unit in which a plurality of pixels 110 are arranged in a two-dimensional array on a semiconductor chip 2. 120 is provided, and a peripheral region portion 150 provided with logic circuits such as a horizontal selection circuit portion 130 and a vertical selection circuit portion 140 is provided in the periphery thereof. The peripheral area 150 is provided with a plurality of dummy patterns 160 formed by a process common to the pixels 110 of the imaging area 120.
The pixel 110 includes a photodiode as a photoelectric conversion element, and various MOS transistors for reading, amplification, resetting, and the like for reading or resetting signal charges generated by the photodiode at a predetermined timing. In the upper layer, a light shielding film having a light receiving opening, various wiring films, an insulating film, and the like are provided.

  The dummy pattern 160 also has the same configuration as the pattern of the pixel 110, but unlike the MOS transistor of the pixel 110, the electrical connection for reading is not taken and only the stacked structure is common to the pixel 110. As described above, it has a function for maintaining uniformity in the chip during various etchings, CMP planarization, and the like. The dummy pattern 160 is formed in a repetitive pattern with a constant pitch so as to surround the imaging region unit 120 and the horizontal selection circuit unit 130 and the vertical selection circuit unit 140.

Further, as shown in FIG. 2, each pixel 110 provided in the image area unit 120 is scanned by a horizontal selection circuit unit 130 and a vertical selection circuit unit 140, and a pixel signal is output from an output signal line to a column signal conversion circuit unit 170. And is transmitted to the image signal processing circuit unit 180 and sequentially subjected to processing such as D / A conversion, gain adjustment, noise removal, image correction, and the like to be converted into an image signal, and is output from the output terminal 190 to an external device (not shown). Is output.
The example shown in FIG. 2 is merely an example, and the specific configuration such as the pixel signal readout method and where the D / A conversion is performed can be variously modified, and the present invention is not particularly limited. To do.

In the solid-state imaging device of this example, the dimensions and pitch of the dummy pattern 160 are determined corresponding to the repetition pitch of the pixels 110, and as shown in FIG. The pitches α1 and α2 in the direction are equal to the pitches β1 and β2 of the pixels 110 in the imaging region 120.
That is, since the pixels 110 of the imaging region 120 are provided in close contact with each other, the dimensions in the row direction and the column direction of each pixel 110 are substantially equal to the pitches β1 and β2 of the repetitive pattern of each pixel 110. However, the size (plane area) of the portion corresponding to the pixel of the dummy pattern 160 is smaller than that of the pixel 110, the dimensions of the sides of the dummy pattern 160 in the row direction and the column direction are a1, a2, and the intervals are b1, b2. Then, the pitches α1 and α2 in the repeated row and column directions of the dummy pattern 160 are α1 (= β1) = a1 + b1 and α2 (= β2) = a2 + b2.

  Therefore, in such a solid-state imaging device, when the operation of the horizontal selection circuit unit 130 and the vertical selection circuit unit 140 performs an operation of reading a pixel signal from the pixel 110 of the imaging region unit 120, the repetitive pattern of the pixel 110 is changed. Since the pitch and the repetition pitch of the dummy pattern are equal, the generation state of the parasitic capacitance is aligned in the row direction and the column direction in the imaging region portion 120 and the peripheral region portion 150. Therefore, the signal is not affected by the parasitic capacitance. It is possible to perform processing, prevent vertical and horizontal stripe noise on the output screen, and improve image quality.

Next, a method for manufacturing the solid-state imaging device according to this embodiment will be described.
The solid-state imaging device of this example forms elements such as pixels 110, dummy patterns 160, and various MOS transistors on a semiconductor wafer using a CMOS process, as in the prior art, and a technique such as photoresist or etching on the upper layer. Are used to form various upper layer films such as an insulating film, a light shielding film, and a wiring film. Then, planarization such as CMP is performed in the process of forming such an upper layer film, and a color filter and a microlens are formed in an on-chip structure on the planarized upper layer film.

When manufacturing such a solid-state imaging device, the layout design of each element is first performed. As a design rule for this layout design, it is best to correspond to the specification of the pixel size (pitch) of the imaging area part in advance. The size and pitch of a dummy pattern are determined and stored in a database.
In actual design, by designing on the system the pixel size of the imaging area and the element arrangement of the peripheral circuit on the system, information on the dummy pattern automatically created from the database is retrieved. The size and pitch of the dummy pattern are determined based on the search result, and are taken into the system as layout data.

For example, in a solid-state imaging device having a repeating pattern with a pixel pitch of 5 μm in the horizontal direction (row direction) and 4 μm in the vertical direction (column direction), if it is desired to generate a dummy pattern at a density of 25%, the repetition is 5 μm in the horizontal direction and 4 μm in the vertical direction. Design rules are stored in advance so that dummy patterns having a horizontal dimension of 2.5 μm and a vertical dimension of 2 μm are arranged, and the pixel pitch and dummy pattern density are input during layout design. The layout design is executed along the line.
Therefore, by such a method, an optimum dummy pattern can be easily created, layout errors can be prevented, and a solid-state imaging device having excellent operating characteristics can be easily created.

It is explanatory drawing which shows element arrangement | positioning of the solid-state imaging device by the Example of this invention. It is a schematic block diagram which shows the circuit structure of the solid-state imaging device shown in FIG. It is explanatory drawing which shows element arrangement | positioning of the conventional solid-state imaging device.

Explanation of symbols

2 ... Semiconductor chip, 110 ... Pixel, 120 ... Imaging area section, 130 ... Horizontal selection circuit section, 140 ... Vertical selection circuit section, 150 ... Peripheral area section, 160 ... Dummy pattern.

Claims (6)

An imaging area unit in which a plurality of pixels are arranged in a two-dimensional array on the same semiconductor chip, and a peripheral area unit in which various logic circuits are arranged around the imaging area unit.
The peripheral area is provided with a plurality of dummy patterns formed by a process common to the pixels of the imaging area.
The repetition pitch of the dummy pattern in the peripheral area is formed corresponding to the pitch of the repetition pattern of the pixels in the imaging area.
A solid-state imaging device.   The solid-state imaging device according to claim 1, wherein a repetition pitch of the dummy pattern in the peripheral region portion is equal to a pitch of a repetition pattern of the pixels in the imaging region portion.   2. The solid-state imaging according to claim 1, wherein a repetition pitch of the dummy pattern in the peripheral area portion is formed corresponding to a pitch of a repetition pattern of pixels in the imaging area portion in both the row direction and the column direction. apparatus.   The solid-state imaging device according to claim 1, wherein the dummy pattern in the peripheral region portion is provided so as to surround the periphery of the pixel selection circuit portion. After an imaging area part in which a plurality of pixels are arranged in a two-dimensional array and a peripheral area part in which various logic circuits are arranged around the imaging area part on the same semiconductor chip, an upper layer film is laminated on the upper layer A method of manufacturing a solid-state imaging device in which the upper surface of the upper layer film is planarized by CMP processing,
A pixel forming step of providing a plurality of dummy patterns in the peripheral region portion by a step common to the pixels of the imaging region portion;
In the pixel formation step, the repetition pitch of the dummy pattern in the peripheral area is formed corresponding to the pitch of the repetition pattern of the pixel in the imaging area.
A method of manufacturing a solid-state imaging device. The pitch of the repetitive pattern of the pixels in the imaging region corresponding to the repetitive pitch of the dummy pattern in the peripheral region is created as a database in advance as a design rule, and the repetitive pitch of the dummy pattern in the image forming process is determined based on the design rule. 6. The method of manufacturing a solid-state imaging device according to claim 5, wherein the determination is performed.

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