JP2005201691A - Test board for semiconductor evaluation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately measure a high-frequency current leaking from a semiconductor element, without being affected by the shape of the semiconductor shape or the connection state. <P>SOLUTION: This test board 1 formed by laminating three substrates comprises a mounting face (first layer) GND solid 8 layer (second layer), an insulating layer (third layer), and a solder face (fourth layer) where a ball grid 7 is formed. A measuring wire 2 is connected to the third layer by a though hole 5, returned to the inside corresponding to the length portion of the measuring wire 2 on the third layer, and connected to the fourth layer. The wire 2 is connected to the ball grid 7 with a connection wire 3 on the fourth layer, and mounted on a device substrate via it. A micro-strip line structure is formed, by forming the measuring wire 2 on the first layer and the second layer to be GND solid 8, and the characteristic impedance is set at 50Ω. The connection wire 3 on the first layer is connected to the fourth layer by the though hole 5, connected to the ball grid 7 by the connection wire 3 on the fourth layer, and mounted on the device substrate via the ball grid 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a test board structure and a measuring method for easily measuring a high-frequency current leaking from a semiconductor accurately and reproducibly in an actual operation state regardless of the shape of the semiconductor.

  Electromagnetic interference (EMI) caused by a high-frequency current leaking from a semiconductor mounted on a substrate is also called electromagnetic radiation (emission), and adversely affects the surrounding electronic devices such as performance degradation. In order to carry out an effective countermeasure design for suppressing this, it is required to accurately grasp the high-frequency current flowing from the semiconductor. As this type of prior art, for example, the measuring method described in Japanese Patent Laid-Open No. 2000-171504 “Semiconductor Evaluation Apparatus” and Japanese Patent No. 3139478 “IC Socket” can be cited. Hereinafter, both measurement methods will be briefly described with reference to the drawings.

  First, the former prior art will be described with reference to FIG. QFP (Quad-Flat-Package: a type of surface-mount type package. Lead pins come out from all four sides of the package) mounted on the IC socket 10 installed on the test board Has been. On the side surface of the IC socket 10, slits 15 are formed in a one-to-one relationship with the lead pins. By inserting a magnetic field probe 14 such as a sealed dead loop coil type into this slit, measuring the magnetic field of the measurement terminal 13 electrically connected to the lead pin to be measured, and displaying the measurement result by the spectrum analyzer 16, The EMI of IC12 was measured. According to this measurement method, measurement at a position very close to the terminal to be measured is possible, and the reliability of the measurement value is improved.

  Subsequently, the latter prior art will be described with reference to FIG. A semiconductor device 22 is mounted on the test board 21, a printed wiring 23 to which the terminals of the semiconductor device 22 are connected is formed on the surface of the test board 21, and a peripheral circuit that operates the semiconductor device 22 on the back surface side (not shown) and A power circuit is mounted. A magnetic field probe 16 for detecting a magnetic field generated from the printed wiring 23 is provided above the printed wiring 23, and current detection for detecting a high-frequency current flowing through the printed wiring 23 based on the magnitude of the magnetic field detected here. A vessel (not shown) is provided. According to this measurement method, EMI evaluation of a semiconductor device can be performed in the same environment as the state in which the device is normally used, and it is possible to realize EMI evaluation in a state very close to the actual usage state. It becomes.

Japanese Patent No. 3139478

JP 2000-171504 A

  However, the semiconductor evaluation test board disclosed in this prior art publication has the following problems.

  First, in the former measurement method, the impedance characteristics of the connected terminals change due to the difference in the environment in which the semiconductor is mounted, or the measurement point of the magnetic probe such as the shielded loop coil type is the upper part of the semiconductor terminal or It may touch the upper part of the wiring extending from the terminal. In order to compare all the measured values as absolute values, it is necessary to improve the reliability of the measured values and measure the absolute values accurately and with reproducibility. At present, the main noise source in EMC (Electric-Magnetic-Compatibility) is a semiconductor. By measuring and grasping the high-frequency current leaking from this semiconductor, the design considering the amount of generated noise is possible. It is said that. However, when high-frequency current leaking from a semiconductor mounted on an actual device board or IC socket is measured with a magnetic probe such as a shielded loop type, the measured value differs depending on the environment in which the semiconductor is mounted. The problem is that the measurement of the value becomes impossible.

  Second, when a BGA (Ball-Grid-Array = ball grid array) is mounted on an actual device substrate, the ball grid may be directly connected to the inner layer of the substrate. In this case, there may be no measurement point in a magnetic probe such as a shielded loop coil type. Even when mounted on an IC socket or the like, there is no IC socket capable of measuring the ball grid existing inside the BGA, and measurement is not possible. Therefore, when the shape of the semiconductor mounted on the actual device board or IC socket is BGA, if the leaking high-frequency current is measured with a magnetic field probe such as a shielded loop coil, there are some terminals that cannot be measured. It will be.

  Third, since the test board used in the latter measurement method is intended to measure high-frequency current leaking from a single semiconductor, it is made into a board with peripheral circuits and measurement wiring that allow the semiconductor to operate at a minimum. ing. Therefore, it is possible to measure the high-frequency current that leaks from a single semiconductor, but strictly speaking, it does not measure the high-frequency current that leaks in the actual operating state. Measurements cannot be made accurately.

  The object of the present invention is to improve the reliability of measured values by enabling a high-frequency current leaking from a semiconductor in an actual operating state to be measured accurately and reproducibly regardless of the shape of the semiconductor by a new test board structure. It is to realize a semiconductor evaluation test board that can be used for design and countermeasures in consideration of noise.

  Another object of the present invention is to simplify the measurement and improve the operability by using the semiconductor evaluation test board of the present invention.

  In view of the above problems, the test board for semiconductor evaluation of the present invention has a terminal for supplying power or an electrical signal to the QFP type semiconductor element mounted on the surface, and in the vicinity of the terminal while the semiconductor element is mounted. A semiconductor evaluation test board for measuring a high-frequency current emitted from the semiconductor element by bringing a magnetic field probe into contact with the semiconductor element in a non-contact state, and laminating three substrates, the first substrate on which the QFP semiconductor is mounted and the middle substrate A test board in which a GND solid layer is sandwiched in the gap with the second substrate, and an insulating layer is sandwiched in the gap between the second substrate and the lower third substrate, and the first substrate surface side Compared with the connection terminal, the first connection terminal formed in the vicinity of the QFP type semiconductor element mounting region and the periphery of the QFP type semiconductor element mounting region on the surface side of the first substrate are compared with the connection terminal. The measurement terminal formed to extend long in the outer peripheral direction of the substrate, and the connection terminal and the measurement at a position corresponding to the QFP-type semiconductor element mounting region on the first substrate surface side on the back surface side of the third substrate A second connection terminal formed in a one-to-one correspondence with the terminal, and a through hole drilled from the forefront of the measurement terminal and the first connection terminal. The through-hole drilled from the foremost end is drilled from the foremost end with the measurement terminal through the three-layer substrate so as to linearly connect to secure the electrical connection with the second connection terminal. The through hole is formed from the forefront of the second connection terminal via a connection wiring having a length that cancels out the difference in length between the measurement terminal inserted into the insulating layer and the first connection terminal. Secure through hole and electrical connection It is.

  As another example of the configuration of the test board for semiconductor evaluation of the present invention, there is a terminal for supplying power or an electrical signal to a BGA type semiconductor element mounted on the surface, and the terminal is mounted with the semiconductor element mounted. A first board on which three substrates are stacked and the BGA type semiconductor is mounted on a test board for semiconductor evaluation that measures a high-frequency current emitted from the semiconductor element by bringing a magnetic field probe close to the substrate in a non-contact state A test board in which a GND solid layer is sandwiched in the gap between the first substrate and the middle second substrate, and an insulating layer is sandwiched in the gap between the second substrate and the third lower substrate, and the surface of the first substrate The first connection terminal formed on the inner side of the BGA type semiconductor element mounting region on the side, and the outer side of the BGA semiconductor element mounting region on the surface side of the first substrate, as compared with the connection terminal. A measurement terminal formed to extend in the outer peripheral direction of one substrate, and a position corresponding to the BGA type semiconductor element mounting region on the first substrate surface side on the back surface side of the third substrate; A second connection terminal formed corresponding to the measurement terminal on a one-to-one basis, and a through hole drilled from the forefront of the measurement terminal and the first connection terminal. A through-hole drilled from the forefront of the hole penetrates the three layers of the substrate so as to be connected in a straight line to ensure electrical connection with the second connection terminal, and is drilled from the forefront of the measurement terminal. The through-hole is drilled from the forefront of the second connection terminal through a connection wiring having a length that cancels out the difference in length between the measurement terminal inserted into the insulating layer and the first connection terminal. To ensure electrical connection with through-holes It is set to.

  By using the semiconductor evaluation test board of the present invention, the following effects can be obtained.

  First, the semiconductor device can be mounted on the test board for semiconductor evaluation regardless of the shape of the semiconductor device, and the characteristic impedance of the measurement wiring is unified (50Ω in the embodiment of the present invention), so that the measurement is mounted. It became possible without being influenced by the environment. In addition, the absolute value can be measured.

  Next, by preparing two types of test boards for semiconductor evaluation, one corresponding to the QFP shape and the other corresponding to the BGA shape, it was possible to measure all terminals for all semiconductor shapes.

  Third, the test board for semiconductor evaluation is miniaturized as close as possible to the shape of the semiconductor, and a ball grid that can be easily mounted on an actual device board is provided on the solder surface, so that the normal semiconductor single-chip mounting state can be obtained. By making the measurement wiring shapes almost the same and unifying the measurement wiring shapes, it became possible to measure absolute values in actual operating conditions.

  Hereinafter, an embodiment of a semiconductor evaluation test board of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 1 (or FIG. 2), it is composed of a semiconductor evaluation test board 1 using a substrate having four or more layers and a ball grid 7 for mounting on an apparatus substrate. The difference between the two is based on the shape of the semiconductor to be mounted. FIG. 1 shows a “QFP shape type”, and FIG. 2 shows a “BGA (a type of surface mount type package. Spherical solder is arranged in an array on the back of a printed wiring board. Each shows a test board called “shape type” instead of lead.

  FIG. 1A shows a component mounting surface (first layer) of a QFP-shaped type semiconductor evaluation test board 1, and has a measurement wiring (having a measurement length) connected to a terminal for measurement. 2) A connection wiring 3 connected to a terminal not to be measured, a pad 4 used for mounting a semiconductor lead pin, and a through hole 5 for dropping the measurement wiring 2 and the connection wiring 3 into the inner layer. It is installed.

  As the inner layer of the test board 1 goes downward from the first layer, a GND plane 8 (second layer) sandwiched between the test boards, an insulating layer (third layer) sandwiched between the next test boards, balls It is assumed that the solder surface (fourth layer) on which the grid 7 is formed.

  FIG. 1B is a cross-sectional view taken along the line A-A ′ in FIG. 1A, and shows the respective layer configurations of the measurement wiring 2, the connection wiring 3, the through hole 5, and the GND solid 8. The measurement wiring 2 is connected to the second layer through the through hole 5, is returned inward by the length of the measurement wiring 2 in the third layer, and is connected to the fourth layer again through the through hole 5. Further, in the fourth layer, the ball grid 7 is connected by the connection wiring 3. The test board 1 is mounted on a device board (not shown) via the ball grid 7. Furthermore, the measurement wiring 2 of the first layer and the second layer are set to the GND solid 8 to form a microstrip line structure, and this characteristic impedance is set in advance to be 50Ω.

  The connection wiring 3 in the first layer is connected to the fourth layer through the through hole 5, and then connected to the ball grid 7 by the connection wiring 3 in the fourth layer. The test board 1 is mounted on the apparatus substrate via the ball grid 7.

  FIG. 1C is a cross-sectional view taken along the line B-B ′ of FIG. 1A and shows a layer structure of the connection wiring 3 (GND). The GND connection wiring 3 is connected to the second-layer GND solid 8 through the through-hole 5, and is directly connected to the fourth layer through the through-hole 5 penetrating the third layer. The fourth layer is connected to the ball grid 7 by the connection wiring 3. The test board 1 is mounted on the apparatus substrate via the ball grid 7.

  FIG. 1D shows the solder surface (fourth layer) side of the semiconductor evaluation test board 1 of the QFP shape type. In the layer configuration of FIG. 1B and FIG. 1C, through holes corresponding to the total number of terminals of the semiconductor are formed, and each is connected to the ball grid 7 by connection wiring 3. The test board 1 is mounted on the apparatus substrate via the ball grid 7.

  Next, the configuration of the BGA shape type semiconductor evaluation test board will be described in detail with reference to FIG. FIG. 2A shows the component surface (first layer) of the test board 1 for semiconductor evaluation. Similar to the QFP shape type of FIG. 1, the BGA mounting pad 4 and the measurement connected to the terminal to be measured are shown. A wiring (having a length for measurement) 2, a connection wiring 3 connected to a terminal that does not perform measurement are provided, and a through hole 5 is provided for dropping the measurement wiring 2 and the connection wiring 3 into the inner layer. Has been. The second to fourth layers have the same configuration as the QFP shape type shown in FIG.

  FIG. 2B is a cross-sectional view taken along the line C-C ′ of FIG. 2A, and shows the respective layer configurations of the measurement wiring 2, the connection wiring 3, the through hole 5, and the GND solid 8. Since it is a structure for the BGA shape type, the measurement wiring 2 inside the BGA passes through between the pads 4 in the first layer and is wired near the outer periphery of the substrate, and conversely, the connection wiring 3 is the pad 4 in the first layer. Wired at the center or the center of the BGA and connected to the through-holes 5 respectively. The measurement wiring 2 is connected to the third layer through the through hole 5, is returned to the inner side by the length of the measurement wiring in the third layer, and is connected to the fourth layer again through the through hole 5. The fourth layer is connected to the ball grid 7 by the connection wiring 3 and further mounted on the apparatus substrate via the ball grid 7. Further, the measurement wiring 2 of the first layer and the second layer are made of a solid GND 8 to form a microstrip line structure, and the characteristic impedance is adjusted to be 50Ω. The connection wiring 3 is connected to the fourth layer through the through-hole 5, and the fourth layer is connected to the ball grid 7 through the connection wiring 3, and is further mounted on the device substrate via the ball grid 7.

  FIG. 2C shows the layer structure of the GND wiring in the D-D ′ cross section of FIG. Due to the shape of the BGA, the terminals inside the BGA (the region surrounded by the dotted line in FIG. 2A) are through-holes at the position between the pads 4 in the first layer or at the center of the BGA by the GND connection wiring 3. Wiring up to 5 is performed. The GND connection wiring 3 is also connected to the fourth layer through the through hole 5. The fourth layer is connected to the ball grid 7 by the connection wiring 3 and is further mounted on the device substrate via the ball grid 7.

  FIG. 2D shows the solder surface (fourth layer) of the BGA-shaped type semiconductor evaluation test board 1. 2 (b) and 2 (c), through holes 5 corresponding to the total number of terminals of the semiconductor are formed, and each of the through holes 5 is connected to a ball grid 7 by connection wirings 3. 7 is mounted on the apparatus substrate.

  Next, the operation of the present invention will be described in detail with reference to the drawings.

  As shown in FIG. 3, when the semiconductor shape is a QFP shape type, the test pad 2 for semiconductor evaluation of the present invention in which the semiconductor (QFP) 6 is mounted on the device substrate is mounted on the mounting pad 4 with the ball grid 5 interposed therebetween. Solder and mount to. Then, at the measurement point closest to the through hole of the measurement wiring 3, the contact terminal of the magnetic probe 14 such as a shielded loop coil type is brought into contact, and the coaxial cable 9 is connected to the spectrum analyzer 16 to perform measurement.

  The semiconductor evaluation test board according to the present invention increases in the number of terminals and the number of measurement wirings depending on the shape of the semiconductor to be measured, as described using a form using four or more layers of substrates. The present invention can be applied even in the case of using a multi-layered substrate such as 6 layers or 8 layers. Moreover, it is not limited to a board | substrate, The structure using a mold raw material may be sufficient.

  For the measurement using the test board for semiconductor evaluation, a structure in which a magnetic probe such as a shielded loop coil type is previously attached to the test board for semiconductor evaluation may be employed.

  Further, although an example in which the impedance characteristic is adjusted to 50Ω with the microstrip line structure has been described, it goes without saying that the transmission line characteristic can be appropriately changed to 75Ω or 150Ω depending on the actual operating conditions of the device substrate.

It is a figure which shows embodiment of the test board for semiconductor evaluation (4 layer board | substrate, QFP shape type) of this invention, (a) is the top view seen from the 1st layer side, (b) is AA 'sectional drawing (C), BB 'sectional drawing, (d) is the top view seen from the 4th layer side. It is a figure which shows embodiment of the test board for semiconductor evaluation (4 layer board | substrate, BGA shape type) of this invention, (a) is the top view seen from the 1st layer side, (b) is CC 'sectional drawing (C) is DD 'sectional drawing, (d) is the top view seen from the 4th layer side. It is an image figure which shows the high frequency current measuring method using the test board for semiconductor evaluation (QFP shape type) of this invention. It is an image figure which shows the high frequency current measuring method using the test board for semiconductor evaluation (BGA shape type) of this invention. It is a figure which shows the conventional measuring method which uses IC socket. It is a figure which shows the conventional measuring method which uses a test board.

Explanation of symbols

1 Test Board 2 Measurement Wiring 3 Connection Wiring 4 Pad 5 Through Hole 6 Semiconductor (QFP Shape Type)
7 Ball grid 8 GND solid 9 Coaxial cable 10 IC socket 11 Test board 12 IC (QFP shape type)
13 Measurement Terminal 14 Magnetic Field Probe 15 Slit 16 Spectrum Analyzer 21 Test Board 22 Semiconductor Device 23 Printed Wiring

Claims (2)

A terminal for supplying electric power or an electrical signal to a QFP type semiconductor element mounted on the surface; a magnetic field probe is brought close to the terminal in a non-contact state while the semiconductor element is mounted; About the test board for semiconductor evaluation that measures high frequency current
At least three substrates are stacked, and a GND solid layer is sandwiched between the first substrate on which the QFP semiconductor is mounted and the middle second substrate, and further, the second substrate and the lower third substrate A test board in which an insulating layer is sandwiched in the gap;
A first connection terminal formed in the vicinity of the QFP type semiconductor element mounting region on the surface side of the first substrate;
Similarly, a measurement terminal formed in the periphery of the QFP-type semiconductor element mounting region on the surface side of the first substrate and extending longer in the outer peripheral direction of the first substrate than the connection terminal;
A second connection formed in a one-to-one correspondence with the connection terminal and the measurement terminal at a position corresponding to the QFP type semiconductor element mounting region on the back surface side of the third substrate on the front surface side of the first substrate. A terminal,
A through hole formed from the forefront of the measurement terminal and the first connection terminal;
A through-hole drilled from the forefront of the first connection terminal penetrates the three layers of the substrates so as to be connected in a straight line, and ensures electrical connection with the second connection terminal. The through hole drilled from the forefront is connected to the second connection terminal through a connection wiring having a length that cancels out the difference in length between the measurement terminal inserted into the insulating layer and the first connection terminal. A test board for semiconductor evaluation characterized by ensuring electrical connection with through-holes drilled from the cutting edge. A terminal for supplying electric power or an electrical signal to a BGA type semiconductor element mounted on the surface; a magnetic field probe is brought close to the terminal in a non-contact state while the semiconductor element is mounted; About the test board for semiconductor evaluation that measures high frequency current
At least three substrates are stacked, and a GND solid layer is sandwiched between the first substrate on which the BGA type semiconductor is mounted and the middle second substrate, and further, the second substrate and the lower third substrate A test board in which an insulating layer is sandwiched between the gaps,
A first connection terminal formed inside the BGA type semiconductor element mounting region on the surface side of the first substrate;
Similarly, on the outside of the BGA semiconductor element mounting region on the surface side of the first substrate, a measurement terminal formed to extend longer in the outer peripheral direction of the first substrate than the connection terminal;
A second connection formed in a one-to-one correspondence with the connection terminal and the measurement terminal at a position corresponding to the BGA type semiconductor element mounting region on the back surface side of the third substrate on the front surface side of the first substrate. A terminal,
A through hole formed from the forefront of the measurement terminal and the first connection terminal;
A through-hole drilled from the forefront of the first connection terminal penetrates the three layers of the substrates in a straight line so as to ensure electrical connection with the second connection terminal, and the measurement terminal. The through hole drilled from the forefront is connected to the second connection terminal through a connection wiring having a length that cancels out the difference in length between the measurement terminal inserted into the insulating layer and the first connection terminal. A test board for semiconductor evaluation characterized by ensuring electrical connection with through-holes drilled from the cutting edge.

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