JP2005196046A - Generation/verification method and system for electron beam drawing data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a generation/verification method and system for electron beam drawing data capable of speeding up drawing data generation/verification processing by concurrently executing drawing data generation and drawing data verification while cooperating both. <P>SOLUTION: The generation/verification method for the electron beam drawing data comprises generating the electron beam drawing data for performing drawing by using an electron beam on an object to be exposed and verifying the generation. After the generation processing of the electron beam drawing data is executed relating to only the portion of layout data and before the generation processing of the electron beam drawing data relating the remaining portion of the layout data, the verification processing of the electron beam drawing data generated relating only to the portion is executed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a creation verification method and a creation verification apparatus for electron beam drawing data, and more particularly, to a creation verification method and a creation verification apparatus for electron beam drawing data capable of verifying drawing data used for manufacturing a semiconductor device or the like in a short time. .

  With the improvement in performance of semiconductor integrated circuits, the miniaturization of patterns has been rapidly advanced. The drawing method using an electron beam (EB) is being put to practical use because it can form a fine pattern with a width of 0.25 micrometers or less that will be required in the future.

  In order to perform drawing with an electron beam, it is necessary to convert the layout data of the semiconductor integrated circuit into electron beam drawing data (hereinafter abbreviated as “drawing data”) and to verify the created drawing data.

FIG. 8 is a schematic diagram illustrating the flow of creating and verifying drawing data.
That is, the drawing shows drawing data creation processing S1 and verification processing S6 that are performed when an exposure mask such as a “master reticle” is formed.
First, the layout of the semiconductor integrated circuit is designed, and layout data LD is created. The layout data LD is sometimes referred to as “CAD (computer aided design) data”.

  The layout data LD is converted into drawing data DD through the creation process S1. The contents will be described. First, the layout data LD is hierarchically expanded as required (step S2), and then various graphic calculation processes (step S3) are performed. Then, pattern division into the drawing unit area (step S4) is performed, and drawing data DD is created by drawing data format conversion (step S5).

The drawing data DD created in this way is then verified by a verification process S6 (for example, Patent Document 1). In other words, the created drawing data DD is inversely converted into a layout data figure in step S7 by an inverse operation process that is the reverse of the figure operation performed at the time of drawing data creation. The data thus obtained and the layout data LD are subjected to pattern comparison in step S8. The pattern that does not match is the error location. When an error is detected, whether there is any defect or error in drawing data creation or drawing data verification is appropriately analyzed.
JP 2001-344302 A

  However, according to the above-described method, there is a problem that it takes a processing time because the drawing data creation process and the verification process are performed in series.

FIG. 9 is a schematic diagram showing the processing order of the drawing data creation process S1 and the drawing data verification process.
FIG. 10 is a schematic diagram showing the time required for the drawing data creation process S1 and the drawing data verification process S6.

  As shown in these drawings, the drawing data verification process S6 is executed after the drawing data creation process S1. For this reason, even if drawing data creation has been completed, drawing has to be waited until drawing data verification that requires processing time equivalent to drawing data creation is completed. As the LSI (Large Scale Integrated circuit) is miniaturized and scaled up, the period required for creating drawing data for an electron beam drawing apparatus for mask manufacturing has also become longer. Further, in order to improve the quality of drawing data, verification processing for the created drawing data is indispensable, which has spurred an increase in drawing data processing time.

  The present invention has been made on the basis of recognition of such a problem. The object of the present invention is to perform drawing data creation / verification processing at high speed by executing them in parallel while coordinating drawing data creation and drawing data verification. An object of the present invention is to provide a creation verification method and creation verification apparatus for electron beam drawing data that can be realized.

  In the embodiment of the present invention, the entire LSI chip is divided into small areas corresponding to the drawing unit areas, and the drawing data verification process of the area where the drawing data generation process is completed is changed to the drawing data generation process of another area. To be executed in parallel. Since most of the drawing data verification processing is completed during the drawing data creation processing, the same effect as when the drawing data verification time is shortened can be obtained. According to the present invention, it is possible to speed up drawing data processing.

That is, according to the present invention, a method for creating and verifying electron beam drawing data for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
An electron beam created for only a part of the layout data after the creation process of the electron beam drawing data for only a part of the layout data and before the creation of the electron beam drawing data for the remaining part of the layout data is completed. An electron beam drawing data creation / verification method is provided, which performs a drawing data verification process.

Alternatively, an electron beam drawing data creation verification method for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
If the data amount of the layout data is equal to or greater than a predetermined value, the generation process of the electron beam drawing data is executed for only a part of the layout data, and then the electron beam drawing data for the remaining part of the layout data is Before the creation process is completed, the verification process of the electron beam drawing data created for only the part is executed,
When the data amount of the layout data is smaller than a predetermined value, the electron beam drawing data verification process is executed after the electron beam drawing data creation process is executed for the entire layout data. A method for creating and verifying electron beam drawing data is provided.

  Alternatively, a method for creating and verifying electron beam drawing data for creating and verifying electron beam drawing data for drawing on an object to be exposed using an electron beam, the step of dividing layout data into a plurality of processing unit regions; A step of executing creation processing of electron beam drawing data for a first processing unit region of the plurality of processing unit regions, and electron beam drawing data for a second processing unit region of the plurality of processing unit regions A method for verifying the electron beam drawing data created for the first processing unit region while executing the creation process. The

Alternatively, a method of creating and verifying electron beam drawing data for creating and verifying electron beam drawing data for drawing on an object to be exposed using an electron beam, the step of calculating the amount of layout data, and the layout A first creation verification step that is performed when the data amount of the data is equal to or greater than a predetermined value; and a second creation verification step that is performed when the data amount of the layout data is smaller than the predetermined value. Prepared,
The first creation verification step includes a step of dividing layout data into a plurality of processing unit regions, and a step of executing electron beam drawing data creation processing for the first processing unit region of the plurality of processing unit regions. And a verification process of the electron beam drawing data created for the first processing unit area while executing the electron beam drawing data creation process for the second processing unit area of the plurality of processing unit areas. Including a process,
The second creation verification step includes a step of executing generation processing of electron beam drawing data for the entire layout data, and a step of executing verification processing of the electron beam drawing data generated for the entire layout data. , And a method for creating and verifying electron beam drawing data.

Here, in the step of dividing into the plurality of processing unit areas, the division may be performed such that the data amounts of the plurality of processing unit areas are substantially uniform.
Each of the plurality of processing unit areas can be composed of one or a plurality of drawing unit areas.
Further, the number of the drawing unit areas included in any one of the plurality of processing unit areas may be different from the number of the drawing unit areas included in any other of the plurality of processing unit areas. .
In addition, at least one of the creation process and the verification process can be performed in parallel by a plurality of processing means.

On the other hand, according to the present invention, an electron beam drawing data creation verification apparatus for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
An electron beam created for only a part of the layout data after the creation process of the electron beam drawing data for only a part of the layout data and before the creation of the electron beam drawing data for the remaining part of the layout data is completed. An apparatus for verifying the creation of electron beam drawing data, characterized in that it is configured to execute drawing data verification processing, is provided.

  Alternatively, according to the present invention, there is provided an electron beam drawing data creation verification apparatus for creating and verifying electron beam drawing data for drawing on an object to be exposed using an electron beam, wherein the amount of layout data is predetermined. If the value is equal to or greater than the value, after executing the electron beam drawing data creation process for only a part of the layout data, before the electron beam drawing data creation process for the remaining part of the layout data is completed. When the verification process of the electron beam drawing data created for only the part is executed and the amount of layout data is smaller than a predetermined value, the electron beam drawing data creation process is performed for the entire layout data. An apparatus for verifying the creation of electron beam drawing data is provided, which is configured to execute verification processing of electron beam drawing data after execution.

  Alternatively, according to the present invention, there is provided an electron beam drawing data creation verification apparatus for creating and verifying electron beam drawing data for drawing on an object to be exposed using an electron beam. An electron beam drawing data creation process is executed for a first processing unit area of the plurality of processing unit areas, and an electron beam is generated for a second processing unit area of the plurality of processing unit areas. Provided is an electron beam drawing data creation verification device configured to execute verification processing of electron beam drawing data created for the first processing unit area while executing drawing data creation processing. Is done.

Alternatively, according to the present invention, there is provided an electron beam drawing data creation and verification device for creating and verifying electron beam drawing data for drawing on an object to be exposed using an electron beam, and calculating a data amount of layout data When the data amount of the layout data is greater than or equal to a predetermined value, a first creation verification process is performed. When the data amount of the layout data is smaller than the predetermined value, the second creation verification is performed. The first creation verification process includes a step of dividing layout data into a plurality of processing unit areas, and creation of electron beam drawing data for the first processing unit area of the plurality of processing unit areas. A step of executing the process, and an electron beam drawing data creation process for the second process unit area of the plurality of process unit areas, while the electron beam drawing data created for the first process unit area is created. Wherein the step of performing the verification processing of the line drawing data, and
The second creation verification step includes a step of executing generation processing of electron beam drawing data for the entire layout data, and a step of executing verification processing of the electron beam drawing data generated for the entire layout data. , A device for verifying the creation of electron beam drawing data is provided.

  Here, when dividing into the plurality of processing unit areas, the data amounts of the plurality of processing unit areas may be divided so as to be substantially uniform.

Each of the plurality of processing unit areas can be composed of one or a plurality of drawing unit areas.
Further, the number of drawing unit areas included in each of the plurality of processing unit areas may not be the same.
In addition, a plurality of processing means may be provided, and at least one of the creation process and the verification process may be processed in parallel by the plurality of processing means.

  According to the present invention, if layout data is divided into a plurality of processing unit areas, and drawing data can be created and verified for each processing unit area, the entire drawing data of the layout data can be created. In addition, an error included in the drawing data can be detected. If an error is detected in the verification process, the drawing data generation can be stopped immediately and the drawing data can be recreated or repaired, reducing unnecessary processing and greatly reducing process time. It becomes possible to do.

  Furthermore, according to the present invention, the drawing data creation process and the verification process can be performed in parallel, and the total processing time can be greatly reduced.

  As a result, it is possible to reliably carry out ultra-fine processing with high speed and high yield, and there are great industrial advantages.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic view illustrating the flow of a method for creating and verifying electron beam drawing data according to an embodiment of the present invention.

  In the present embodiment, first, in the drawing data creation process S1, layout data LD is input, and the layout data LD is divided and processed. For example, one processing unit area is set with the drawing unit area as a basic area. The processing unit area to be set is set (step S11). Then, for each processing unit area divided in this way, hierarchical expansion (step S2), figure calculation (step S3), drawing area division (step S4)), and drawing data format conversion (step S5) are performed. The divided drawing data 12 is created for each unit. A determination is made as to whether or not drawing data has been created for all processing unit areas (step S13), and a series of processes from hierarchical development (step S2) to drawing data format conversion (step S5) for unprocessed processing unit areas. Repeat the process. When the divided drawing data 12 for all the processing unit areas has been created, merging (step S14) is performed to create the drawing data DD.

  On the other hand, in the drawing data verification process S6, the divided drawing data 12 created for each processing unit area is input as needed, and the inverse operation process (step S7) of the graphic operation performed at the time of drawing data creation is performed. Further, the data of the processing unit area corresponding to the divided drawing data 12 is extracted from the layout data LD (step S15). Then, pattern comparison (step S8) is performed between the data extracted from the layout data LD and the data obtained by the inverse calculation process. The above verification processing is executed for all processing unit areas.

  As described above, if the layout data LD is divided into a plurality of processing unit areas and the drawing data can be created and verified for each processing unit area, the entire drawing data of the layout data LD can be created. In addition, an error included in the drawing data can be detected. If an error is detected in the verification process, the drawing data generation can be stopped immediately and the drawing data can be recreated or repaired, reducing unnecessary processing and greatly reducing process time. It becomes possible to do.

  Furthermore, according to the present embodiment, the creation process S1 and the verification process S6 can be performed in parallel, and the total processing time can be greatly reduced.

FIG. 2 is a schematic diagram showing the first embodiment of the present invention.
That is, in the case of the specific example shown in FIG. 5A, the layout data LD is divided into 15 drawing unit areas 1 to 15. First, the drawing unit areas 1 to 3 in the first column are set as one processing unit area, and layout data is input to create divided drawing data.

  Here, the “drawing unit area” is also called a “field” or “subfield”, and is a size determined by the hardware or software specifications of the drawing apparatus (usually a rectangular area with a side of about 1 mm). It is. Specifically, from the viewpoint of hardware, there may be a range where drawing can be performed by electromagnetic deflection or electrostatic deflection without moving the stage of the drawing apparatus. From the viewpoint of software, it may be determined by the number of bits representing the position of the pattern, the buffer memory size, or the like. In general, as the drawing unit area is reduced, the drawing accuracy is improved, but the drawing time is increased.

Since it is necessary to divide the pattern between adjacent drawing unit areas, it is not necessary to add a new division boundary for the processing unit area.
At this time, in order to guarantee the pattern connection at the boundary between the drawing unit areas 1 to 3 and the drawing unit areas 4 to 6, the layout data of the overlapped area is input and processed. For example, when creating drawing data for the drawing unit areas 1 to 3, drawing data may be created for areas including a part of the adjacent drawing unit areas 4 to 6.

On the other hand, in the specific example shown in FIG. 2B, the layout data LD is divided in the horizontal direction to form five drawing unit regions 1 to 5. In this case, for example, each of the drawing unit areas 1 to 5 can be assigned as a processing unit area. Also in this case, the pattern connection at the boundary can be guaranteed by including the overlapped area at the boundary between the drawing divided areas.
The present invention can be applied to both FIG. 2A and FIG. 2B, but will be described below with reference to a specific example divided into 15 drawing unit areas as shown in FIG.

  When the divided drawing data creation of the drawing unit areas 1 to 3 is completed, the divided drawing data creation of the drawing unit areas 4 to 6 is started. At that time, the drawing data verification processing of the drawing unit areas 1 to 3 is started in parallel. Finally, the drawing data verification processing for the drawing unit areas 13 to 15 is completed, and all drawing data processing is completed.

FIG. 3 is a schematic diagram showing the flow of processing in this embodiment in time series.
In this embodiment, the layout data LD is divided into a plurality of processing unit areas, and the drawing data creation process S1 and the drawing data verification process S6 are performed in parallel, so that the processing time of the entire drawing data creation / verification process is as follows. The drawing data creation time can be shortened to + α. Here, α is limited by the processing time of the maximum processing unit area.

  FIG. 4 is a schematic diagram showing a second embodiment of the present invention. That is, this figure is a schematic diagram showing the flow of drawing data creation processing and drawing data verification processing in time series.

  Also in this embodiment, drawing data is created from the layout data LD divided into 15 drawing unit areas 1 to 15 as shown in FIG. Further, in the present embodiment, when the processing unit area is set (step S11 in FIG. 1) at the top of the drawing data creation process S1, the processing scale of each processing unit area is included so as to be approximately the same. Adjust the number of drawing unit areas to be displayed. That is, adjustment is made so that the data amount or the data scale of each processing unit area is approximately the same.

  In the specific example shown in FIG. 4, the number of drawing unit areas of the first processing unit area is 2 (drawing unit areas 1 and 2), and the number of drawing unit areas of the last processing unit area is 4 (drawing unit area 12). To 15), equalization is performed.

  In this way, the drawing data creation process (S1) and the verification process (S6) can be made substantially uniform for each processing unit area, so that the “waiting time” can be reduced and a rapid process can be performed. For example, the drawing data creation process (S1) for the drawing unit areas 1 and 2 ends, and while the verification process (S6) proceeds, the drawing data creation process (S1) for the drawing unit areas 3 to 5 is performed in parallel. Let Then, when the drawing data verification process (S6) for the drawing unit areas 1 and 2 is completed, the creation of the drawing data of the drawing unit areas 3 to 5 is completed almost simultaneously, and this can be immediately verified (S6). .

  In the case of the first embodiment described above with reference to FIGS. 2 and 3, the processing time of the entire drawing data creation / verification process is the drawing data creation time + α, and α is limited by the processing time of the maximum processing unit area. On the other hand, according to the second embodiment, by equalizing the data amount of the processing unit area, α is reduced, so that the entire processing time is also shortened.

  FIG. 5 is a schematic diagram showing a third embodiment of the present invention. That is, this figure is also a schematic diagram showing the flow of drawing data creation processing and drawing data verification processing in time series.

  Also in this embodiment, drawing data is created from the layout data LD divided into 15 drawing unit areas 1 to 15 as shown in FIG. Further, in this embodiment, an environment in which the drawing data verification process (S6) can be executed in parallel by a plurality of computers is prepared, and the verification process is executed by an available computer every time divided drawing data is generated. In the case of the specific example shown in FIG. 5, three computers C1 to C3 are provided, the drawing data creation processing (S1) is executed by one computer C1, and the drawing data verification processing (S6) is performed by two computers. This is appropriately executed by the computers C1 and C2. In the specific example shown in FIG. 5, the drawing data corresponding to the drawing unit areas 7 to 9 and 13 to 15 are executed in parallel by the second computer C2.

  In the first embodiment described above with reference to FIGS. 2 and 3, the processing time of the entire verification process is determined by the drawing data creation time + α, and α is determined by the processing time of the maximum processing unit area. On the other hand, according to the third embodiment, α is determined by the last processing unit area by executing the verification process (S6) in parallel. In other words, the overall processing time is shortened by reducing the scale of the last processing unit area.

  As a result, even when the amount of data in the processing unit area is uneven, the drawing data verification process can be executed without causing a “waiting time”, and the overall processing time can be further reduced.

  FIG. 6 is a schematic diagram showing a fourth embodiment of the present invention. That is, this figure is a schematic diagram showing the flow of drawing data creation processing and drawing data verification processing in time series.

  Also in this embodiment, drawing data is created from the layout data LD divided into 15 drawing unit areas 1 to 15 as shown in FIG. Further, in this embodiment, both the drawing data verification process (S6) and the drawing data creation process (S1) are executed in parallel for each processing unit area.

  That is, in the specific example shown in FIG. 6, four computers C1 to C4 are provided, and the drawing data creation process (S1) is executed by the two computers C1 and C2, and the drawing data verification process (S6). Is also appropriately executed by the two computers C3 and C4. In the case of the specific example shown in FIG. 6, the drawing data corresponding to the drawing unit areas 1 to 3, 7 to 9, and 13 to 15 is created by the first computer C1, and the drawing unit areas 4 to 6 and 10 to 12 are generated. The drawing data corresponding to is generated by the second computer C2. The drawing data corresponding to the drawing unit areas 1 to 3, 7 to 9, and 13 to 15 is verified by the third computer C3, and the drawing data corresponding to the drawing unit areas 4 to 6 and 10 to 12 is four. It is verified by the eye computer C4.

  In the first embodiment described above with reference to FIGS. 2 and 3, the processing time of the entire verification process is determined by the drawing data creation time + α, and α is determined by the processing time of the maximum processing unit area. On the other hand, in the fourth embodiment, α is determined by the last processing unit area, and the drawing data creation time can be shortened according to the number of parallel executions. Therefore, the entire processing time can be greatly shortened.

  Further, in this embodiment, it is not necessary to associate the two computers C1 and C2 that execute the data creation process with the two computers C3 and C4 that execute the data verification process. That is, the divided drawing data sequentially output using the two computers C1 and C2 can be appropriately distributed to one of the two computers C3 and C4. Typically, drawing data may be input to a computer that is waiting for data to be processed among the two computers C3 and C4 that execute data verification. Further, when both the two computers C3 and C4 are processing data, drawing data may be input to the computer that has completed the data processing first.

Next, as a fifth embodiment of the present invention, a specific example in which a verification processing method is selected according to the amount of layout data will be described.
FIG. 7 is a schematic diagram illustrating a processing flow in the present embodiment.
That is, first, layout data LD is input, and the total data amount T is calculated (step S20). Examples of the parameter representing the data amount T include the number of figures, the number of sides, the number of vertices, and the like. Of these various parameters, the data amount T is evaluated using a parameter having a high correlation with the processing time in consideration of the algorithm of the drawing data creation program.

Then, comparing the amount of data T and the reference data amount _{T S} (step S22). Here, the reference data amount T _S can be set according to the required processing time. If the amount of data T is smaller than the reference amount of data T _S (step S22: no) is not carried out the division of the layout data LD, the process of creating the drawing data as described above with reference to FIG. 8 through FIG. 10 and the verification process It executes serially (step S24). That is, if the processing time is within the required range even if the drawing data creation process and the verification process are performed in series, the parallel processing described above with reference to FIGS. 1 to 6 needs to be performed. Absent.

On the other hand, if the amount of data T is larger than the reference amount of data T _S (step S22: yes), the calculation of the amount of data contained in each of the imaging unit area (step S26) and, as the area of a unit region becomes uniform A processing unit area is set (step S28). Then, the data amount for each processing unit area is calculated, and the average data amount A and the maximum data amount M are obtained (step S30). Then, to calculate the difference between the average data amount A and the maximum amount of data M, is compared with the reference value T _P of variation (step S32).

If the difference between M and A is equal to or less than the reference value T _P of variation (step S32: no) performs the process of the first embodiment described above with reference to FIG. 3 (step S34). That is, the drawing data creation processing and the drawing data verification processing are executed in parallel by dividing the processing unit region so that the respective areas are uniform.

On the other hand, when the difference between M and A is larger than the reference value T _P of variation (step S32: yes) executes the processing of the second embodiment described above with respect to FIG. That is, in order to shorten the overall processing time of the drawing data creation process and the drawing data verification process, the processing unit area is reset so that the data amount becomes uniform (step S36). Then, the drawing data creation process and the drawing data verification process are executed in parallel.
The drawing data creation process and the drawing data verification process are executed in parallel (step S38).

Reference value T _P of variation can be appropriately determined from the viewpoint of whether better to the uniform amount of data is shortened overall processing time. That is, if the resetting process in step S36 is performed, the processing time increases accordingly. However, as described above with respect to the second embodiment, the entire processing time is shortened by making the data amount uniform. Is obtained. When the variation in the data amount of the processing unit area is small, the processing time is shorter when the processing is executed as in the first embodiment without executing the equalization processing (step S36). On the other hand, when the variation in the data amount of the processing unit area is large, the entire processing time is shortened by resetting the data amount to be uniform (step S36) as in the second embodiment. Therefore, in consideration of the effect of these processing times increase and decrease, it may be determined reference value T _P variations.

  The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  For example, the present invention is not limited only to the manufacture of a mask, but can also be applied to verification of electron beam drawing data for performing electron beam drawing on a target object in which a resist is formed on a wafer of a semiconductor integrated circuit. .

  In addition, all electron beam drawing data creation verification methods and creation verification apparatuses that include elements of the present invention and that can be appropriately modified by those skilled in the art are included in the scope of the present invention.

It is a schematic diagram which illustrates the flow of the production verification method of the electron beam drawing data concerning embodiment of this invention. It is a schematic diagram showing the 1st example of the present invention. It is the schematic diagram which represented the flow of the process in a 1st Example in time series. It is a schematic diagram showing the 2nd Example of this invention. It is a schematic diagram showing the 3rd Example of this invention. It is a schematic diagram showing the 4th Example of this invention. It is a schematic diagram showing the flow of the process in the 5th Example of this invention. It is a schematic diagram which illustrates the flow of creation and verification of drawing data. It is a schematic diagram showing the processing order of drawing data creation processing S1 and drawing data verification processing. It is a schematic diagram showing time concerning drawing data creation processing S1 and drawing data verification processing S6, respectively.

Explanation of symbols

1 to 15 Drawing unit areas C1 to C4 Computer DD Drawing data LD Layout data S1 Drawing data creation processing S6 Drawing data verification processing

Claims (12)

An electron beam drawing data creation verification method for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
An electron beam created for only a part of the layout data after the creation process of the electron beam drawing data for only a part of the layout data and before the creation of the electron beam drawing data for the remaining part of the layout data is completed. A method for creating and verifying electron beam drawing data, comprising performing a drawing data verification process. An electron beam drawing data creation verification method for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
If the data amount of the layout data is equal to or greater than a predetermined value, the generation process of the electron beam drawing data is executed for only a part of the layout data, and then the electron beam drawing data for the remaining part of the layout data is Before the creation process is completed, the verification process of the electron beam drawing data created for only the part is executed,
When the data amount of the layout data is smaller than a predetermined value, the electron beam drawing data verification process is executed after the electron beam drawing data creation process is executed for the entire layout data. A method for creating and verifying electron beam drawing data. An electron beam drawing data creation verification method for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
Dividing layout data into a plurality of processing unit areas;
Performing a process of creating electron beam drawing data for a first processing unit region of the plurality of processing unit regions;
Executing verification processing of the electron beam drawing data created for the first processing unit region while executing generation processing of the electron beam drawing data for the second processing unit region of the plurality of processing unit regions; ,
A method for creating and verifying electron beam drawing data, comprising: An electron beam drawing data creation verification method for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
Calculating the amount of layout data;
A first creation verification step that is performed when the data amount of the layout data is equal to or greater than a predetermined value;
A second creation verification step that is performed when the data amount of the layout data is smaller than a predetermined value;
With
The first creation verification step includes
Dividing layout data into a plurality of processing unit areas;
Performing a process of creating electron beam drawing data for a first processing unit region of the plurality of processing unit regions;
Executing verification processing of the electron beam drawing data created for the first processing unit region while executing generation processing of the electron beam drawing data for the second processing unit region of the plurality of processing unit regions; ,
Including
The second creation verification step includes
A step of executing creation processing of electron beam drawing data for the entire layout data;
Performing verification processing of the electron beam drawing data created for the entire layout data;
A method for creating and verifying electron beam drawing data, comprising:   5. The electron beam drawing data according to claim 3, wherein, in the step of dividing the plurality of processing unit regions, the division is performed so that the data amount of each of the plurality of processing unit regions is substantially uniform. Creation verification method.   6. The method for verifying the creation and verification of electron beam drawing data according to claim 3, wherein each of the plurality of processing unit areas includes one or a plurality of drawing unit areas.   The number of the drawing unit areas included in any of the plurality of processing unit areas is different from the number of the drawing unit areas included in any of the other processing unit areas. A method of creating and verifying the described electron beam drawing data.   8. The method of creating and verifying electron beam drawing data according to claim 1, wherein at least one of the creation process and the validation process can be performed in parallel by a plurality of processing means. An electron beam drawing data creation verification apparatus for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
An electron beam created for only a part of the layout data after the creation process of the electron beam drawing data for only a part of the layout data and before the creation of the electron beam drawing data for the remaining part of the layout data is completed. An apparatus for verifying the creation of electron beam drawing data, characterized in that the drawing data verification process is executed. An electron beam drawing data creation verification apparatus for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
If the data amount of the layout data is equal to or greater than a predetermined value, the generation process of the electron beam drawing data is executed for only a part of the layout data, and then the electron beam drawing data for the remaining part of the layout data is Before the creation process is completed, the verification process of the electron beam drawing data created for only the part is executed,
When the data amount of the layout data is smaller than a predetermined value, the electron beam drawing data creation process is executed for the entire layout data, and then the electron beam drawing data verification process is executed. An apparatus for creating and verifying electron beam drawing data. An electron beam drawing data creation verification apparatus for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
Divide layout data into multiple processing unit areas,
Executing a process for creating electron beam drawing data for a first processing unit region of the plurality of processing unit regions;
The verification process of the electron beam drawing data created for the first processing unit area is executed while the electron beam drawing data creation process is executed for the second processing unit area of the plurality of processing unit areas. An apparatus for creating and verifying electron beam drawing data, characterized by being configured. An electron beam drawing data creation verification apparatus for creating and verifying electron beam drawing data for drawing with an electron beam on an object to be exposed,
Calculate the amount of layout data,
When the data amount of the layout data is greater than or equal to a predetermined value, a first creation verification process is performed,
When the data amount of the layout data is smaller than a predetermined value, a second creation verification process is performed,
The first creation verification process includes:
Dividing layout data into a plurality of processing unit areas;
Performing a process of creating electron beam drawing data for a first processing unit region of the plurality of processing unit regions;
Executing verification processing of the electron beam drawing data created for the first processing unit region while executing generation processing of the electron beam drawing data for the second processing unit region of the plurality of processing unit regions; ,
Including
The second creation verification step includes
A step of executing creation processing of electron beam drawing data for the entire layout data;
Performing verification processing of the electron beam drawing data created for the entire layout data;
An apparatus for verifying the creation of electron beam drawing data, characterized by comprising:

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