CN107783369B - Optical proximity correction repairing method - Google Patents

Abstract

A method for optical proximity correction repair. At least one hot spot marking area is obtained according to a first layout of a semiconductor wafer. According to the hot spot marking area, a to-be-repaired area and a non-hot spot area are obtained in the first layout, wherein the to-be-repaired area comprises the hot spot marking area. And dividing the area to be repaired into a plurality of templates. And executing a repairing program for each template. Providing a second layout according to each of the repaired templates and the non-hot spot region.

Description

Optical proximity correction repairing method

Technical Field

The present disclosure relates to a repairing method, and more particularly, to a repairing method for optical proximity correction of a semiconductor photomask.

Background

Nowadays, the semiconductor Integrated Circuit (IC) industry is a rapidly growing industry. In the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per unit area of a wafer) has generally increased as the feature size (i.e., the smallest device or line width that can be fabricated using a fabrication process) has decreased. The process of miniaturization of integrated circuits can improve production efficiency and reduce related cost, thereby providing benefits. However, the process of scaling down the integrated circuit also increases the complexity of the integrated circuit in manufacturing. Accordingly, the same developments in the processing and fabrication of integrated circuits are needed.

For example, photolithography processes often use Optical Proximity Correction (OPC) to improve and enhance the image quality on photomasks used to manufacture integrated circuits. However, as feature sizes continue to shrink, such techniques become increasingly difficult and complex to implement.

Therefore, a method for repairing optical proximity correction is needed to ensure the quality of the image on the photomask.

Disclosure of Invention

The present disclosure provides a method for optical proximity correction repair. At least one hot spot marking area is obtained according to a first layout of a semiconductor wafer. According to the hot spot marking area, a to-be-repaired area and a non-hot spot area are obtained in the first layout, wherein the to-be-repaired area comprises the hot spot marking area. And dividing the area to be repaired into a plurality of templates. And executing a repairing program for each template. Providing a second layout according to each of the repaired templates and the non-hot spot region.

Furthermore, the present disclosure provides another optical proximity correction restoration method. At least one hot spot marking area is obtained according to a first layout of a semiconductor wafer. According to the hot spot marking area, a to-be-repaired area and a non-hot spot area are obtained in the first layout, wherein the to-be-repaired area comprises the hot spot marking area. And dividing the area to be repaired into a plurality of templates. And executing a repairing program for each template. Providing a second layout according to each of the repaired templates and the non-hot spot region. The area of the region to be repaired is larger than that of the hot spot marking region, and the optimized area of each template is calculated according to the repairing program.

Drawings

FIG. 1 illustrates a method of fabricating a photomask according to some embodiments of the present disclosure, wherein the method of fabricating a photomask of FIG. 1 is performed by a processor capable of executing an Electronic Design Automation (EDA) tool;

FIG. 2 shows a flow diagram of a repair procedure for optical proximity correction according to some embodiments of the present disclosure;

FIG. 3A shows an exemplary first layout after performing step S210 of FIG. 2 according to some embodiments of the present disclosure;

FIG. 3B shows an exemplary first layout after performing step S220 of FIG. 2 according to some embodiments of the present disclosure;

FIG. 3C shows an example of a second layout after performing step S240 of FIG. 2 according to some embodiments of the present disclosure;

FIG. 4 shows a schematic diagram of the division of the entire first layout into a plurality of templates; and

FIG. 5 illustrates a computer system according to some embodiments of the present disclosure.

Description of reference numerals:

310. 400-a first layout;

320A, 320B to a hot spot marking area;

330A, 330B to the area to be repaired;

340-no hot spot area;

350_1-350_9, 360_1-350_12 to the template;

380-second layout;

500-computer system;

510, a computer;

520 to a display device;

530-user input device;

540 to a processor;

550-a memory; and

S110-S150, S210-S240.

Detailed Description

In order to make the aforementioned and other objects, features, and advantages of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below:

the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. The following disclosure describes specific examples of components and arrangements thereof to simplify the description. In addition, different examples of the following disclosure may repeat use of the same reference symbols and/or designations. These iterations are not intended to limit the specific relationship between the various embodiments and/or configurations discussed herein for purposes of simplicity and clarity.

Various variations of the embodiments are described below. Like element numerals are used to identify like elements throughout the various views and depicted embodiments. It should be understood that additional operational steps may be performed before, during, or after the method, and that in other embodiments of the method, portions of the operational steps may be replaced or omitted.

In Integrated Circuit (IC) design, many functions are integrated in one chip, and an Application Specific Integrated Circuit (ASIC) or system on a chip (SOC) based design is often used. After setting the functional design of the component by selecting and connecting a number of standard functions, Electronic Design Automation (EDA) tools may be used to verify the correct operation of the resulting circuit. The design flow is continued by performing placement and routing (using standard cells) to form the local and global connections required for the complete design.

After design rule checking, design rule verification, timing analysis, critical path analysis, static and dynamic power analysis, and final modification to the design, a tape out procedure is performed to generate photomask generation data. The photomask is then used to generate data for creating a photomask, and the photomask is used to fabricate semiconductor devices in a photolithographic (photolithographic) process in a FAB (FAB). In the offline process, the Database file of the integrated circuit is converted into a Graphic Database System (GDS) file (e.g., a GDS file or a GDSII file or an OASIS file). Then, for integrated circuit fabrication, the graphical database system file may be used to fabricate different layers of photomasks. In particular, graphic database system files are becoming an industry standard format for transferring integrated circuit layout data between design tools of different vendors.

Fig. 1 illustrates a method of fabricating a photomask according to some embodiments of the present disclosure, wherein the method of fabricating a photomask of fig. 1 is performed by a processor capable of executing an Electronic Design Automation (EDA) tool. First, in step S110, integrated circuit design layout data (or an integrated circuit design layout) is obtained. In some embodiments, the integrated circuit design layout data may be provided by a separate design company or by a semiconductor manufacturing facility. In some embodiments, the semiconductor fab is also capable of fabricating photomasks, semiconductor wafers, or both.

The integrated circuit design layout data may be a data file having geometric information. Generally, an integrated circuit design layout may be a Graphic Database System (GDS) file (e.g., a GDS file or a GDSII file or an OASIS file). In addition, designers can execute appropriate design procedures to generate integrated circuit design layouts, depending on the specifications of the integrated circuits to be manufactured. Design processes may also include logical design, physical design, and/or placement and routing, among others. For example, a portion of an integrated circuit design layout includes various features (also referred to as main features) formed in and on a semiconductor substrate (e.g., a silicon wafer) and various layers of material disposed on the semiconductor substrate. In some embodiments, the features of the integrated circuit include active regions, gates, drains and sources, metal lines, vias (via) for interlayer interconnects (i.e., interlevel interconnects), and bond pads (pads). In addition, the integrated circuit design layout may also include certain assist features, such as information for image effect (imaging effect), process enhancement (processing), and/or mask identification (mask identification).

It is noted that the integrated circuit design layout data obtained in step S110 may be the entire layout data or a part of the layout data of the integrated circuit, such as a part of the layout data of a specific circuit in the integrated circuit.

In step S120 of fig. 1, based on the obtained layout data of the integrated circuit design, the processor executes an Optical Proximity Correction (OPC) procedure to obtain a first layout. Next, in step S130, the processor performs hot-spot analysis on the first layout according to the plurality of process parameters to obtain a hot-spot marker (hot-spot marker) region in the first layout.

After obtaining the hot spot indication areas in the first layout, the processor performs a repair (replay) procedure of optical proximity correction on the hot spot indication areas in the first layout (step S140) to obtain a second layout. After the repair procedure, no hot spots will appear in the second layout. Then, in step S150, a photomask process (or a photomask manufacturing) may be performed using the information of the second layout (i.e., the photomask generation data) to generate a photomask. For example, the layout pattern in the second layout may be formed on the photomask through a photomask exposure machine. In some embodiments, the photomask exposure machine may be an electron beam (electron beam) writer, an ion beam (ion beam) writer, or a laser beam (laser beam) writer.

Fig. 2 shows a flowchart of a repair procedure (e.g., step S140 of fig. 1) for optical proximity correction according to some embodiments of the present disclosure. First, in step S210, according to each obtained hot spot marking area, the processor may obtain a corresponding area to be repaired in a first layout. Specifically, each area to be repaired covers the corresponding hot spot marking area. In addition, the processor may also obtain a non-hotspot region in the first layout. In the no-hot spot region, no hot spots need to be repaired. Thus, the area of the first layout is the sum of the areas of all the regions to be repaired and the non-hot spot region.

In step S220, the processor divides each to-be-repaired area into a plurality of templates (templates). In each area to be repaired, the size of each template is the optimized area obtained according to the repairing procedure. In some embodiments, the size of the template is determined according to the area of the region to be repaired and/or the number of hot spots to be repaired. In some embodiments, the templates in the area to be repaired may be divided into a first template and a second template, and the first template is disposed around the area to be repaired, and the second template is disposed inside the area to be repaired. Thus, the hot spot designation area in the first template is smaller than the hot spot designation area in the second template.

In step S230, the processor executes a repairing procedure on the hot spot marking area in each template, so that no hot spot exists in the repaired template. It is noted that the processor does not perform the repair procedure on the non-hotspot area. In addition, the processor does not divide the non-hot spot region into a plurality of templates. Next, in step S240, the processor provides a second layout according to the repaired template and the non-hot spot region. As previously described, after obtaining a second layout without hot spots present, the second layout may be used to generate a photomask.

Fig. 3A shows an example of the first layout 310 after performing step S210 of fig. 2 according to some embodiments of the present disclosure. In fig. 3A, after the hot spot analysis, the processor may obtain two hot spot indication areas 320A and 320B in the first layout 310. In this embodiment, the area of the hot spot marking region 320B is larger than the area of the hot spot marking region 320A. Next, according to the hot spot indication areas 320A and 320B, the processor may obtain the area to be repaired 330A corresponding to the hot spot indication area 320A and the area to be repaired 330B corresponding to the hot spot indication area 320B in the first layout 310. As shown in fig. 3A, the area of the region to be repaired 330A is larger than the hot spot marking region 320A to cover the hot spot marking region 320A. Similarly, the area of the region to be repaired 330B is larger than the hot spot marking region 320B to cover the hot spot marking region 320B. In some embodiments, the center point of the to-be-repaired area 330A is the same as the center point of the hot spot marking area 320A, and the center point of the to-be-repaired area 330B is the same as the center point of the hot spot marking area 320B. In addition, in the first layout 310, the processor may further obtain the hot spot free region 340. Notably, in the non-hotspot region 340, no hotspot needs to be repaired. As described above, the area of the first layout 310 is the sum of the areas of the regions to be repaired 330A and 330B and the non-hot spot region 340.

Fig. 3B shows an example of the first layout 310 after performing step S220 of fig. 2 according to some embodiments of the present disclosure. In FIG. 3B, the processor divides the area to be repaired 330A into 9 templates 350_1-350_ 9. In this embodiment, the size (area) of each template 350_1-350_9 is the same. In some embodiments, the size (area) of each of the templates 350_1-350_9 is obtained by performing an optimized area analysis according to the repair procedure. Similarly, the processor divides the area to be repaired 330B into 12 templates 360_1-360_ 12. In this embodiment, the size of each template 360_1-360_12 is the same. In some embodiments, the size (area) of each template 360_1-360_12 is obtained by performing an optimized area analysis according to the repair procedure. In this embodiment, templates 350_1-350_9 and templates 360_1-360_12 have the same size. In some embodiments, the size of templates 350_1-350_9 is different from the size of templates 360_1-360_ 12. It is noted that optimizing the area minimizes the number of templates, thereby improving the efficiency of parallel operation of the processor.

In the area to be repaired 330A of fig. 3B, the templates 350_1-350_8 are first templates disposed around the area to be repaired 330A, and the template 350_9 is a second template disposed inside the area to be repaired 330A. In addition, template 350_9 is surrounded by templates 350_1-350_8, i.e., the second template would be surrounded by the first template. In the area to be repaired 330B of fig. 3B, the templates 360_1-360_10 are first templates disposed around the area to be repaired 330B, and the templates 360_11-360_12 are second templates disposed inside the area to be repaired 330B. In addition, the templates 360_11-360_12 are surrounded by the templates 360_1-360_10, i.e., the second template would be surrounded by the first template.

In FIG. 3B, the first template (e.g., templates 350_1-350_8 and 360_1-360_10) includes a smaller hot spot designation area than the second template (e.g., templates 350_9 and 360_11-360_ 12). In other words, in the first template, the hot spot marking region occupies part of the area, and the other remaining areas have no hot spot. In addition, in the second template, the hot spot indication area occupies the entire area. In some embodiments, compared to the second template, the execution time of the processor executing the repair program on the first template is less than the execution time of executing the repair program on the second template because the hot spot indication area in the first template is less. It should be noted that the processor only executes the repair procedure on the templates in the regions to be repaired 330A and 330B, but not on the hot spot-free region 340.

Fig. 3C shows an exemplary example of the second layout 380 after performing step S240 of fig. 2 according to some embodiments of the present disclosure. In this embodiment, templates 350_1-350_9 and templates 360_1-360_12 have been repaired. The processor then provides a second layout 380 based on the repaired template and the non-hotspot region 340. As previously described, in second layout 380, no hot spots exist.

In contrast to a repair procedure that divides the entire first layout into a plurality of templates and repairs the entire first layout (e.g., divide the first layout 400 of fig. 4 into a plurality of templates), according to an embodiment of the disclosure, the processor only needs to divide the area to be repaired (e.g., the areas to be repaired 330A and 330B of fig. 3) into a plurality of templates and execute the repair procedure on the templates of the area to be repaired. Thus, the number of templates required to execute the repair procedure may be reduced. Therefore, the time and the amount of calculation for executing the repair program can be reduced, thereby reducing the cost. For example, memory resources needed to be used when executing the repair program may be reduced. In addition, according to the embodiments of the present disclosure, the processor may dynamically adjust the size of the corresponding template according to each hot spot indication area.

FIG. 5 illustrates a computer system 500 according to some embodiments of the present disclosure. The computer system 500 includes a computer 510, a display device 520, and a user input device 530. The computer 510 includes a processor 540 and a memory 550. The computer 510 is coupled to a display device 520 and a user input device 530. The processor 540 of the computer 510 may execute an Electronic Design Automation (EDA) tool. Furthermore, the computer 510 can receive the first layout from the remote device via the user input device 530 or in a wired or wireless manner, and display the first layout on the display device 520. In addition, after the optical proximity correction repair process is completed, the computer 510 may display the second layout on the display device 520. In some embodiments, the display device 520 and the user input device 530 may be disposed in the computer 510. In the computer 510, the memory 550 may store an operating system, applications, and related data. In addition, the processor 540 of the computer 510 may perform one or more operations (automatically or in accordance with user input) of the methods described in embodiments of the disclosure.

Although the present disclosure has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure, and therefore the scope of the disclosure should be determined by that defined in the appended claims.

Claims (8)

1. A method of optical proximity correction restoration, comprising:

obtaining at least one hot spot marking area according to a first layout of a semiconductor wafer;

obtaining a region to be repaired and a region without hot spots in the first layout according to the hot spot marking region, wherein the region to be repaired comprises the hot spot marking region;

dividing the area to be repaired into a plurality of templates;

executing a repairing program for each template; and

providing a second layout according to each of the repaired templates and the non-hot spot region,

the plurality of templates include a plurality of first templates and at least one second template, wherein the hot spot indication area included in each of the first templates is smaller than the hot spot indication area included in the second template, and the second template is surrounded by the plurality of first templates.

2. The repair method of claim 1, further comprising:

providing a photomask for the semiconductor wafer according to the second layout.

3. The method of repairing of claim 1, wherein the step of obtaining the hot spot marking area according to the first layout of the semiconductor wafer further comprises:

receiving an integrated circuit design layout data of the semiconductor wafer;

executing an optical proximity correction procedure on the integrated circuit design layout data to obtain the first layout; and

the first layout is analyzed according to a plurality of process parameters to obtain the hot spot marking area.

4. The repairing method of claim 1, wherein the area of the region to be repaired is larger than the area of the hot spot marking region.

5. The repair method of claim 1, wherein the area of each of the templates is determined by the repair process according to the area of the region to be repaired.

6. A method of optical proximity correction restoration, comprising:

obtaining at least one hot spot marking area according to a first layout of a semiconductor wafer;

obtaining a region to be repaired and a region without hot spots in the first layout according to the hot spot marking region, wherein the region to be repaired comprises the hot spot marking region;

dividing the area to be repaired into a plurality of templates;

executing a repairing program for each template; and

providing a second layout according to each of the repaired templates and the non-hot spot region,

wherein the area of the region to be repaired is larger than the area of the hot spot marking region,

wherein the area of each template is determined by the repair program according to the area of the region to be repaired or the number of hot spots in the hot spot marking region,

the plurality of templates include a plurality of first templates and at least one second template, wherein the hot spot indication area included in each of the first templates is smaller than the hot spot indication area included in the second template, and the second template is surrounded by the plurality of first templates.

7. The repair method of claim 6, further comprising:

providing a photomask for the semiconductor wafer according to the second layout.

8. The method of repairing of claim 6, wherein the step of obtaining the hot spot marking area according to the first layout of the semiconductor wafer further comprises:

receiving an integrated circuit design layout data of the semiconductor wafer;

executing an optical proximity correction procedure on the integrated circuit design layout data to obtain the first layout; and

the first layout is analyzed according to a plurality of process parameters to obtain the hot spot marking area.

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