CN107783369B - Optical proximity correction repairing method - Google Patents

Abstract

A repair method for optical proximity correction. According to a first layout of a semiconductor wafer, at least one hot spot marking area is obtained. According to the hot spot marking area, a region to be repaired and a non-hot spot area are obtained in the first layout, wherein the region to be repaired includes the hot spot marking area. The region to be repaired is divided into a plurality of templates. A repair procedure is performed on each of the templates. According to each of the repaired templates and the non-hot spot area, a second layout is provided.

Description

The Repair Method of Optical Proximity Correction

technical field

The present disclosure relates to a repair method, and more particularly, to a repair method for optical proximity correction of a semiconductor photomask.

Background technique

Today, the semiconductor integrated circuit (IC) industry is a rapidly growing industry. During the evolution of integrated circuits, functional density (ie, the number of interconnected components per unit wafer area) has become prevalent as feature size (ie, the smallest component or line width that can be fabricated using a fabrication process) has decreased increase. The process of miniaturization of integrated circuits can improve production efficiency and reduce related costs, thereby providing benefits. However, the process of miniaturization of integrated circuits also increases the complexity of the fabrication of integrated circuits. Therefore, the same development is required in the processing and manufacture of integrated circuits.

For example, lithography processes often use optical proximity correction (OPC) to improve and enhance image quality on photomasks used to fabricate integrated circuits. However, as feature sizes continue to shrink, such techniques become increasingly difficult and complex to implement.

Therefore, there is a need for an optical proximity correction repair method to ensure the image quality on the photomask.

SUMMARY OF THE INVENTION

The present disclosure provides a repair method for optical proximity correction. According to a first layout of a semiconductor wafer, at least one hot spot marked area is obtained. According to the hot spot marking area, a to-be-repaired area and a non-hot-spot area are obtained in the first layout, wherein the to-be-repaired area includes the hot spot marked area. The area to be repaired is divided into multiple templates. A repair procedure is performed on each of the templates. A second layout is provided based on each of the repaired templates and the hotspot-free area.

Furthermore, the present disclosure provides another repair method for optical proximity correction. According to a first layout of a semiconductor wafer, at least one hot spot marked area is obtained. According to the hot spot marking area, a to-be-repaired area and a non-hot-spot area are obtained in the first layout, wherein the to-be-repaired area includes the hot spot marked area. The area to be repaired is divided into multiple templates. A repair procedure is performed on each of the templates. A second layout is provided based on each of the repaired templates and the hotspot-free area. The area of the area to be repaired is larger than the area of the hot spot marked area, and the optimized area of each template is calculated according to the repair procedure.

Description of drawings

FIG. 1 shows a photomask fabrication method according to some embodiments of the present disclosure, wherein the photomask fabrication method of FIG. 1 is executed by a processor executing an Electronic Design Automation (EDA) tool;

FIG. 2 shows a flowchart of a repair procedure for optical approximation correction according to some embodiments of the present disclosure;

FIG. 3A shows an exemplary example of the first layout after performing step S210 of FIG. 2 according to some embodiments of the present disclosure;

FIG. 3B shows an exemplary example of the first layout after performing step S220 of FIG. 2 according to some embodiments of the present disclosure;

FIG. 3C shows an exemplary example of the second layout after performing step S240 of FIG. 2 according to some embodiments of the present disclosure;

Figure 4 shows a schematic diagram of dividing the entire first layout into a plurality of templates; and

FIG. 5 shows a computer system according to some embodiments of the present disclosure.

Description of reference numbers:

310, 400 ~ the first layout;

320A, 320B ~ hot spot marked area;

330A, 330B ~ areas to be repaired;

340 to no hotspot area;

350_1-350_9, 360_1-350_12～template;

380～Second layout;

500～computer system;

510～computer;

520～display device;

530 ~ user input device;

540～processor;

550 to memory; and

Steps S110-S150, S210-S240.

Detailed ways

In order to make the above-mentioned and other objects, features, and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are given below, and are described in detail as follows in conjunction with the accompanying drawings:

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. In addition, different examples of the following disclosure may reuse the same reference symbols and/or signs. These repetitions are for the purpose of simplicity and clarity and are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

Various variations of the embodiments are described below. Similar element numbers are used to designate similar elements throughout the various views and depicted embodiments. It should be understood that additional operational steps may be performed before, during, or after the method, and in other embodiments of the method, some operational steps may be substituted or omitted.

In integrated circuit (IC) design, many functions are integrated into one chip, and application specific integrated circuit (ASIC) or system on a chip (SOC)-based designs are often used . After the functional design of the components has been set by selecting and connecting a number of standard functions, electronic design automation (EDA) tools can be used to verify the correct operation of the resulting circuit. The design flow continues by performing the placement and routing of local and global connections required to form a complete design using standard cells.

After design rule checking, design rule verification, timing analysis, critical path analysis, static and dynamic power analysis, and final modifications to the design, a tape out procedure is performed to generate photomask production data. The photomask is then used to generate data to generate a photomask, and the photomask is used to fabricate semiconductor elements in a photolithographic process in a wafer fabrication facility (FAB). During the offline procedure, the database files of the integrated circuits are converted into Graphic Database System (GDS) files (eg, GDS files or GDSII files or OASIS files). Then, for integrated circuit fabrication, the graphic database system files can be used to make different layers of photomasks. In particular, graphics database system files have become an industry standard format for transferring integrated circuit layout data between design tools from different vendors.

FIG. 1 shows a photomask fabrication method according to some embodiments of the present disclosure, wherein the photomask fabrication method of FIG. 1 is executed by a processor executing an Electronic Design Automation (EDA) tool. First, in step S110, integrated circuit design layout data (or integrated circuit design layout diagram) is obtained. In some embodiments, the integrated circuit design layout data may be provided by an independent design company or by a semiconductor fabrication facility. Additionally, in some embodiments, the semiconductor fabrication facility is also capable of fabricating photomasks, semiconductor wafers, or both.

The integrated circuit design layout data may be a data file with geometry information. In general, the integrated circuit design layout may be a Graphic Database System (GDS) file (eg, a GDS file or a GDSII file or an OASIS file). In addition, the designer can perform an appropriate design procedure to generate an integrated circuit design layout according to the specifications of the integrated circuit to be fabricated. The design process may also include logical design, physical design and/or configuration and routing. For example, a portion of an integrated circuit design layout includes various features (also referred to as main features) formed in and on a semiconductor substrate (eg, a silicon wafer) and various features disposed on the semiconductor substrate. material layer. In some embodiments, the features of the integrated circuit include active regions, gates, drains and sources, metal lines, vias for interlayer interconnections, pads, and the like. In addition, the integrated circuit design layout may also include certain auxiliary features, such as information for imaging effects, process enhancements, and/or mask identification.

It should be noted that the integrated circuit design layout data obtained in step S110 may be the entire layout data or part of the layout data of the integrated circuit, for example, part of the layout data of a specific circuit in the integrated circuit.

In step S120 of FIG. 1 , according to the obtained integrated circuit design layout data, the processor executes an optical approximation correction (Optical Proximity Correction, OPC) procedure to obtain a first layout. Next, in step S130, the processor performs a hot-spot analysis on the first layout according to a plurality of process parameters, so as to obtain a hot-spot marker area in the first layout.

After obtaining the hot spot marked area in the first layout, the processor performs a repair procedure of optical approximation correction on the hot spot marked area in the first layout (step S140 ) to obtain the second layout. After the fix, no hot spots appear in the second layout. Next, in step S150, photomask processing (either photomask fabrication or photomask production) may be performed using the information of the second layout (ie, photomask generation data) to generate a photomask. For example, the layout pattern in the second layout can be formed on the photomask through a photomask exposure writer. In some embodiments, the photomask exposure writer may be an electron beam writer, an ion beam writer, or a laser beam writer.

FIG. 2 shows a flowchart of an optical approximation correction repair procedure (eg, step S140 of FIG. 1 ) according to some embodiments of the present disclosure. First, in step S210, according to each obtained hot spot marked area, the processor can obtain the corresponding to-be-repaired area in the first layout. Specifically, each area to be repaired covers the corresponding hot spot marked area. In addition, the processor can also obtain no hotspot areas in the first layout. In a hotspot free area, there are no hotspots to fix. Therefore, the area of the first layout is the sum of the areas of all the areas to be repaired and the areas without hot spots.

In step S220, the processor divides each area to be repaired into a plurality of templates. In each area to be repaired, the size of each template is based on the optimized area obtained by the repair procedure. In some embodiments, the size of the template is determined according to the area of the area to be repaired and/or the number of hot spots to be repaired. In some embodiments, the templates in the area to be repaired can be divided into a first template and a second template, and the first template is arranged around the area to be repaired, and the second template is arranged inside the area to be repaired. Therefore, the hot spot marked area in the first template is smaller than the hot spot marked area in the second template.

In step S230, the processor performs a repair procedure on the hot spot marked area in each template, so that there is no hot spot in the repaired template. It's worth noting that the processor does not perform fixes for hotspot-free areas. In addition, the processor does not divide the hotspot-free area into multiple templates. Next, in step S240, the processor provides a second layout according to the repaired template and the hotspot-free area. As previously described, after obtaining the second layout without the presence of hot spots, the second layout can be used to create a photomask.

FIG. 3A shows an exemplary example of the first layout 310 after step S210 of FIG. 2 is performed according to some embodiments of the present disclosure. In FIG. 3A , after hot spot analysis, the processor can obtain two hot spot marked areas 320A and 320B in the first layout 310 . In this embodiment, the area of the hot spot marking area 320B is larger than that of the hot spot marking area 320A. Then, according to the hot spot marked areas 320A and 320B, the processor can obtain the to-be-repaired area 330A corresponding to the hot-spot marked area 320A and the to-be-repaired area 330B corresponding to the hot spot marked area 320B in the first layout 310 . As shown in FIG. 3A , the area of the to-be-repaired area 330A is larger than the hot spot marked area 320A so as to cover the hot spot marked area 320A. Likewise, the area of the area to be repaired 330B is larger than that of the hot spot marked area 320B so as to cover the hot spot marked area 320B. In some embodiments, the center point of the area to be repaired 330A is the same as the center point of the hot spot marked area 320A, and the center point of the area to be repaired 330B is the same as the center point of the hot spot marked area 320B. In addition, in the first layout 310 , the processor can further obtain the hotspot-free area 340 . Notably, in the hotspot free area 340, there are no hotspots to repair. As previously described, the area of the first layout 310 is the sum of the areas of the areas to be repaired 330A and 330B and the area without the hot spot 340 .

FIG. 3B shows an exemplary example of the first layout 310 after step S220 of FIG. 2 is performed according to some embodiments of the present disclosure. In FIG. 3B, the processor divides the area to be repaired 330A into 9 templates 350_1-350_9. In this embodiment, the size (area) of each template 350_1-350_9 is the same. In some embodiments, the size (area) of each template 350_1 - 350_9 is obtained by performing an optimized area analysis according to a repair procedure. Likewise, the processor divides the area to be repaired 330B into 12 templates 360_1-360_12. In this embodiment, the size of each template 360_1-360_12 is the same. In some embodiments, the size (area) of each template 360_1-360_12 is obtained by performing an optimized area analysis according to a repair procedure. In this embodiment, the templates 350_1-350_9 and the templates 360_1-360_12 have the same size. In some embodiments, the dimensions of the templates 350_1-350_9 are different from the dimensions of the templates 360_1-360_12. It is worth noting that the optimized area is to minimize the number of templates, thereby increasing the efficiency of the parallel operation of the processor.

In the area to be repaired 330A in FIG. 3B , the templates 350_1 - 350_8 are the first templates arranged around the area to be repaired 330A, and the template 350_9 is the second template arranged inside the area to be repaired 330A. In addition, the template 350_9 is surrounded by templates 350_1-350_8, ie the second template will be surrounded by the first template. In the area to be repaired 330B of FIG. 3B , templates 360_1 - 360_10 are first templates arranged around the area to be repaired 330B, and templates 360_11 - 360_12 are second templates arranged inside the area to be repaired 330B. In addition, templates 360_11-360_12 are surrounded by templates 360_1-360_10, ie, the second template will be surrounded by the first template.

In FIG. 3B , the hotspot marked areas included in the first template (eg, templates 350_1-350_8 and templates 360_1-360_10) are smaller than those included in the second template (eg, templates 350_9 and 360_11-360_12). In other words, in the first template, the hot spot marked area occupies part of the area, and there is no hot spot in the other remaining areas. In addition, in the second template, the hot spot marked area occupies the entire area. In some embodiments, compared with the second template, since there are fewer hot spot areas in the first template, the execution time of the processor for executing the repair procedure on the first template is shorter than the execution time for executing the repair procedure on the second template. . It is worth noting that the processor will only perform the repair process on each template in the to-be-repaired areas 330A and 330B, and will not perform the repair process on the non-hot spot area 340 .

FIG. 3C shows an exemplary example of the second layout 380 after step S240 of FIG. 2 is performed according to some embodiments of the present disclosure. In this embodiment, templates 350_1-350_9 and templates 360_1-360_12 have been repaired. Next, the processor provides a second layout 380 according to the repaired template and the hotspot-free area 340 . As previously described, in the second layout 380, no hot spots exist.

Compared to a repair procedure that divides the entire first layout into multiple templates and repairs them all (eg, divides the first layout 400 of FIG. 4 into multiple templates), according to embodiments of the present disclosure, the processor only It is necessary to divide the to-be-repaired area (eg, the to-be-repaired areas 330A and 330B in FIG. 3 ) into a plurality of templates and perform a repair procedure on the templates of the to-be-repaired area. As a result, the number of templates required to perform the repair procedure is reduced. Therefore, the time for executing the repair program and the amount of computation can be reduced, thereby reducing the cost. For example, the memory resources required to execute the repair program can be reduced. In addition, according to an embodiment of the present disclosure, the processor can dynamically adjust the size of the corresponding template according to each hot spot marked area.

FIG. 5 shows a computer system 500 according to some embodiments of the present disclosure. The computer system 500 includes a computer 510 , a display device 520 and a user input device 530 . Computer 510 includes processor 540 and memory 550 . The computer 510 is coupled to the display device 520 and the user input device 530 . The processor 540 of the computer 510 can execute electronic design automation (EDA) tools. Furthermore, the computer 510 may receive the first layout from the remote device via the user input device 530 or in a wired or wireless manner, and display the first layout on the display device 520 . In addition, the computer 510 may display the second layout on the display device 520 after completing the repair procedure of the optical approximation correction. In some embodiments, the display device 520 and the user input device 530 may be provided in the computer 510 . In the computer 510, the memory 550 can store the operating system, applications and related data. In addition, the processor 540 of the computer 510 may perform one or more operations of the methods described in the embodiments of the present disclosure (either automatically or according to user input).

Although the present disclosure has been disclosed above with preferred embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, The scope of protection of the present disclosure should be defined by the appended claims.

Claims (8)

1. a repair method of optical proximity correction, is characterized in that, comprises: obtaining at least one hot spot marked area according to a first layout of a semiconductor wafer; obtaining a to-be-repaired area and a non-hot-spot area in the first layout according to the hot-spot marked area, wherein the to-be-repaired area includes the hot spot marked area; Divide the area to be repaired into multiple templates; performing a repair procedure on each of the templates; and providing a second layout according to each said template that has been repaired and the hotspot free area, The plurality of templates include a plurality of first templates and at least one second template, wherein the hot spot marked area included in each of the first templates is smaller than the hot spot marked area included in the second template, and the first template The second template is surrounded by the plurality of first templates. 2. The repair method of claim 1, further comprising: According to the second layout, a photomask of the semiconductor wafer is provided. 3. The repairing method of claim 1, wherein the step of obtaining the hot spot marked area according to the first layout of the semiconductor wafer further comprises: receiving an integrated circuit design layout data of the semiconductor wafer; performing an optical proximity correction procedure on the integrated circuit design layout data to obtain the first layout; and According to a plurality of process parameters, the first layout is analyzed to obtain the hot spot marked area. 4 . The repairing method of claim 1 , wherein the area of the area to be repaired is larger than the area of the hot spot marked area. 5 . 5 . The repairing method of claim 1 , wherein the area of each template is determined by the repairing procedure according to the area of the area to be repaired. 6 . 6. A repair method for optical proximity correction, characterized in that, comprising: obtaining at least one hot spot marked area according to a first layout of a semiconductor wafer; obtaining a to-be-repaired area and a non-hot-spot area in the first layout according to the hot-spot marked area, wherein the to-be-repaired area includes the hot spot marked area; Divide the area to be repaired into multiple templates; performing a repair procedure on each of the templates; and providing a second layout according to each said template that has been repaired and the hotspot free area, Wherein the area of the to-be-repaired area is larger than the area of the hot spot marked area, The area of each of the templates is determined by the repair procedure according to the area of the area to be repaired or the number of hot spots in the hot spot marked area, The plurality of templates include a plurality of first templates and at least one second template, wherein the hot spot marked area included in each of the first templates is smaller than the hot spot marked area included in the second template, and the first template The second template is surrounded by the plurality of first templates. 7. The repair method of claim 6, further comprising: According to the second layout, a photomask of the semiconductor wafer is provided. 8. The repairing method of claim 6, wherein the step of obtaining the hot spot marked area according to the first layout of the semiconductor wafer further comprises: receiving an integrated circuit design layout data of the semiconductor wafer; performing an optical proximity correction procedure on the integrated circuit design layout data to obtain the first layout; and According to a plurality of process parameters, the first layout is analyzed to obtain the hot spot marked area.

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