JP2005191835A - Driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit for preventing any erroneous operation when the potential difference of a wiring inductance due to the change of charging currents is turned into the positive bias of an element input. <P>SOLUTION: This driving circuit 40 in a booth strap system to be charged and used by making charging currents flow by a charging capacitor C1 and a charging resistance R4 is configured to drive an upper arm switching element Q5. A pull-down resistance R5 is pulled down from the gate of a Q2 to the output side of a charging resistance R4 in order to prevent the erroneous operation of the Q2 when any potential difference due to the change of a wiring inductance and the charging currents to be inputted to the gate of the MOSFET of the Q2 is turned into a positive bias. Thus, the erroneous operation of the Q2 is prevented, and arm short-circuit is prevented from being generated owing to the erroneous operation from the Q2 to a Q5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a bootstrap driving circuit that drives a switching element having a bridge circuit or an arm configuration.

  There is a technique in which a drive circuit for driving a switching element of a bridge circuit is performed by a bootstrap system. In the bridge circuit, the switching element has an arm configuration, and includes an upper arm switching element and a lower arm switching element. The upper arm switching element and the lower arm switching element are alternately operated by the chopper control in each drive circuit, and a pulse signal is output.

  Conventionally, the circuits for driving the upper arm switching element and the lower arm switching element of the arm configuration are each operated by a floating power source. In recent years, a bootstrap system that does not require the use of a floating power supply and requires a small number of power supplies has become widespread. In the bootstrap system, a charging capacitor is charged when the lower arm switching element is ON, and when the lower arm switching element is OFF, the power is used as a power source for a circuit that drives the upper arm switching element.

FIG. 6 shows a circuit diagram of the prior art. The prior art of FIG. 6 uses a bootstrap system. The circuit is divided into an upper side and a lower side, and the upper arm switching element Q5 and the lower arm switching element Q6 are driven by the upper and lower circuits, respectively.
The lower arm switching element drive circuit 20 outputs a square wave signal to drive the switching of Q6. The upper arm switching element drive IC 10 performs switching driving of Q5. The upper arm switching element drive IC 10 outputs a square wave signal having a phase opposite to that of the lower arm switching element drive circuit 20. This signal drives the upper arm switching element Q5 through Q1, Q2 and Q3, Q4 CMOS inverters. Q1, Q2, Q3, and Q4 constitute a part of a circuit that drives the upper arm switching element Q5.

The charging capacitor C1 is a bootstrap charging capacitor.
In the present application, a conventional drive includes a diode D1, a charging capacitor C1, an upper arm switching element drive IC 10, two inverters Q1, Q2, Q3, and Q4, an output resistor R1, a resistor R2, a charging resistor R4, and the like surrounded by an alternate long and short dash line. Called circuit 30.

  The charging resistor R4 is for preventing an inrush current of the charging current of the charging capacitor C1. Without R4, the inrush current of the charging capacitor C1 is very large, and a potential difference caused by a change in current and wiring inductance may lead to malfunction or damage of the circuit, so a resistor R4 is inserted. Further, the upper arm switching element drive IC 10 is prevented from being damaged due to a change in the midpoint potential between Q5 and Q6 due to switching of Q5 and Q6. The midpoint potential of the prior art is the reference potential of the upper arm switching element, which is the potential of the wiring connecting the output side of the charging resistor 4, the source of Q5, and the drain of Q6. The charging resistor R4 cannot be placed between the terminals 1 and R2 of the upper arm switching element drive IC 10. This is because the potential difference between both ends of R4 enters the gate of Q2 due to the charging current flowing through R4 during charging, causing Q2 to malfunction.

The operation of this circuit is shown below using a part of the timing chart of FIG.
The upper arm switching element Q5 and the lower arm switching element Q6 are driven by square waves having opposite phases. The upper arm switching element Q5 is driven by the upper arm switching element drive IC10, the Q1 and Q2 CMOS inverters, and the Q3 and Q4 CMOS inverters. The lower arm switching element drive circuit 20 drives the lower arm switching element Q6. Square-wave outputs are output by the upper arm switching element drive IC 10 and the lower arm switching element drive circuit 20 with their respective timings controlled by a CPU (not shown). As a result, Q5 and Q6 are turned ON alternately.

  The gate-source voltage Vgs of Q2 in FIG. 7 is due to a square wave from the upper arm switching element drive IC 10 through the output resistor R1. With this square wave, Q2 is turned ON / OFF. When Vgs of Q2 is High, Q2 is ON, Q1 is OFF, Q3 is ON, and Q4 is OFF, so that the gate of Q5 becomes High like Vgs of Q5 shown in FIG. 7, and Q5 is also ON. Become.

  When the Vgs of Q2 is Low, Q2 is OFF, Q1 is ON, Q3 is OFF, Q4 is ON, so that the gate of Q5 is Low and Q5 is also OFF. This is normal operation. That is, Vgs of Q2 and Vgs of Q5, and ON / OFF of Q2 and Q5 are synchronized as a result.

However, the triangular waveform in FIG. The waveform of the Vgs triangle peak of Q2 and the waveform of Vgs of Q5 in FIG. 7 will be referred to in “Problems to be Solved by the Invention”.
When Vgs of Q2 and Vgs of Q5 are High, Q5 is ON, and Q6 is OFF by driving a square wave with an antiphase. When Vgs of Q2 and Vgs of Q5 are Low, Q6 is ON by driving an antiphase square wave.

  Next, when Q5 is OFF and Q6 is ON, a current flows from Vcc through the charging capacitor C1, charging resistors R4 and Q6 to the ground, and the charging capacitor C1 is charged. At this time, a potential difference is generated in the wiring through which the charging current flows due to a change in the charging current flowing through the wiring inductance L. Therefore, a DC voltage of Vcc is applied to the charging capacitor C1, the charging resistor R4, and the wiring inductance L. In a circuit in which a DC power supply is added to a capacitor, resistor, and inductance connected in series, the current peaks in a peak as a transient phenomenon. Since the voltage across the charging resistor R4 is obtained by multiplying the flowing current by the resistance value, it takes a peak in the same mountain shape. This is VR4 of R4 in FIG. This transient occurs every time Q6 is turned on and charging starts. This is repeated in FIG.

A drive circuit for driving the inverter is described in Patent Document 1, for example, and a drive circuit adopting a bootstrap system is described in Patent Document 2, for example.
Japanese Patent Laid-Open No. 10-75578 “Inverter Control Device” JP 2002-330064 “Bootstrap circuit”

  However, in the prior art circuit, the MOSFET Q2 may be erroneously turned ON during charging. Due to the wiring inductance L of the substrate pattern or the like, a potential difference is caused by the change in charging current di / dt. When the charging current is flowing, the gate voltage of Q2 is Low and Q2 is OFF. If the wiring inductance in the wiring from the terminal 1 of the upper arm switching element drive IC 10 to the source of Q2 is L, the potential difference due to the change in the charging current is ΔV = L (di / dt). If this potential difference is applied through R2 between the gate and source of Q2 of the MOSFET and exceeds the ON threshold value Vth of Q2, Q2 is erroneously turned ON. When Q2 is erroneously turned ON, the gates of Q3 and Q4 are set to Low and Q3 is erroneously turned ON and Q4 is erroneously turned OFF. As a result, the gate of Q5 becomes High and Q5 is erroneously turned ON. As a result, the upper arm switching element Q5 and the lower arm switching element Q6 are simultaneously turned ON, so that the arm is short-circuited with the DC power source VB and the ground, and the upper arm switching element and the lower arm switching element are damaged due to an overcurrent or the like. There is danger.

Note that when a charging current of the charging capacitor C1 flows, a potential difference is generated between both ends of the charging resistor R4. If the charging current is i, the potential difference at both ends of R4 is VR4 = R4 · i.
FIG. 7 shows a time chart during abnormal operation in the prior art. When the gate-source voltage Vgs of Q2 is Low, Q6 is turned ON, and the charging capacitor C1 is charged. However, when the potential difference ΔV = L (di / dt) generated by the change of the wiring inductance and the charging current, Q2 A positive bias is generated in Vgs. This positive bias is the same as the above-mentioned voltage VR4 of R4, and is a result of an excessive phenomenon caused by the application of a DC voltage of Vcc to the charging capacitor C1, the charging resistor R4, and the wiring inductance L. In a circuit in which a DC power supply is added to a capacitor, resistor, and inductance connected in series, the current, that is, the charging current, takes a peak as a transient phenomenon.
Due to this change in current and the like, the potential difference is generated as a positive bias and takes a peak in the form of a mountain. This is the waveform of the triangular peak of Vgs of Q2.

  When the positive bias voltage exceeds the ON threshold value Vth of Q2, Q2 is erroneously turned ON, and when Vgs of Q2 falls below the threshold value of Q2 on the descending triangle, Q2 is turned OFF. As a result, the output of Q2 outputs a pulse signal that is low only while Vgs of Q2 is larger than the threshold value of ON of Q2, that is, during the erroneous ON of Q2. This becomes an erroneous pulse signal and is output from Q2. The inputs of Q3 and Q4 are the outputs of Q1 and Q2, and they malfunction as Q3 erroneous ON and Q4 erroneous OFF only during the Low pulse period. The Q3 and Q4 CMOS inverters input a pulse having a high malfunction period to the gate of the upper arm switching element Q5.

  This is a positive pulse in Vgs of Q5 in FIG. 7, that is, Low of the gate-source voltage of Q5. Due to this positive pulse input, the upper arm switching element Q5 is also erroneously turned ON. As a result, an arm short circuit occurs when both the upper arm switching element Q5 and the lower arm switching element Q6 are turned ON.

  Therefore, an object of the present invention is to provide a drive circuit that prevents the potential difference due to the change in the wiring inductance and the charging current from becoming a positive bias of the switching elements that constitute the drive circuit.

    According to the present invention, there is provided a bootstrap driving circuit for driving a bridge circuit composed of an upper arm switch and a lower arm switch. The capacitor is charged and discharged according to the state of the bridge circuit, and the capacitor A first resistor provided on a path connecting the bridge circuit to the bridge circuit, a signal source for generating a signal for driving the upper arm switch, an output of the signal source to the control terminal, and a main current The terminal includes a first transistor connected to an input side of the first resistor on a path connecting the capacitor and the bridge circuit, and the upper arm switch based on a signal generated by the signal source A circuit for driving and a control terminal of the first transistor on a path connecting the capacitor and the bridge circuit; A second resistor connected to the input side of the first resistor, and a control terminal of the first transistor connected to the output side of the first resistor on the path connecting the capacitor and the bridge circuit. This is solved by a drive circuit comprising three resistors.

Further, it is included in a circuit for driving the upper arm switch, the output of the first transistor is given to the control terminal, and the main current terminal is connected to the output side of the first resistor on the path connecting the capacitor and the bridge circuit The second transistor is provided in the above drive circuit.
The second transistor is included in a circuit for driving the upper arm switch, and the output of the first transistor is given to the control terminal, and the main current terminal is connected to the capacitor on the path connecting the bridge circuit. It may be connected to the input side of one resistor.

  Further, the above problem is that the resistance value of the third resistor and the resistance value of the fourth resistor, which is the output resistance of the signal source, are the main current of the first transistor through which the charging current changes and the charging current flows. This is solved by a drive circuit that lowers the voltage at the control terminal of the first transistor caused by the positive bias due to the wiring inductance on the input side from the terminal below the ON threshold of the first transistor.

  According to the present invention, even if there is a transistor in which a charging current and a control terminal are connected in a drive circuit, a third resistor is provided as a pull-down resistor at the control terminal of the element, and on the output side of the charging resistor that is the first resistor. By pulling down and wiring to the position of the midpoint potential on the low potential side, malfunction of the element can be prevented. By pulling down the output side of the first resistor, that is, to a lower potential, it is possible to prevent a malfunction of the transistor that causes a positive bias due to a change in wiring inductance and a charging current.

  Further, even when the charging current of the bootstrap charging capacitor is increased or the current change di / dt is increased, the malfunction of the element can be prevented by adjusting the constant such as a pull-down resistor as the third resistor. .

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 shows an overall circuit diagram. The drive circuit 40 surrounded by the alternate long and short dash line is the bootstrap drive circuit 40 of the present invention. The drive circuit 40 is composed of an inverter composed of switching elements of the upper arm switching element drive ICs 10, Q1, Q2, an inverter composed of switching elements of Q3, Q4, an output resistor R1, a charging resistor R4, a diode D1, and the like. The

There are an upper arm switching element Q5 and a lower arm switching element Q6 of the MOSFET. Q5 and Q6 take an arm configuration. The upper arm switching element Q5 and the lower arm switching element Q6 constitute a bridge circuit.
The upper arm switching element Q5 is an upper arm switch, and the lower arm switching element Q6 is a lower arm switch.

  The lower arm switching element drive circuit 20 drives the lower arm switching element Q6. Upper arm switching element Q5 is driven by CMOS inverters of upper arm switching element drive ICs 10, Q1, Q2 and Q3, Q4. The upper arm switching element drive IC 10 is a signal source that generates a signal for driving the upper arm switch.

  The lower arm switching element drive circuit 20 outputs a square wave signal to drive the switching of Q6. However, the contents of the lower arm switching element drive circuit 20 may achieve the above function. The terminal 1 of the lower arm switching element drive circuit 20 is ground, the terminal 2 is a signal output, and the terminal 3 is a power supply terminal.

  The upper arm switching element drive IC 10 passes a square wave signal having an opposite phase to that of the lower arm switching element drive circuit 20 for switching and driving Q6, through the output resistor R1, and is in the preceding stage of the two-stage configuration of Q1 and Q2 of the next MOSFET. Output to the CMOS inverter. This signal drives the upper arm switching element Q5 of the MOSFET through the CMOS inverter at the subsequent stage of the MOSFETs Q3 and Q4. Two CMOS inverters are provided for signal consistency. The terminal 1 of the upper arm switching element drive IC 10 is ground, the terminal 2 is a signal output, and the terminal 3 is a power supply terminal.

Q2 is a first transistor and Q4 is a second transistor. A source which is a main current terminal for both Q2 and Q4 is connected on a path connecting the capacitor and the bridge circuit.
In this embodiment, Q1, Q2, Q3, Q4, etc. constitute a circuit for driving the upper arm switch. In the MOSFET, the gate is the control terminal and the source is the main current terminal. Q1 and Q3 are P-channel MOSFETs, and Q2, Q4, Q5, and Q6 are N-channel MOSFETs.

  The charging capacitor C1 is a bootstrap charging capacitor. The current flowing through the charging capacitor C1 is mainly determined by the charging resistor R4, and is connected to the connection line between the source of Q5 and the drain of Q6 through R4. The charging capacitor C1 is charged / discharged according to the state of the bridge circuit.

The diode D1 prevents the power charged in the charging capacitor C1 from flowing back into the power source Vcc and the lower arm switching element drive circuit 20 with current.
Charging current Rc flows through charging resistor R4 when power supply Vcc charges charging capacitor C1 when lower arm switching element Q6 is ON. It is provided between the sources of Q2 and Q4 on the path connecting the charging capacitor and the bridge circuit.

The charging resistor R4 is a first resistor. A resistor R2 connecting the gate and source of Q2 is a second resistor. The pull-down resistor R5 is a third resistor. The output resistor R1 is a fourth resistor.
The pull-down resistor R5, which is a feature of the present invention, is pulled down to the lower potential of the charging resistor R4, that is, to the output side when the charging current flows through the gate of Q2. The output side is the output side shown in FIG. This also means pulling down to the midpoint potential. The midpoint potential is the potential at the point where the line is connected from the source between the source of Q4 and the source between the source of the upper arm switching element Q5 and the drain of the lower arm switching element Q6.

Thereby, it is possible to cancel the positive bias of the gate-source voltage Vgs that occurs due to the change of the wiring inductance and the charging current and appears at the gate that is the signal input portion of Q2.
A bootstrap circuit will be described below.
When the lower arm switching element Q6 is ON, a current flows in the order of the power source Vcc → the diode D1 → the charging capacitor C1 → the charging resistor R4 → the drain of the lower arm switching element Q6 → the source → the ground. The charging capacitor C1 is charged by this charging current. When the lower arm switching element Q6 is turned off and the upper arm switching element Q5 is turned on, the power of the charging capacitor C1 is supplied to the CMOS inverters Q3, Q4 of the terminals 3, Q1, Q2 of the upper arm switching element drive IC10. Power is supplied to the CMOS inverter. This eliminates the need to supply power to the upper arm switching element drive ICs 10, Q1 and Q2 CMOS inverters, and Q3 and Q4 CMOS inverters for driving the upper arm switching element Q5 with a floating power supply. From the alternate switching operation of the upper arm switching element Q5 and the lower arm switching element Q6, a pulse signal is output to “output” in the circuit diagram of FIG. In this pulse, the upper potential is the DC power supply VB and the lower potential is the ground potential, that is, the ground potential.

  Next, the charging resistor R4 prevents an inrush current of the charging current of the charging capacitor C1. Without R4, the inrush current of the charging capacitor C1 is very large, and thus di / dt is also large, and the potential difference generated by the wiring inductance is also large. This potential difference may lead to malfunction or damage of the circuit, so a charging resistor R4 is inserted. Q6 is ON during charging, Q5 is OFF, and Q4 is also ON at this time. Therefore, even if the charging resistor R4 has a potential difference between the source of Q2 and the source of Q4, there is no malfunction.

Further, the upper arm switching element drive IC 10 is prevented from being damaged due to the change of the midpoint potential due to the switching of Q5 and Q6.
In addition, a diode D3 is added. D3 prevents a negative bias from being applied to the gate of Q2. The diode D2 serves to prevent erroneous ON in which the generated potential difference charges the MOS parasitic capacitance and the like.

Specific wiring will be described below.
The lower arm switching element drive circuit 20 is grounded at the terminal 1 together with the source of the lower arm switching element Q6, and the terminal 2 is connected to the gate of Q6. The terminal 3 of the lower arm switching element drive circuit 20 is connected to the power supply Vcc and the anode of the diode D1. The cathode of the diode D1 is connected to the charging capacitor C1, the terminal 3 of the upper arm switching element drive IC 10, the source of the MOSFET Q1, and the resistor R3. The other side of the charging capacitor C1 connected to the diode D1 is connected to the terminal 1 of the upper arm switching element drive IC 10, the anode of the diode D3, the resistor R2, the source of the MOSFET Q2, and the charging resistor R4. The terminal 2 of the upper arm switching element drive IC 10 is connected to the output resistor R1. The other end of the output resistor R1 is connected to the gate of Q1, the gate of Q2, the cathode of D3, the resistor R2, and the pull-down resistor R5. The drain of Q1 is connected to the anode of diode D2, the gate of Q3, and the gate of Q4. The cathode of D2 is connected to the drain of Q2. The other end of the resistor R3 is connected to the source of Q3. The drain of Q3 is connected to the anode of D4 and the gate of Q5. The source of Q5 is connected to the source of Q4, the drain of Q6, the other end of the charging resistor R4, the other end of the pull-down resistor R5, and the output of the circuit. The drain of Q5 is connected to the + terminal of DC power supply VB. The negative side of the DC power supply VB is grounded.

The operation of the driving circuit according to the present invention will be described with reference to the time chart of FIG.
The upper arm switching element drive IC 10 outputs a square wave that drives the upper arm switching element Q5 of the MOSFET. This square wave passes through the output resistor R1 and is input to the Q1 and Q2 CMOS inverters. Therefore, the gate-source voltage of Q2 is the square wave of FIG. Here, since the gate of Q2 is pulled down to the output side of the charging resistor R4 and the midpoint potential by the pull-down resistor R5, the positive bias of the potential difference due to the change of the wiring inductance and the charging current as seen in the prior art is not seen. .

  This square wave is inverted by the CMOS inverter at the front stage of Q1 and Q2, is output in reverse phase, and is input to the CMOS inverter at the subsequent stage of the next Q3 and Q4. Therefore, the CMOS inverters Q3 and Q4 are also inverted and have opposite phases, so that they return to the square wave of the original phase and are input to Q5. Therefore, the gate-source voltage Vgs of Q5 is input as a result of synchronization with the gate-source voltage of Q2 as shown in FIG. 2, and drives the upper arm switching element Q5.

The lower arm switching element drive circuit 20 is driven by inputting a square wave having the opposite phase to the input of Q5 to the lower arm switching element Q6. Therefore, Q5 and Q6 are driven alternately.
When Q5 is OFF and Q6 is ON, a current flows through the charging capacitor C1 and charging is performed.

Therefore, when Vgs of Q2 and Vgs of Q5 are High, Q5 is ON, and Q6 is OFF by driving an antiphase square wave. When Vgs of Q2 and Vgs of Q5 are Low, Q6 is ON by driving an antiphase square wave.
When Q5 is OFF and Q6 is ON, current flows from Vcc through the charging capacitor C1 and the charging resistors R4 and Q6, and the charging capacitor C1 is charged. At this time, a potential difference is generated in the wiring through which the charging current flows due to changes in the wiring inductance L and the charging current. Therefore, a DC voltage of Vcc is applied to the charging capacitor C1, the charging resistor R4, and the wiring inductance L. In a circuit in which a DC power supply is added to a capacitor, resistor, and inductance connected in series, the current peaks in a peak as a transient phenomenon. Since the voltage across the charging resistor R4 is obtained by multiplying the flowing current by the resistance value, it takes a peak in the same mountain shape. This is VR4 of R4 in FIG. This transient occurs every time Q6 is turned on and charging starts.

  FIG. 3 shows the calculation of the gate-source voltage Vgs of Q2 when the pull-down resistor R5 is used. The circuit of FIG. 3 is the same as that of FIG. The pull-down resistor R5 of the present invention and its wiring are pulled down so that a positive bias of a potential difference due to changes in wiring inductance and charging current is kept low, and a high voltage does not rotate at the gate of the MOSFET Q2. Thereby, Q2 is not erroneously turned ON.

The pull-down resistor R5 connects the gates of Q1 and Q2 to the source of Q4. This is a route through which charging current flows, but is separated from the source of Q2 by a charging resistor R4.
By this pull-down resistor R5, the gate-source voltage of Q2 is derived as follows. Each voltage is defined as shown in FIG. Voltage generated in wiring inductance: VL (between terminals 1 and R2 of upper arm switching element drive IC 10), voltage generated in output resistance R1 of upper arm switching element drive IC 10: V1, voltage generated in charging resistance R4: V4, The voltage generated at the pull-down R5 is V5. Here, for simplification of the calculation formula, R2 is ignored. Further, the terminal 1 and the terminal 2 of the upper arm switching element drive IC 10 have the same potential when the output of the terminal 2 is L.

VL + V4 = V1 + V5 (1), Vgs = V5−V4 (2)
V5 = (R5 / (R1 + R5)) * (V1 + V5) (3)
From the above, replacing (V1 + V5) in (3) using (1) and substituting (3) in (2) ∴ Vgs = (R5VL−R1V4) / (R1 + R5)
Is obtained. Therefore, if the voltage VL generated in the wiring inductance and the charging current flowing through the charging resistor R4 are known, the voltage across the terminal R4: V4 can be known, so that Vgs is determined by the charging current flowing through R4 and the resistance values of R1 and R5. Understand. R1V4 with V4 is a negative term. Therefore, by adjusting the resistance values of the output resistor R1 and the pull-down resistor R5, that is, the fourth resistor and the third resistor, Vgs is made lower than the gate ON voltage of Q2. This prevents erroneous ON of Q2.

Further, as shown in FIG. 4, Vgs of Q2 can also be expressed by a current and a resistance value. The drive circuit shown in FIG. 4 is the same as that shown in FIGS.
Current flowing through R1: I1, current flowing through R2, I2, current flowing through R4: I4, current flowing through R5: I5. Vgs of Q2 can be expressed by the following equation.

Ｖ Vgs = I5R5-I4R4
(Modification of Embodiment 1)
The present invention can be applied to a drive circuit such as a DC chopper circuit, an H bridge, or a full bridge circuit. The upper arm switching element and the lower arm switching element may use IGBTs.

(Embodiment 2)
FIG. 5 shows a circuit diagram of the second embodiment. In the second embodiment, the position of the charging resistor R4 and the pull-down destination of the pull-down resistor R5 are changed, and a diode D4 is added.
Description of the same parts as those in the first embodiment is omitted. As shown in FIG. 7, the charging resistor R4 is placed between the point where the charging current flows and the point connected to the source of Q4 and the point connecting the source of Q5 and the drain of Q6. That is, it is placed on the output side of the source of Q4. The pull-down resistor R5 is placed between the gate of Q2, the connection line between the source of Q5 and the drain of Q6, and the line through which the charging current flows. That is, it pulls down to the output side of the charging resistor R4. However, in this case, it is necessary to place the diode D4 between the drain of Q4 and the gate of Q5, as with the diode D2. The diode D4 serves to prevent erroneous ON in which the generated potential difference charges the MOS parasitic capacitance and the like.

  Other configurations and operations are the same as those in the first embodiment. This form also prevents Q2 from being erroneously turned on because the gate of Q2 is pulled down to the output side of the charging resistor R4 having a lower potential. The analysis of the gate-source voltage Vgs of Q2 in the first embodiment is also applied to the second embodiment.

1 shows a circuit diagram of a first embodiment of the present invention. It is a timing chart of the present invention. It is a figure explaining the circuit of this invention with a voltage. It is a figure explaining the circuit of this invention with an electric current. It is a circuit diagram of a 2nd embodiment of the present invention. It is a circuit of a prior art. It is a timing chart of a prior art and abnormal operation | movement.

Explanation of symbols

10 ... Upper arm switching element drive IC
20 ... lower arm switching element drive circuit 30 ... conventional drive circuit 40 ... drive circuit C1 ... charging capacitors D1, D2, D3, D4 ... diodes Q1, Q2, Q3, Q4,.・ MOSFET
Q5... Upper arm switching element Q6... Lower arm switching element R1... Output resistance R2, R3... Resistance R4... Charging resistance R5. ·Power supply

Claims (4)

In a bootstrap drive circuit that drives a bridge circuit composed of an upper arm switch and a lower arm switch,
A capacitor that is charged and discharged according to the state of the bridge circuit;
A first resistor provided on a path connecting the capacitor and the bridge circuit;
A signal source for generating a signal for driving the upper arm switch;
A first transistor connected to the input side of the first resistor on the path connecting the capacitor and the bridge circuit, the output of the signal source being given to the control terminal; A circuit for driving the upper arm switch based on a signal generated by a source;
A second resistor connecting a control terminal of the first transistor to an input side of the first resistor on a path connecting the capacitor and the bridge circuit;
And a third resistor that connects a control terminal of the first transistor to an output side of the first resistor on a path connecting the capacitor and the bridge circuit. An output of the first resistor on a path included in a circuit for driving the upper arm switch, the output of the first transistor being given to a control terminal, and a main current terminal connecting the capacitor and the bridge circuit The driving circuit according to claim 1, further comprising a second transistor connected to the side. Included in a circuit for driving the upper arm switch, an output of the first transistor is given to a control terminal, and an input of the first resistor on a path where a main current terminal connects the capacitor and the bridge circuit The driving circuit according to claim 1, further comprising a second transistor connected to the side. The resistance value of the third resistor and the resistance value of the fourth resistor, which is the output resistance of the signal source, are a change in charging current for charging the capacitor and a main current terminal of the first transistor through which the charging current flows. 4. The drive circuit according to claim 1, wherein a voltage of the control terminal of the first transistor caused by a positive bias due to a wiring inductance on the input side is lower than an ON threshold value of the first transistor. 5.

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