JP2005191248A - Semiconductor device, electronic circuit device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it difficult to separate the joined portion of a contact member and a wiring. <P>SOLUTION: This device comprises a first wiring 34 formed in an active region 104 which is a part of a chip in a plane arrangement; an interlayer insulating film 40 formed in a region containing on the first wiring 34; a second wiring 44 which is located in the active region 104 and formed on the interlayer insulating film 40; a via contact member 42 which is located in the active region 104, and connects the first wiring 34 to the second wiring 44 by being embedded in the interlayer insulating film 40; a dummy conductive film 56 which is located adjacent to the active region 104 in the planar layout, and on an end side in the longitudinal direction of the chip of the active region 104, and is formed in the same layer as the second wiring 44; and a dummy contact member 55 which is embedded in the interlayer insulating film 40 and is joined to the dummy conductive film 56. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, an electronic circuit device, and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device, an electronic circuit device, and a manufacturing method thereof that make it difficult to separate a connection portion between a contact member and a wiring.

  FIG. 10 is a cross-sectional view showing the structure of a chip end portion 200a of a conventional general semiconductor device. A plurality of interlayer insulating films 202,..., 210, 220 are stacked on the silicon substrate 201. Wirings (for example, wirings 214 and 224) are formed between these interlayer insulating films. Each wiring is connected to another wiring by a via contact member (for example, via contact member 222) embedded in the interlayer insulating film. The uppermost wiring 224 and the interlayer insulating film 220 are covered with a passivation film 230.

Since the main component of the interlayer insulating film is silicon oxide, its thermal expansion coefficient is different from that of the silicon substrate. For this reason, when a semiconductor device is mounted on a wiring board by soldering, thermal stress may occur in the semiconductor device. Also, physical stress may be applied from the wiring board after mounting. In these cases, the semiconductor device is bent up and down. In the case where the semiconductor device is bent up and down, if the density of the via contact in the region close to the end of the semiconductor device is low, the contact member and the wiring are separated from each other in that region, and a gap (for example, indicated by reference numeral 224a in FIG. May be formed. If the gap is formed, poor conduction is likely to occur, and the reliability of the semiconductor device is reduced. This tendency is particularly prominent when the semiconductor device is elongated or when the diameter of the contact member is reduced as the wiring becomes thinner.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device, an electronic circuit device, and a method of manufacturing the same, in which it is difficult to separate the joint portion between the contact member and the wiring. It is in.

In order to solve the above problems, a semiconductor device according to the present invention is a semiconductor device formed on an elongated chip,
An interlayer insulating film formed on the first wiring;
A connection hole formed in the interlayer insulating film and located on the first wiring;
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole and on the end side in the longitudinal direction of the chip from the connection hole;
A via contact member embedded in the connection hole;
A dummy contact member embedded in the dummy connection hole;
A second wiring formed on the via contact member and the interlayer insulating film and connected to the first wiring by the via contact member;
A dummy conductive film formed on the dummy contact member and the interlayer insulating film.

  According to this semiconductor device, the dummy conductive film and the dummy contact member are formed in the same layer as the second wiring and the via contact member, respectively, next to the second wiring and the via contact member. For this reason, an anchor effect increases and it becomes difficult to peel the connection part of a 2nd wiring and a via contact member. Therefore, the reliability of the semiconductor device is increased.

Another semiconductor device according to the present invention is a semiconductor device formed in an elongated chip,
An interlayer insulating film formed on the plurality of first wirings;
A plurality of connection holes formed on the interlayer insulating film and positioned on the plurality of first wirings;
A plurality of via contact members embedded in each of the plurality of connection holes;
A plurality of second wirings formed on the interlayer insulating film and on each of the plurality of via contact members, and connected to the plurality of first wirings by the via contact members;
Comprising
The chip includes
A contact high-density region having a high density of the via contact member;
Formed in a position overlapping the contact high-density region in the longitudinal direction of the chip, a contact low-density region in which the density of the via contact member is lower than the contact high-density region is formed,
further,
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole in the low-density contact region and on the end side in the longitudinal direction of the chip from the connection hole;
A dummy contact member embedded in the dummy connection hole;
A dummy conductive film formed on the dummy contact member and the interlayer insulating film.

  According to this semiconductor device, the dummy conductive film and the dummy contact member are formed in the same layer as the second wiring and the via contact member, respectively, next to the second wiring and the via contact member in the contact low density region. Has been. For this reason, in the contact low density region, the anchor effect is increased and the connection portion between the second wiring and the via contact member is difficult to peel off. Therefore, the reliability of the semiconductor device is increased.

  The dummy conductive film may be formed of the same material as the second wiring, and the dummy contact member may be formed of the same material as the via contact member. In this case, the second wiring and the dummy conductive film have at least one of a titanium film and a titanium nitride film on the lower surface, and the via contact member and the dummy contact member are connected to the second wiring or the dummy conductive film. The connecting portion may be made of tungsten.

  The present invention is particularly effective when the length in the longitudinal direction with respect to the width of the chip is 8 times or more. The present invention is also particularly effective when the semiconductor device has a silicon substrate and the interlayer insulating film is a silicon oxide film.

Other semiconductor devices according to the present invention are:
A semiconductor element formed on a semiconductor substrate;
An interlayer insulating film formed on the semiconductor element and the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the semiconductor element;
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole and on the end side in the longitudinal direction of the chip;
A contact member embedded in the connection hole and located on the semiconductor element;
A dummy contact member embedded in the dummy connection hole;
A wiring formed on the contact member and the interlayer insulating film, and connected to the semiconductor element by the contact member;
A dummy conductive film formed on the dummy contact member and the interlayer insulating film.

  According to this semiconductor device, the dummy conductive film and the dummy contact member are formed in the same layer as the wiring and the contact member, respectively, next to the wiring and the contact member. For this reason, an anchor effect increases and the connection part of wiring and a contact member becomes difficult to peel. Therefore, the reliability of the semiconductor device is increased.

An electronic circuit device according to the present invention includes:
A wiring board;
A semiconductor device mounted on the wiring board;
Comprising
The semiconductor device includes:
Is formed into an elongated tip,
An interlayer insulating film formed on the first wiring;
A connection hole formed in the interlayer insulating film and located on the first wiring;
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole and on the end side in the longitudinal direction of the chip from the connection hole;
A via contact member embedded in the connection hole;
A dummy contact member embedded in the dummy connection hole;
A second wiring formed on the via contact member and the interlayer insulating film and connected to the first wiring by the via contact member;
A dummy conductive film formed on the dummy contact member and the interlayer insulating film.
According to this electronic circuit device, the connection portion between the second wiring and the via contact member is hardly peeled in the semiconductor device. Therefore, the reliability of the electronic circuit device is increased.

Other electronic circuit devices according to the present invention are:
A wiring board;
A semiconductor device mounted on the wiring board;
Comprising
The semiconductor device includes:
Is formed into an elongated tip,
A semiconductor element formed on a semiconductor substrate;
An interlayer insulating film formed on the semiconductor element and the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the semiconductor element;
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole and on the end side in the longitudinal direction of the chip;
A contact member embedded in the connection hole and located on the semiconductor element;
A dummy contact member embedded in the dummy connection hole;
A wiring formed on the contact member and the interlayer insulating film, and connected to the semiconductor element by the contact member;
A dummy conductive film formed on the dummy contact member and the interlayer insulating film.
According to this electronic circuit device, the connection portion between the wiring and the contact member in the semiconductor device is difficult to peel off. Therefore, the reliability of the electronic circuit device is increased.

  In the electronic circuit device described above, the semiconductor device may be mounted on the wiring board by reflowing solder applied on the wiring board.

A method for manufacturing a semiconductor device according to the present invention includes:
Forming a first wiring in each of a plurality of elongated chip regions provided on a wafer-like semiconductor substrate;
Forming an interlayer insulating film on the first wiring;
A connection hole located on the first wiring is formed in the interlayer insulating film, and a dummy connection located next to the first wiring and on the end side in the longitudinal direction of the chip region from the first wiring. Forming a hole in each of the plurality of chip regions;
Embedding a via contact member connected to the first wiring in the connection hole and embedding a dummy contact member in the dummy connection hole;
Forming a second wiring on the interlayer insulating film and the via contact member, and forming a dummy conductive film on the interlayer insulating film and the dummy contact member.

Another method of manufacturing a semiconductor device according to the present invention is as follows.
Forming a semiconductor element in each of a plurality of elongated chip regions provided on a wafer-like semiconductor substrate;
Forming an interlayer insulating film on the semiconductor element;
A connection hole located on the semiconductor element is formed in the interlayer insulating film, and a dummy connection hole located next to the semiconductor element and on the end side in the longitudinal direction of the chip region from the semiconductor element Forming each chip region;
Embedding a contact member connected to the semiconductor element in the connection hole, and embedding a dummy contact member in the dummy connection hole;
Forming a wiring on the interlayer insulating film and the contact member, and forming a dummy conductive film located on the interlayer insulating film and the dummy contact member.

  In the manufacturing method of the semiconductor device described above, the step of embedding the via contact member and the dummy contact member includes a step of forming a conductive film in the connection hole, the dummy connection hole and on the interlayer insulating film, and a conductive film on the interlayer insulating film. May be a step of polishing and removing by CMP.

A method for manufacturing an electronic circuit device according to the present invention includes:
Forming a first wiring in each of a plurality of elongated chip regions provided on a wafer-like semiconductor substrate;
Forming an interlayer insulating film on the first wiring;
A connection hole located on the first wiring is formed in the interlayer insulating film, and a dummy connection located next to the first wiring and on the end side in the longitudinal direction of the chip region from the first wiring. Forming a hole in each of the plurality of chip regions;
Embedding a via contact member connected to the first wiring in the connection hole and embedding a dummy contact member in the dummy connection hole;
Forming a second wiring on the interlayer insulating film and the via contact member, and forming a dummy conductive film on the interlayer insulating film and the dummy contact member; A method for manufacturing an electronic circuit device, comprising:
A step of mounting the semiconductor device on a wiring board;

Another method of manufacturing an electronic circuit device according to the present invention is
Forming a semiconductor element in each of a plurality of elongated chip regions provided on a wafer-like semiconductor substrate;
Forming an interlayer insulating film on the semiconductor element;
A connection hole located on the semiconductor element is formed in the interlayer insulating film, and a dummy connection hole located next to the semiconductor element and on the end side in the longitudinal direction of the chip region from the semiconductor element Forming each chip region;
Embedding a contact member connected to the semiconductor element in the connection hole, and embedding a dummy contact member in the dummy connection hole;
Forming a wiring on the interlayer insulating film and the contact member, and forming a dummy conductive film positioned on the interlayer insulating film and the dummy contact member; A device manufacturing method comprising:
A step of mounting the semiconductor device on a wiring board;

  In each semiconductor device, electronic circuit device, and manufacturing method thereof, the first wiring and the second wiring are not limited to the first layer wiring and the second layer wiring, respectively. It also corresponds to the nth layer wiring and the (n + 1) th layer wiring.

BEST MODE FOR CARRYING OUT THE INVENTION

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a plan view of the main part of the electronic circuit device according to the first embodiment, and FIG. 1B is a side view of the main part of the electronic circuit device shown in FIG. In the electronic circuit device according to the present embodiment, the semiconductor device 10 is mounted on the wiring board 100. The semiconductor device 10 is formed in an elongated chip. This chip has, for example, a length in the longitudinal direction that is at least 8 times the width. The semiconductor device 10 is a face mount type semiconductor device, and is mounted on the wiring board 100 by reflowing solder applied in a pattern. The semiconductor device 10 is, for example, logic. When the electronic circuit device is a liquid crystal display device, the semiconductor device 10 is a driver of the liquid crystal display device. The wiring substrate 100 is formed by forming a wiring pattern on a flexible substrate made of, for example, a polyimide film.

  FIG. 2 is an enlarged view of a region surrounded by a broken line A in FIG. A plurality of pads 106 for connecting the semiconductor device 10 to the wiring substrate 100 are formed on the edge of the semiconductor device 10. An active region 104 is formed in a part of the semiconductor device 10. In the active region 104, a plurality of interlayer insulating films (not shown) and a plurality of wirings (not shown) positioned between these interlayer insulating films are formed. Each wiring is connected to another wiring by a via contact member embedded in the interlayer insulating film.

  A dummy region 108 is formed at a position adjacent to the active region 104 on the end side in the longitudinal direction from the active region 104. In the dummy region 108, a dummy Al alloy film (not shown), which is an example of a dummy conductive film, is formed in the same layer as each wiring. Each dummy Al alloy film is connected to each other by a dummy contact member (not shown) embedded in the interlayer insulating film. The dummy Al alloy film and the dummy contact member are not connected to the wiring of the active region 104 or the semiconductor element, and the wiring of the active region 104 and the via contact member are hardly separated.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. 3A to 3C, FIGS. 4A to 4C, and FIGS. 5A and 5B. 3, 4, and 5 are cross-sectional views corresponding to the AA cross section of FIG. 2.
First, as shown in FIG. 3A, one or a plurality of interlayer insulating films and wirings are formed in an elongated chip region provided on a wafer-like silicon substrate. At this time, the interlayer insulating film 20 is exposed on the surface. The interlayer insulating film 20 is mainly composed of silicon oxide. The silicon substrate is an example of a semiconductor substrate.

  Then, a photoresist film is applied on the interlayer insulating film 20, and a resist pattern is formed by exposing and developing the photoresist film. Next, by etching the interlayer insulating film 20 using this resist pattern as a mask, a connection hole (not shown) is formed in the active region 104, and a dummy connection hole 20c is formed in the dummy region.

  Next, a conductive film 8 made of a barrier layer (not shown) and a tungsten film is formed on the interlayer insulating film 20 and on the inner surfaces of the connection holes and the dummy connection holes 20c. At this time, a part of the conductive film 8 is embedded in each of the connection hole and the dummy connection hole 20c.

  Next, as shown in FIG. 3B, the conductive film 8 is polished and removed from the interlayer insulating film 20 by CMP. Thus, a via contact member (not shown) made of tungsten and a barrier layer is formed in the connection hole, and a dummy contact member 51 made of tungsten and a barrier layer is formed in the dummy connection hole 20c. The via contact member is connected to a wiring (not shown) formed under the interlayer insulating film 20, but the dummy contact member 51 is not connected to the wiring.

  Next, as shown in FIG. 3C, a barrier layer in which a Ti film and a TiN film are stacked is formed on the interlayer insulating film 20, the via contact member, and the dummy contact member 51. Next, an Al alloy film is formed on the barrier layer by a sputtering method. Next, a photoresist film is applied on the Al alloy film, and the photoresist film is exposed and developed to form a resist pattern. Next, by etching the Al alloy film and the barrier layer using this resist pattern as a mask, an Al alloy wiring 24 composed of the barrier layer and the Al alloy film is formed in the active region 104, and the barrier layer and the Al alloy film are formed in the dummy region 108. A dummy Al alloy film 52 is formed. In the Al alloy wiring 24, the lower barrier layer is joined to the upper end surface of the via contact member embedded in the interlayer insulating film 20 at a portion not shown, that is, tungsten. The dummy Al alloy film 52 has a lower barrier layer bonded to the upper end surface of the dummy contact member 51, that is, tungsten.

  Next, as shown in FIG. 4A, an interlayer insulating film 30 is formed on the interlayer insulating film 20, the Al alloy wiring 24 and the dummy Al alloy film 52 by, for example, a CVD method. The main component of the interlayer insulating film 30 is silicon oxide. Next, a connection hole 30 a located on the Al alloy wiring 24 and a dummy connection hole 30 b located on the dummy Al alloy film 52 are formed in the interlayer insulating film 30. The method for forming the connection hole 30 a and the dummy connection hole 30 b is the same as the method for forming the connection hole and the dummy connection hole 20 c in the interlayer insulating film 20.

  Next, a via contact member 32 made of tungsten and a barrier layer is buried in the connection hole 30a, and a dummy contact member 53 made of tungsten and a barrier layer is buried in the dummy connection hole 30b. The method for embedding the via contact member 32 and the dummy contact member 53 is the same as the method for embedding the via contact member and the dummy contact member 51 in the interlayer insulating film 20. The via contact member 32 has a lower end surface bonded to the Al alloy wiring 24, and a dummy contact member 53 has a lower end surface bonded to the dummy Al alloy film 52.

  Next, as shown in FIG. 4B, the Al alloy wiring 34 located in the active region 104 and the dummy Al alloy film 54 located in the dummy region 108 are formed on the interlayer insulating film 30. In the Al alloy wiring 34, the lower barrier layer is bonded to the upper end surface of the via contact member 32, that is, tungsten, and in the dummy Al alloy film 54, the lower barrier layer is bonded to the upper end surface of the dummy contact member 53, that is, tungsten. ing. The formation method of the Al alloy wiring 34 and the dummy Al alloy film 54 is the same as the formation method of the Al alloy wiring 24 and the dummy Al alloy film 52.

  Next, as shown in FIG. 4C, the interlayer insulating film 40 is formed on the interlayer insulating film 30, the wiring 34, and the dummy Al alloy film 54 by, for example, the CVD method. The main component of the interlayer insulating film 40 is silicon oxide. Next, a connection hole 40 a located on the Al alloy wiring 34 is formed in the interlayer insulating film 40, and a dummy connection hole 40 b located on the dummy Al alloy film 54 is formed. The method for forming the connection hole 40 a and the dummy connection hole 40 b is the same as the method for forming the connection hole and the dummy connection hole 20 c in the interlayer insulating film 20.

  Next, a via contact member 42 made of tungsten and a barrier layer is embedded in the connection hole 40a, and a dummy contact member 55 made of tungsten and a barrier layer is embedded in the dummy connection hole 40b. The method for embedding the via contact member 42 and the dummy contact member 55 is the same as the method for embedding the via contact member 32 and the dummy contact member 53. The lower end surface of the via contact member 42 is bonded to the Al alloy wiring 34, and the lower end surface of the dummy contact member 55 is bonded to the dummy Al alloy film 54.

  Next, as shown in FIG. 5A, an Al alloy wiring 44 located in the active region 104 and a dummy Al alloy film 56 located in the dummy region 108 are formed on the interlayer insulating film 40. The Al alloy wiring 44 has a lower barrier layer bonded to the upper end surface of the via contact member 42, that is, tungsten, and the dummy Al alloy film 56 has a lower barrier layer bonded to the upper end surface of the dummy contact member 55, that is, tungsten. ing. The formation method of the Al alloy wiring 44 and the dummy Al alloy film 56 is the same as the formation method of the Al alloy wiring 24 and the dummy Al alloy film 52. The pad 106 shown in FIG. 1 is formed simultaneously with the Al alloy wiring 44 and the dummy Al alloy film 56.

Next, as shown in FIG. 5B, a passivation film 46 made of a silicon nitride film or a laminated film of silicon oxide and silicon nitride is formed on the interlayer insulating film 40, the Al alloy wiring 44, and the dummy Al alloy film 56, for example, by CVD. Form by the method.
Next, although not shown in the drawing, an opening located on the pad 106 shown in FIG. 1 is formed in the passivation film 46, and after an electrical characteristic test is performed, the wafer-like silicon substrate is divided into chips by dicing.

  The semiconductor device 10 thus formed has the following structure on a silicon substrate. That is, in the active region 104, the Al alloy wirings 24, 34, 44 are connected to each other by via contact members 32, 42 made of tungsten embedded in the interlayer insulating films 30, 40. In addition, dummy Al alloy films 52, 54, and 56 are formed in the same layer as the Al alloy wirings 24, 34, and 44, respectively, in the dummy region 108 positioned on the longitudinal direction end side of the semiconductor device 10 with respect to the active region 104. . The dummy Al alloy films 52, 54, and 56 are joined to dummy contact members 53 and 55 embedded in the interlayer insulating films 30 and 40. The lower surface of the dummy Al alloy film 52 is bonded to a dummy contact member 51 embedded in the interlayer insulating film 20. The widths of the dummy Al alloy films 52, 54, and 56 are wider than the widths of the dummy contact members 51, 53, and 55.

When manufacturing an electronic circuit device, the semiconductor device 10 is placed on the wiring substrate 100 after solder is applied to the wiring substrate 100. Then, the semiconductor device 10 is mounted on the wiring substrate 100 by reflowing the applied solder. At this time, heat is applied to the semiconductor device 10. In the semiconductor device 10, the main component of the interlayer insulating film is silicon oxide, so that the thermal expansion coefficient differs between the silicon substrate and the film formed thereon. Therefore, the semiconductor substrate 10 may be warped due to thermal stress during reflow. Further, a force may be applied to the semiconductor device 10 from the wiring board 100 after mounting, and the semiconductor device 10 may be warped.
Even in this case, since the dummy Al alloy films 52, 54, 56 and the dummy contact members 51, 53, 55 are formed in the dummy region 108, the semiconductor device 10 has an increased anchor effect and is located on the inner side in the longitudinal direction from the dummy region 108. The Al alloy wirings 24, 34, 44 and the via contact members 32, 42 are difficult to peel off. Accordingly, poor conduction between the Al alloy wiring and the via contact member is less likely to occur at the longitudinal end portion of the semiconductor device, and the reliability of the semiconductor device and the electronic circuit device using the same increases.

Next, a second embodiment will be described. This embodiment differs from the first embodiment in the configuration of the semiconductor device 10. FIG. 6 is a plan view of an end portion in the longitudinal direction of the semiconductor device 10 according to the second embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
The semiconductor device 10 is formed in an elongated chip. The active region 104 of the semiconductor device 10 includes a contact high-density region 104a in which via contact members are formed at a high density, and a contact low-density region 104b in which the density of the via contact member is lower than that of the contact high-density region 104a. They are formed at positions that overlap each other in the longitudinal direction. In the contact high-density region 104a, a semiconductor element such as a MOS transistor is formed on a silicon substrate. The dummy region 108 is formed only in a region adjacent to the contact low density region 104b.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. Each of FIGS. 7 and 8 is a cross-sectional view corresponding to the AA cross section of FIG.
First, as shown in FIG. 7A, an element isolation film 2 is formed on a wafer-like silicon substrate 1 by a LOCOS method. At this time, the element region opening 2a is formed in the contact high-density region 104a, and the dummy opening 2b is formed in the dummy region 108. Next, the gate insulating film 3 is formed inside the element region opening 2a by, for example, a thermal oxidation method. At this time, the insulating film 3a is formed inside the dummy opening 2b.

  Next, a polysilicon film is formed on the region including the gate insulating film 3 by, for example, a CVD method. A photoresist film (not shown) is applied on the polysilicon film, and the photoresist film is exposed and developed to form a resist pattern. Next, the gate electrode 4 made of a polysilicon film is formed on the gate insulating film 3 by etching the polysilicon film using the resist pattern as a mask. Then, the resist pattern is removed.

  Next, impurity ions are implanted into the silicon substrate 1 using the element isolation film 2 and the gate electrode 4 as a mask, and then a predetermined heat treatment is performed. As a result, the diffusion layer 5 serving as the source / drain of the transistor is formed in the element region opening 2a, and the dummy diffusion layer 57 is formed in the dummy opening 2b.

Next, an interlayer insulating film 20 is formed on the entire surface including the element isolation film 2, the gate insulating film 3, the insulating film 3 a, the gate electrode 4, and the diffusion layer 5. Next, a photoresist film (not shown) is applied on the interlayer insulating film 20, and this photoresist film is exposed and developed to form a resist pattern. Next, by using the resist pattern as a mask, the interlayer insulating film 20 is etched to form a connection hole 20a located on the gate electrode 4, and the interlayer insulating film 20 and the gate insulating film 3 are etched to form on the diffusion layer 5. The connection hole 20b located in the is formed. At this time, the interlayer insulating film 20 and the insulating film 3a are etched to form a dummy connection hole 20c located on the dummy opening 2b.
Next, after removing the resist pattern, a conductive film 8 is formed on the interlayer insulating film 20 in each of the connection holes 20a and 20b and in the dummy connection hole 20c.

  Next, as shown in FIG. 7B, the conductive film 8 located on the interlayer insulating film 20 is removed by polishing by CMP, so that a contact made of a barrier layer and tungsten is formed in the connection holes 20a and 20b. Members 8a and 8b are formed. At this time, a dummy contact member 51 made of a barrier layer and tungsten is formed in the dummy connection hole 20c. Contact member 8 a is connected to gate electrode 4, and contact member 8 b is connected to diffusion layer 5. The dummy contact member 51 has a lower end joined to the silicon substrate 1 in the dummy opening 2b.

  Next, as shown in FIG. 8A, a barrier layer (not shown) in which a Ti film and a TiN film are stacked is formed on the interlayer insulating film 20, the contact members 8a and 8b, and the dummy contact member 51. Thereafter, an Al alloy film is formed on the barrier layer. Next, a photoresist film (not shown) is applied on the Al alloy film, and the photoresist film is exposed and developed to form a resist pattern. Next, the Al alloy film is etched using this resist pattern as a mask. As a result, a plurality of Al alloy wirings 24 are formed in the contact high-density region 104a, and a dummy Al alloy film 52 bonded to the upper end surface of the dummy contact member 51 is formed in the dummy region 108. Some of the Al alloy wirings 24 are connected to the gate electrode 4 by bonding the lower barrier layer to the upper end surface of the contact member 8a, that is, tungsten, and other Al alloy wirings 24 are in contact with the lower barrier layer. The upper end surface of the member 8b, that is, tungsten is connected to the diffusion layer 5.

Next, as shown in FIG. 8B, on the interlayer insulating film 20, the Al alloy wiring 24 and the dummy Al alloy film 52, the interlayer insulating film 30, the via contact member 32, the dummy contact member 53, the Al alloy wiring 34, and The dummy Al alloy film 54, the interlayer insulating film 40, the via contact member 42 and the dummy contact member 55, the Al alloy wiring 44 and the dummy Al alloy film 56, and the passivation film 46 are formed in this order. These forming methods are the same as those in the first embodiment.
Next, although not shown in the drawing, an opening located on the pad 106 is formed in the passivation film 46, and after conducting an electrical characteristic test, the wafer-like silicon substrate is divided into chips by dicing.

  The semiconductor device 10 thus formed has the following structure. That is, interlayer insulating films 20, 30, 40 and a passivation film 46 are formed on the silicon substrate 1. Al alloy wirings 24, 34, and 44 are formed on the interlayer insulating films 20, 30, and 40, respectively. The Al alloy wirings 24, 34 and 44 are connected to each other by via contact members 32 and 42 embedded in the interlayer insulating films 30 and 40. In the contact high-density region 104a of the active region 104, a MOS transistor including the gate insulating film 3, the gate electrode 4, and the diffusion layer 5 is formed on a silicon substrate. The MOS transistor is connected to the Al alloy wiring 24 by contact members 8 a and 8 b embedded in the interlayer insulating film 20. In the contact low density region 104b, the density of the via contact members 32 and 42 is lower than that of the contact high density region 104a.

In addition, dummy Al alloy films 52, 54 and 56 and dummy contact members 51, 53 and 55 are formed in the dummy region 108 adjacent to the contact low density region 104b.
In this embodiment, the same effect as that of the first embodiment can be obtained. Further, in the contact high-density region 104a, the via contact member is formed at a high density, so even if the dummy region 108 is not provided, the Al alloy wiring and the via contact member are not easily separated.

  Next, a third embodiment will be described. This embodiment differs from the second embodiment in the configuration of the semiconductor device 10. In this embodiment, the dummy connection hole, the dummy contact member, and the dummy conductive film are formed adjacent to the MOS transistor. FIG. 9 is a cross-sectional view of the end portion in the longitudinal direction of the semiconductor device 10 according to the third embodiment. The same components as those in the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

Interlayer insulating films 20, 30, 40 and a passivation film 46 are formed in the active region 104 and the dummy region 108 of the semiconductor device 10. Al alloy wirings 24, 34, and 44 are formed on the interlayer insulating films 20, 30, and 40, respectively. The Al alloy wirings 24, 34 and 44 are connected to each other by via contact members 32 and 42 embedded in the interlayer insulating films 30 and 40. In the active region 104, a MOS transistor including the gate insulating film 3, the gate electrode 4 and the diffusion layer 5 is formed on the silicon substrate 1. Each of the gate electrode 4 and the diffusion layer 5 of the MOS transistor is connected to the Al alloy wiring 24 by contact members 8 a and 8 b embedded in the interlayer insulating film 20.
In the dummy region 108, dummy Al alloy films 52, 54, 56 and dummy contact members 51, 53, 55 are formed.
The manufacturing method of the semiconductor device 10 according to the present embodiment is the same as the manufacturing method of the semiconductor device 10 according to the second embodiment, except that the shape of each resist pattern is changed.

  According to this embodiment, the same effect as that of the first embodiment can be obtained. A dummy contact member 51 is formed next to the contact members 8 a and 8 b, and the upper end of the dummy contact member 51 is connected to the dummy Al alloy film 52. For this reason, the contact members 8a and 8b and the Al alloy wiring 24 are not easily separated. Therefore, poor connection is unlikely to occur between the MOS transistor and the Al alloy wiring 24.

  Note that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, instead of the Al alloy wires 24, 34, 44, Cu alloy wires, CoSi wires, and NiSi wires may be formed. When forming a Cu alloy wiring, the wiring is formed by a damascene method.

(A) is a top view of the principal part of the electronic circuit device concerning 1st Embodiment, (b) is a principal part side view of the electronic circuit device shown to (a). FIG. 2 is an enlarged view of a region surrounded by a broken line A in FIG. (A) is sectional drawing which shows the manufacturing process of the semiconductor device 10, (b) is sectional drawing which shows the next process of (a), (c) is sectional drawing which shows the next process of (b). (A) is sectional drawing which shows the next process of FIG.3 (c), (b) is sectional drawing which shows the next process of (a), (c) is sectional drawing which shows the next process of (b). (A) is sectional drawing which shows the next process of FIG.4 (c), (b) is sectional drawing which shows the next process of (a). The top view of the longitudinal direction edge part of the semiconductor device 10 concerning 2nd Embodiment. (A) is sectional drawing which shows the manufacturing process of the semiconductor device 10, (b) is sectional drawing which shows the next process of (a). (A) is sectional drawing which shows the next process of FIG.7 (b), (b) is sectional drawing which shows the next process of (a). The top view of the longitudinal direction edge part of the semiconductor device 10 concerning 3rd Embodiment. Sectional drawing which shows the structure of the chip | tip edge part 200a of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation film, 2a ... Element region opening part, 2b ... Dummy opening part, 3 ... Gate insulating film, 3a ... Insulating film, 4 ... Gate electrode, 5 ... Diffusion layer, 8 ... Tungsten film 8a, 8b ... contact member, 10 ... semiconductor device, 20, 30, 40 ... interlayer insulating film, 20a, 20b, 30a, 40a ... connection hole, 20c, 30b, 40b ... dummy connection hole, 24, 34, 44 ... Al alloy wiring, 32, 42 ... Via contact member, 46 ... Passivation film, 51, 53, 55 ... Dummy contact member, 52, 54, 56 ... Dummy Al alloy film, 57 ... Dummy diffusion layer, 100 ... Wiring substrate, 104 ... active area, 104a ... contact high density area, 104b ... contact low density area, 106 ... pad, 108 ... dummy area, 200a ... chip edge, 201 ... Silicon substrate, 202,210,220 ... interlayer insulating film, 214, 224 ... wire, 222 ... contact members, 224a ... gap, 230 ... passivation film

Claims (15)

A semiconductor device formed on an elongated chip,
An interlayer insulating film formed on the first wiring;
A connection hole formed in the interlayer insulating film and located on the first wiring;
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole and on the end side in the longitudinal direction of the chip from the connection hole;
A via contact member embedded in the connection hole;
A dummy contact member embedded in the dummy connection hole;
A second wiring formed on the via contact member and the interlayer insulating film and connected to the first wiring by the via contact member;
A semiconductor device comprising the dummy contact member and a dummy conductive film formed on the interlayer insulating film. A semiconductor device formed on an elongated chip,
An interlayer insulating film formed on the plurality of first wirings;
A plurality of connection holes formed on the interlayer insulating film and positioned on the plurality of first wirings;
A plurality of via contact members embedded in each of the plurality of connection holes;
A plurality of second wirings formed on the interlayer insulating film and on each of the plurality of via contact members, and connected to the plurality of first wirings by the via contact members;
Comprising
The chip includes
A contact high-density region having a high density of the via contact member;
Formed in a position overlapping the contact high-density region in the longitudinal direction of the chip, a contact low-density region in which the density of the via contact member is lower than the contact high-density region is formed,
further,
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole in the low-density contact region and on the end side in the longitudinal direction of the chip from the connection hole;
A dummy contact member embedded in the dummy connection hole;
A semiconductor device comprising the dummy contact member and a dummy conductive film formed on the interlayer insulating film. The dummy conductive film is formed of the same material as the second wiring,
The semiconductor device according to claim 1, wherein the dummy contact member is formed of the same material as the via contact member. The second wiring and the dummy conductive film have at least one of a titanium film and a titanium nitride film on a lower surface,
4. The semiconductor device according to claim 3, wherein the via contact member and the dummy contact member are formed of tungsten at a connection portion with the second wiring or the dummy conductive film. 5.   The semiconductor device according to claim 1, wherein a length in a longitudinal direction with respect to a width of the chip is eight times or more.   The semiconductor device according to claim 1, wherein the semiconductor device has a silicon substrate, and the interlayer insulating film is a silicon oxide film. A semiconductor device formed on an elongated chip,
A semiconductor element formed on a semiconductor substrate;
An interlayer insulating film formed on the semiconductor element and the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the semiconductor element;
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole and on the end side in the longitudinal direction of the chip;
A contact member embedded in the connection hole and located on the semiconductor element;
A dummy contact member embedded in the dummy connection hole;
A wiring formed on the contact member and the interlayer insulating film, and connected to the semiconductor element by the contact member;
A semiconductor device comprising the dummy contact member and a dummy conductive film formed on the interlayer insulating film. A wiring board;
A semiconductor device mounted on the wiring board;
Comprising
The semiconductor device includes:
Is formed into an elongated tip,
An interlayer insulating film formed on the first wiring;
A connection hole formed in the interlayer insulating film and located on the first wiring;
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole and on the end side in the longitudinal direction of the chip from the connection hole;
A via contact member embedded in the connection hole;
A dummy contact member embedded in the dummy connection hole;
A second wiring formed on the via contact member and the interlayer insulating film and connected to the first wiring by the via contact member;
An electronic circuit device comprising the dummy contact member and a dummy conductive film formed on the interlayer insulating film. A wiring board;
A semiconductor device mounted on the wiring board;
Comprising
The semiconductor device includes:
Is formed into an elongated tip,
A semiconductor element formed on a semiconductor substrate;
An interlayer insulating film formed on the semiconductor element and the semiconductor substrate;
A connection hole formed in the interlayer insulating film and located on the semiconductor element;
A dummy connection hole formed in the interlayer insulating film, located next to the connection hole and on the end side in the longitudinal direction of the chip;
A contact member embedded in the connection hole and located on the semiconductor element;
A dummy contact member embedded in the dummy connection hole;
A wiring formed on the contact member and the interlayer insulating film, and connected to the semiconductor element by the contact member;
An electronic circuit device comprising the dummy contact member and a dummy conductive film formed on the interlayer insulating film.   The electronic circuit device according to claim 8 or 9, wherein the semiconductor device is mounted on the wiring board by reflowing solder applied on the wiring board. Forming a first wiring in each of a plurality of elongated chip regions provided on a wafer-like semiconductor substrate;
Forming an interlayer insulating film on the first wiring;
A connection hole located on the first wiring is formed in the interlayer insulating film, and a dummy connection located next to the first wiring and on the end side in the longitudinal direction of the chip region from the first wiring. Forming a hole in each of the plurality of chip regions;
Embedding a via contact member connected to the first wiring in the connection hole and embedding a dummy contact member in the dummy connection hole;
Forming a second wiring on the interlayer insulating film and the via contact member, and forming a dummy conductive film on the interlayer insulating film and the dummy contact member. Forming a semiconductor element in each of a plurality of elongated chip regions provided on a wafer-like semiconductor substrate;
Forming an interlayer insulating film on the semiconductor element;
A connection hole located on the semiconductor element is formed in the interlayer insulating film, and a dummy connection hole located next to the semiconductor element and on the end side in the longitudinal direction of the chip region from the semiconductor element Forming each chip region;
Embedding a contact member connected to the semiconductor element in the connection hole, and embedding a dummy contact member in the dummy connection hole;
Forming a wiring on the interlayer insulating film and the contact member, and forming a dummy conductive film positioned on the interlayer insulating film and the dummy contact member. The step of embedding the via contact member and the dummy contact member includes:
Forming a conductive film in the connection hole and in the dummy connection hole and on the interlayer insulating film;
The semiconductor device according to claim 11 or 12, which is a step of polishing and removing the conductive film from above the interlayer insulating film by CMP. Forming a first wiring in each of a plurality of elongated chip regions provided on a wafer-like semiconductor substrate;
Forming an interlayer insulating film on the first wiring;
A connection hole located on the first wiring is formed in the interlayer insulating film, and a dummy connection located next to the first wiring and on the end side in the longitudinal direction of the chip region from the first wiring. Forming a hole in each of the plurality of chip regions;
Embedding a via contact member connected to the first wiring in the connection hole and embedding a dummy contact member in the dummy connection hole;
Forming a second wiring on the interlayer insulating film and the via contact member, and forming a dummy conductive film on the interlayer insulating film and the dummy contact member; A method for manufacturing an electronic circuit device, comprising:
A method of manufacturing an electronic circuit device comprising a step of mounting the semiconductor device on a wiring board. Forming a semiconductor element in each of a plurality of elongated chip regions provided on a wafer-like semiconductor substrate;
Forming an interlayer insulating film on the semiconductor element;
A connection hole located on the semiconductor element is formed in the interlayer insulating film, and a dummy connection hole located next to the semiconductor element and on the end side in the longitudinal direction of the chip region from the semiconductor element Forming each chip region;
Embedding a contact member connected to the semiconductor element in the connection hole, and embedding a dummy contact member in the dummy connection hole;
Forming a wiring on the interlayer insulating film and the contact member, and forming a dummy conductive film positioned on the interlayer insulating film and the dummy contact member; A device manufacturing method comprising:
A method of manufacturing an electronic circuit device comprising a step of mounting the semiconductor device on a wiring board.

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