JP2006339232A - Circuit board and its manufacturing method, and semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board and its manufacturing method which secure connection reliability with a mounted circuit element, as well as cope with the reduction in parasitic capacitance and noise. <P>SOLUTION: A circuit board 10 comprises a semiconductor substrate 11, penetration electrode 13 formed by penetrating the semiconductor substrate 11 in a thickness direction, and a connection electrode 16 which extends the semiconductor substrate 11 to the middle in a thickness direction, and is electrically connected with the semiconductor substrate 11. Furthermore, a first electric conductive pattern 14 and a second electric conductive pattern 15 are formed in the upper surface and the rear surface of the semiconductor substrate 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a circuit board and a manufacturing method thereof, and more particularly to a circuit board on which circuit elements are mounted and used as an interposer and a manufacturing method thereof. Furthermore, the present invention relates to a semiconductor device employing such a circuit board and a method for manufacturing the same.

  Conventionally, a circuit device has been formed by mounting a semiconductor element such as an IC chip on a mounting substrate having a conductive path formed on the surface thereof, for example. As a structure for connecting a conductive path on a mounting substrate and a semiconductor element, there are two mounting structures of face-up and face-down (flip chip method).

  When the semiconductor element is mounted on the mounting board face up, the back surface of the semiconductor element is fixed to the mounting board. The pad formed on the upper surface of the semiconductor element and the conductive path of the mounting substrate are wire bonded by a thin metal wire. However, in the connection method using wire bonding, it is necessary to secure a region for forming a fine metal wire in the peripheral portion of the semiconductor element, and thus there is a problem that an area required for mounting the semiconductor element increases.

  When the semiconductor element is mounted on the mounting substrate face down, the pad electrode of the semiconductor element arranged on the lower surface and the conductive path on the mounting substrate are connected using solder bumps or the like. By mounting the semiconductor element face down, the area required for mounting can be made equal to the size of the element. However, since the thermal expansion coefficient is different between the mounting substrate and the semiconductor element, thermal stress acts on the solder bump that joins the two together with the temperature change. This thermal stress causes cracks in the solder bumps, resulting in a problem that the connection reliability of the semiconductor element is lowered.

  In order to solve this problem, a structure for connecting a semiconductor element and a mounting substrate via an interposer having a linear expansion coefficient equivalent to that of a chip has been proposed.

  A semiconductor element connection structure using a circuit board as an interposer will be described with reference to a cross-sectional view of FIG. Here, the semiconductor element 101 which is an LSI chip having a large number of pads is mounted on the mounting substrate 104 via the circuit substrate 100. The pad located on the back surface of the semiconductor element 101 and the circuit board 100 are connected by a connection electrode 102. Further, the conductive path 105 formed on the upper surface of the mounting substrate 104 and the circuit board 100 are connected by the external electrode 103. Furthermore, conductive patterns 106 insulated by an insulating layer 107 are formed on the upper surface and the back surface of the circuit board 100.

When a material having a thermal expansion coefficient closer to that of the semiconductor element 101 than that of the mounting substrate 104 is employed as the material of the circuit board 100 that is an interposer, the thermal stress employed in the connection electrode 102 is reduced. Therefore, the connection reliability with respect to the thermal stress of the connection electrode 102 can be improved. As a specific material of the circuit board 100, resin, metal, ceramic, or the like is employed. Patent Document 1 discloses a technique that employs a semiconductor such as silicon as a material for the circuit board 100.
JP 2001-326305 A

  However, in the above-described structure using the circuit board 100, a parasitic capacitance or a voltage drop occurs between the conductive pattern 106 and the circuit board 100, and the malfunction of the semiconductor element 101 may occur due to the ground becoming unstable. was there. Specifically, the circuit board 100 is in a floating state, and the potential is not fixed. Therefore, a potential difference is easily generated between the conductive pattern 106 and the circuit board 100, and a parasitic capacitance is generated between the two. In particular, when the semiconductor element 101 is an element that operates at a high frequency of about several GHz, there arises a problem that the performance of the element deteriorates due to parasitic capacitance generated in the circuit board 100.

  Further, since the circuit board 100 does not take measures against noise, there is a problem that noise transmitted through the circuit board 100 enters the semiconductor element 101 and causes the semiconductor element 101 to malfunction. In particular, when an analog circuit sensitive to noise is formed in the semiconductor element 101, the semiconductor element 101 may malfunction due to noise entering from the outside. Further, there is a problem that noise generated from the semiconductor element 101 is transmitted to the outside through the circuit board 100 and adversely affects other circuit elements. Such a problem also occurs remarkably when the semiconductor element 101 is a high-frequency device.

  The present invention has been made in view of the above-mentioned problems, and the main object of the present invention is to ensure connection reliability with mounted circuit elements, and further to reduce parasitic capacitance and suppress voltage effects due to wiring. An object of the present invention is to provide a circuit board and a method for manufacturing the same, a semiconductor device, and a method for manufacturing the same.

  The circuit board of the present invention includes a semiconductor substrate, a through electrode provided so as to penetrate the semiconductor substrate in the thickness direction, the semiconductor substrate extending partway in the thickness direction, and electrically connected to the semiconductor substrate. And a connection electrode.

  Furthermore, the present invention provides a through electrode embedded in a through hole penetrating a semiconductor substrate, and a connection electrode embedded in a connection hole extending partway through the semiconductor substrate in the thickness direction and electrically connected to the semiconductor substrate. The through hole and the connection hole are formed by etching performed from one main surface of the semiconductor substrate.

  Furthermore, the method for manufacturing a circuit board according to the present invention includes a step of preparing a semiconductor substrate, and an etching mask having a first opening and a second opening smaller than the first opening. A step of covering one main surface; and etching the semiconductor substrate from one main surface through the etching mask to form a through-hole penetrating the semiconductor substrate from the first opening; Forming a connection hole extending partway through the semiconductor substrate in the thickness direction from the second opening, and forming a through electrode by forming a conductive material inside the through hole; And forming a connection electrode electrically connected to the semiconductor substrate by forming a conductive material on the semiconductor substrate.

  Furthermore, the present invention provides a through-electrode embedded in a through-hole penetrating a semiconductor substrate, and a connection electrically connected to the semiconductor substrate embedded in a connection hole extending partway through the semiconductor substrate in the thickness direction. In the method of manufacturing a circuit device including an electrode, the through hole is formed by etching performed from both main surfaces of the semiconductor substrate.

  Furthermore, in the method for manufacturing a circuit board according to the present invention, a step of preparing a semiconductor substrate, one main surface of the semiconductor substrate is covered with a first etching mask provided with a first opening, and the semiconductor substrate Covering the other main surface with a second etching mask provided with a second opening, and etching the semiconductor from both main surfaces to thereby provide the first opening and the second opening. Etching is performed from both of the portions to form a through-hole penetrating the semiconductor substrate, and the semiconductor substrate is extended partway in the thickness direction by etching proceeding from the first opening or the second opening. Forming an existing connection hole; forming a through electrode by forming a conductive material inside the through hole; and forming a conductive material inside the connection hole; Characterized by comprising the step of forming the connected connection electrode.

  The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a semiconductor substrate is prepared and etched through a plurality of etching regions having different sizes to form a plurality of holes, resulting from the size of the etching region. Due to the difference in etching speed, the first hole penetrates the semiconductor substrate and the second hole does not penetrate.

  A semiconductor device according to the present invention includes a semiconductor mounting substrate made of substantially the same material as a substrate of a semiconductor element, a front electrode and a back electrode provided through a through electrode penetrating the semiconductor mounting substrate, and an electrical connection to the front electrode. And the semiconductor element provided on the semiconductor mounting substrate.

  According to the circuit board and the semiconductor device of the present invention, the semiconductor substrate and the conductive pattern formed on the surface thereof can be set to the same potential by the connection electrode provided through the semiconductor substrate halfway in the thickness direction. Accordingly, parasitic capacitance generated between the semiconductor substrate and the conductive pattern can be reduced. The ground impedance can be reduced by grounding using the entire semiconductor surface. In addition, by using the ground circuit as a semiconductor substrate, the wiring density of the conductive path can be suppressed, and the delay associated with signal propagation can be suppressed. For example, when the semiconductor substrate is fixed to the ground potential via the connection electrode, it is possible to prevent parasitic capacitance from being generated between the conductive pattern connected to the ground potential and the semiconductor substrate. Furthermore, since the semiconductor substrate can be connected to the ground potential or the like via the connection electrode, the shielding effect of the circuit board can be improved. Therefore, it is possible to block external noise and stabilize the operation of the circuit element mounted on the circuit board. The grounding stability can stabilize the electric operation and improve the reliability of the high-speed operation. In addition, the suppression of the wiring density can secure an area necessary for timing adjustment such as equal-length wiring, and an electric circuit with higher reliability can be realized.

  According to the manufacturing method of the present invention, the connection hole and the through hole in which the connection electrode and the through electrode are formed can be formed by etching performed from one main surface of the substrate. Specifically, by etching the semiconductor substrate using an etching mask provided with a first opening and a second opening having different planar sizes, a through hole and a connection hole are simultaneously formed in the semiconductor substrate. It is formed. A through hole penetrating the semiconductor substrate is formed at a location corresponding to the first opening. A connection hole is formed at a location corresponding to the second opening that is smaller in plan than the first opening, extending partway through the semiconductor substrate in the thickness direction.

  Furthermore, according to the manufacturing method of the present invention, it is possible to simultaneously form the connection hole and the through hole by performing etching from both main surfaces of the substrate. Specifically, one main surface of the substrate is covered with a first etching mask provided with a first opening, and the other main surface of the substrate is covered with a second etching mask provided with a second opening. . Through-holes that penetrate the substrate are formed by etching that proceeds from both the first opening and the second opening. Further, the connection hole is formed by etching that proceeds from either the first opening or the second opening.

<First Embodiment>
In this embodiment, a structure of a circuit board and a semiconductor device will be described with reference to FIGS.

  With reference to FIG. 1, the structure of the circuit board 10 which is an interposer is demonstrated. 1A is a cross-sectional view of the circuit board 10, FIG. 1B is an enlarged cross-sectional view of a region where the connection electrode 16 is provided, and FIG. 1C is a region where the through electrode 13 is provided. FIG.

  Referring to FIG. 1A, a circuit board 10 of this embodiment includes a semiconductor substrate 11, a through electrode 13 formed through the semiconductor substrate 11 in the thickness direction, and the semiconductor substrate 11 halfway in the thickness direction. A connection electrode 16 extending and electrically connected to the semiconductor substrate 11 is provided. Further, a first conductive pattern 14 and a second conductive pattern 15 are formed on the upper surface and the back surface of the semiconductor substrate 11. In this embodiment, the circuit board 10 is used as an interposer. An interposer is a substrate that is located between a circuit element such as a semiconductor element and a mounting substrate and is used to configure a circuit device or the like.

  The semiconductor substrate (semiconductor mounting substrate) 11 is made of a semiconductor such as silicon. The thickness of the semiconductor substrate 11 is, for example, about 100 μm to 200 μm. As a material of the semiconductor substrate 11, an intrinsic semiconductor or an impurity semiconductor can be employed. In particular, when a semiconductor substrate diffused with P-type or N-type impurities is employed, the electrical conductivity and thermal conductivity of the substrate are increased, and the function of the metal substrate is approached. That is, the semiconductor substrate 11 can be provided with various functions such as a shield function and a heat dissipation function. Further, when the ground wiring is provided, the ground wiring and the substrate can be set to the same potential, and it is possible to eliminate the parasitic capacitance of the ground wiring. As the impurity semiconductor, a P-type semiconductor into which a P-type impurity such as boron is introduced, or an N-type semiconductor into which an N-type impurity such as phosphorus is introduced is employed. By using the impurity semiconductor as the material of the semiconductor substrate 11, the electrical resistance of the semiconductor substrate 11 is lowered and current flows easily, so that the connection electrode 16 and the semiconductor substrate 11 can be easily conducted.

  Further, the semiconductor substrate 11 made of silicon is made of the same material as the semiconductor element such as an LSI chip. Therefore, since the thermal expansion coefficient of the semiconductor element to be mounted is equal to the thermal expansion coefficient of the circuit board 10, the connection reliability between them can be improved. For example, a semiconductor chip can be mounted face-up or face-down. In the case of face-up, since connection is performed using connection means such as a fine metal wire or a lead plate, the reliability of the connection portion between the connection means and the semiconductor element is improved. For example, when considering the case where a semiconductor element is mounted on the upper surface of the circuit board 10 using a bump electrode by using a bump electrode, the thermal stress acting on the bump electrode connecting the two becomes extremely small, and the connection reliability is improved.

  The insulating film 12 is made of a resin film such as a silicon oxide film, a silicon nitride film, or polyimide, and covers the upper surface and the back surface of the semiconductor substrate 11. The insulating film 12 insulates the first conductive pattern 14 and the second conductive pattern 15 from the semiconductor substrate 11. The side surface of the through hole 32 is also covered with the insulating film 12. Furthermore, the side surfaces of the connection holes 27 and 32 are covered with the insulating film 12, and the bottom surface is not covered with the insulating film 12 because the semiconductor substrate is exposed.

  The first conductive pattern (front electrode) 14 and the second conductive pattern (back electrode) 15 are formed on the upper surface and the back surface of the semiconductor substrate 11. These conductive patterns are made of a metal whose main material is copper. Moreover, you may comprise these conductive patterns with other metal materials, such as Al and Au. The first conductive pattern 14 is formed on the upper surface of the semiconductor substrate 11 and forms a pad (for example, a die pad or a bonding pad) to which a semiconductor element or the like is connected, a wiring for connecting the pads, or the like. The second conductive pattern 15 extends from the outside of the semiconductor formation region to the back surface of the semiconductor substrate 11 to form pads used for connection to a mounting substrate, wirings connecting these pads, and the like. Yes. Since a two-layer conductive pattern is formed, crossover is also possible.

  Here, the first conductive pattern 14 and the second conductive pattern 15 of a single layer are formed, but it is also possible to form these conductive patterns in multiple layers.

  The through electrode 13 is made of a conductive material provided in a through hole 23 provided through the semiconductor substrate 11 in the thickness direction. The first conductive pattern 14 and the second conductive pattern 14 are connected by the through electrode 13. The through electrode 13 and the semiconductor substrate 11 are insulated by an insulating film 12 provided on the inner wall of the through hole 23. The through electrode 13 can be formed of, for example, a metal film that is formed by a plating method described later and is electrically connected to the first conductive pattern 14 and the second conductive pattern 15. Here, the through electrode 13 made of a metal film with a thickness of about several μm is formed on the inner wall of the through hole 23 with a width (W1) of about 40 μm. Further, the through electrode 13 may be made of a conductive material embedded in the through electrode 13.

  The connection electrode 16 is made of a conductive material embedded in a connection hole 32 extending partway from the upper surface of the semiconductor substrate 11 in the thickness direction. The lowermost part of the connection electrode 16 is in ohmic contact with the semiconductor substrate 11 exposed at the bottom surface of the connection hole 23, whereby the connection electrode 16 and the semiconductor substrate 11 are electrically connected. The first conductive pattern 14 and the semiconductor substrate 11 are electrically connected via the connection electrode 16. The width W2 of the connection electrode 16 is preferably equal to or less than that of the through electrode 13, and is set to, for example, about 40 μm to 10 μm. The depth of the connection electrode 16 may be as long as it does not penetrate the semiconductor substrate 11 and is, for example, about 100 μm. The connection electrode 16 can be formed of a metal film that is formed integrally with the first conductive pattern 14. Further, a conductive material is embedded in the connection hole 32 to form the connection electrode 16. For example, a structure in which a thin film is deposited on the side wall as in the through hole 23 in FIG. As shown in FIG. 1B, the connection electrode 16 may be a type in which the connection hole 32 is completely embedded, or a type made of a metal film provided on the side wall of the connection hole 32.

  Further, referring to FIG. 1B, the connection electrode 16 is connected to the semiconductor substrate 11 through the barrier film 35. By forming the barrier film 35, it is possible to prevent copper (Cu), which is the material of the connection electrode 16, from diffusing into the semiconductor substrate 11 made of silicon. As the material of the barrier layer 35, a refractory metal such as titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum nitride (TaN), or a compound containing a refractory metal is employed.

  The connection electrode 17 extends from the back surface to the middle of the thickness direction from the back surface and is electrically connected to the semiconductor substrate 11. The semiconductor substrate 11 and the second conductive pattern are electrically connected via the connection electrode 17. The structure of the connection electrode 17 formed inside the connection hole 27 is the same as that of the connection electrode 16 described above.

  Here, the two connection electrodes 16 and 17 are formed from both main surfaces of the semiconductor substrate 11, but the connection electrodes may be formed only from one of the main surfaces. That is, only the connection electrode 16 may be formed from the upper surface of the semiconductor substrate 11, or only the connection electrode 17 may be formed from the back surface of the semiconductor substrate 11.

  The structure of the connection electrode 16 is constituted by a process described later, but may be a structure such as a contact employed in a normal semiconductor process. That is, the connection electrode 16 </ b> A may be formed in the connection hole 32 having a depth enough to remove only the insulating film 12.

  With reference to FIG. 1C, the structure of the through electrode 13 will be further described. Here, a recess 24 is formed in the inner wall near the lower end of the through hole 23 from the inner wall toward the inside of the semiconductor substrate 11. This structure is formed by over-etching the inner wall of the through hole 23 in FIG. 6 shown later. The through hole 23 in the portion where the recess 24 is provided is wider than the other portion. By forming the through electrode 13 inside the through hole 23 so as to fill the recess 24, an anchor effect is generated between the through electrode 13 and the inside of the through hole 23, and the through electrode 13 is formed on the semiconductor substrate. 11 is difficult to peel off.

  In this embodiment, the parasitic capacitance generated between the first conductive pattern 14 and the semiconductor substrate 11 is reduced by electrically connecting the first conductive pattern 14 and the semiconductor substrate 11 via the connection electrode 16. Can be made. Specifically, the first conductive pattern 14 is formed on the upper surface of the semiconductor substrate 11 with the insulating film 12 interposed therebetween. In other words, the insulating film 12 as a dielectric is located between the first conductive pattern 14 and the semiconductor substrate 11. Accordingly, when the potentials of the conductive pattern 14 and the semiconductor substrate 11 are different, parasitic capacitance corresponding to the potential difference is generated. Therefore, in this embodiment, the semiconductor substrate 11 and the conductive pattern 14 are electrically connected to make the potentials of both equal to suppress the generation of parasitic capacitance. By reducing the parasitic capacitance, malfunction of the circuit element mounted on the circuit board 10 can be prevented. The same applies to the semiconductor substrate 11 and the second conductive pattern 15 connected via the connection electrode 17.

  Furthermore, the semiconductor substrate 11 is preferably fixed to the ground potential via the connection electrode 17. As a result, the parasitic capacitance generated between the first conductive pattern (GND line) 14 connected to the ground potential and the semiconductor substrate 11 is eliminated. Furthermore, when the semiconductor substrate 11 is connected to the ground potential, the potential of the semiconductor substrate 11 can always be fixed to the same potential (0 V), so that the potential of the semiconductor substrate 11 can be prevented from fluctuating. Further, a power supply potential (Vcc) may be employed instead of the ground potential.

  Further, when an external GND is connected to the semiconductor substrate 11, the conductive pattern connected to the semiconductor substrate 11 can stably maintain the GND potential. Furthermore, since the grouped region of the semiconductor substrate 11 can be set to the ground potential, the shielding effect is improved and the propagation of noise transmitted through the circuit substrate 11 is prevented. In particular, if the entire semiconductor substrate 11 is dropped to GND, it is effective in absorbing and blocking noise.

  With reference to FIG. 2A, a module (semiconductor device) in which the circuit board of this embodiment is used as an interposer will be described. Here, the circuit device 20 is configured by mounting the circuit element 18 on the upper surface of the circuit board 10. The back surface of the circuit board 11 is fixed to a conductive path 31 formed on the top surface of the mounting substrate 30 via the external electrode 21.

  The first conductive pattern 14 and the second conductive pattern 15 formed on the top surface and the back surface of the circuit board 10 are covered with a coating layer 22 except for the electrically connected region. On the upper surface of the circuit board 10, the first conductive pattern 14 in a region connected to the circuit element 18 is exposed from the coating layer 22. On the back surface of the circuit board 10, the second conductive pattern 15 where the external electrode 21 is attached is exposed from the coating layer 22.

  The circuit element 18 is an element mounted on the circuit board 10 and can generally employ passive elements such as resistors, capacitors, and / or coils, and active elements such as diodes, transistors, ICs, and LSIs. Further, a plurality of circuit elements 18 may be mounted on the circuit board 10 to realize the system function with one circuit device 20A. Sensors such as an optical sensor, a pressure sensor, and a magnetic sensor may be mounted.

  The semiconductor element 18B is connected via a bump electrode 19 to the first conductive pattern 14 formed on the upper surface of the circuit board 10 by a flip chip method. As described above, the semiconductor substrate 11 which is the base material of the circuit board 10 is made of silicon in the same manner as the material of the semiconductor element. Therefore, since the thermal expansion coefficients of the circuit board 10 and the semiconductor element 18B are equal, the thermal stress acting on the bump electrode 19 that connects them is extremely small, and the connection reliability is improved. In addition, an underfill 36 may be filled between the semiconductor element 18B and the circuit board 10 in order to further improve the connection reliability between them.

  In this embodiment, it is possible to operate on the upper surface of the circuit board 10 without degrading the characteristics of the semiconductor element 18B operating at a high frequency. A semiconductor element that operates at a high frequency (for example, several GHz) is likely to be adversely affected by parasitic capacitance, and there is a risk of signal delay or deterioration due to the parasitic capacitance. In this embodiment, with the above-described configuration, it is possible to cope with a high-frequency semiconductor element by reducing the parasitic capacitance generated in the circuit board. Further, in such a conductive path (micro strip line), dielectric loss can be prevented by matching with a general characteristic impedance at high speed transmission.

  Furthermore, by using an insulating material positioned between the semiconductor element 18B and the circuit board 10 as a low dielectric material, it is possible to reduce the parasitic capacitance generated between the semiconductor element 18B and the circuit board 10. . Here, the covering layer 22 and the underfill 36 positioned between them are made of black diamond or fluorinated polyimide, which is a low dielectric material, thereby reducing parasitic capacitance and matching characteristic impedance. Yes.

  Further, the GND line of the mounting substrate fixes the semiconductor substrate 11 to a stable GND potential via the connection electrode 16, or the GND from the outside is directly connected to the semiconductor substrate 11 to stabilize the semiconductor substrate 11. The potential can be fixed.

  Further, unnecessary radiation generated from the wiring of the mounting substrate 30 or the like or unnecessary radiation generated from the semiconductor element 18 can be blocked by the semiconductor substrate 11. For example, the semiconductor element 18B provided with an analog circuit sensitive to noise can also realize a stable operation.

  With reference to FIG. 2 (B), the structure of the circuit device 20B of another form is demonstrated. In the circuit device 20B, the semiconductor element 18B is mounted on the upper surface of the circuit board 10 in a face-up state. A sealing resin 37 is formed on the upper surface of the circuit board 10 so that the semiconductor element 18B is sealed. Thus, even when the semiconductor element 18B is mounted face-up, the above-described effects can be obtained.

  The back surface of the semiconductor element 18 </ b> B is fixed to the upper surface of the circuit board 10 via the bonding material 26. The electrode formed on the upper surface of the semiconductor element 18 </ b> B is connected to the first conductive pattern 14 through the fine metal wire 25.

  As the bonding material 26 used for fixing the semiconductor element 18B, a low dielectric material is preferable as described above. Thereby, the parasitic capacitance generated between the semiconductor element 18B and the first conductive pattern 14 located therebelow can be reduced.

  Here, in FIG. 2A, as the mounting substrate 30, a glass epoxy substrate, a ceramic substrate, a glass substrate, a metal substrate, a flexible substrate, or the like can be considered. However, considering that the semiconductor substrate 11 and the semiconductor element 18B are made of Si and the composition ratio of Si is high, the mounting substrate 30 is preferably a flexible substrate. Further, this figure shows a module in which circuit elements are mounted on the semiconductor substrate 11, but it may be sealed with resin as shown in FIG.

  Furthermore, a stack structure in which a memory chip is employed as the semiconductor element 18 and a plurality of chips are stacked on the upper layer in consideration of expansion of the memory capacity may be employed. At this time, if the memory chip is stacked by using a through electrode extending from the front surface of the chip to the back surface of the chip, a compact and highly reliable module can be realized. The above points are the same as in FIG.

<Second Embodiment>
In this embodiment, with reference to FIGS. 3 and 4, a method of manufacturing a circuit board in which the connection hole 32 and the through hole 23 are simultaneously formed by etching only from one main surface of the semiconductor substrate 11 will be described. To do.

  Referring to FIG. 3A, first, a semiconductor substrate 11 is prepared, and the upper surface of the semiconductor substrate 11 is covered with an etching mask 40 provided with an opening (etching region).

  The semiconductor substrate 11 is a substrate made of a semiconductor such as silicon and having a thickness of about 100 μm to 400 μm. As described above, the semiconductor substrate 11 may be one in which impurities are diffused in the substrate.

  The etching mask 40 generally employs a photoresist, but a silicon oxide film or a silicon nitride film can be employed. When reactive ion etching (RIE) is performed as a later etching method, a silicon oxide film or a resist excellent in etching resistance is preferable. Here, the outer peripheral surface of the semiconductor device 11 may be covered with an oxide film in advance.

  From the first opening 41, a region where the through hole 23 is formed is exposed. The planar shape of the first opening 41 is, for example, a circle or a rectangle, and its width W1 is, for example, about 40 μm.

  A region where the connection hole 27 is formed is exposed from the second opening 42. The width W2 of the second opening 42 is narrower than that of the first opening W1, and is, for example, about 10 μm to 20 μm.

With reference to FIG. 3B and FIG. 3C, next, the through hole 23 and the connection hole 27 are formed by etching the semiconductor substrate 11 through the etching mask 40. As etching performed in this step, dry etching such as plasma etching, sputter etching, RIE, or ECR is employed. For these dry etching, an etching gas containing SF ₆ , O ₂ , C ₄ F _{8 and the} like is used. Here, etching proceeds downward from the upper surface of the semiconductor substrate 11. Further, the through hole 23 and the connection hole 27 may be formed by wet etching.

  FIG. 3B shows a cross section of the semiconductor substrate 11 in the middle of etching. As described above, the width of the second opening 42 is about ¼ of the first opening 41. That is, the etching speed differs depending on the size, the narrow opening 42 is shallow, and the wide opening 41 is deep.

  Referring to FIG. 3C, the semiconductor substrate 11 is etched through the etching mask 40 until the through hole 23 penetrating the semiconductor substrate 11 in the thickness direction is formed. As described above, at this stage, since the etching rate of the second opening 42 is low, the connection hole 27 does not reach the lower surface of the semiconductor substrate 11. That is, the connection hole 27 extends partway in the thickness direction of the semiconductor substrate 11.

  This step is a point of the present invention. First, the connection electrode for fixing the semiconductor substrate to a predetermined potential can be formed by stopping the connection hole 27 in the middle of the substrate. Further, by making the first opening 41 and the second opening 42 different in size, the etching rate in the depth direction is different, and the through hole 23 and the connection hole 27 are formed by one etching. be able to. Therefore, since it is not necessary to form the through hole 23 and the connection hole 27 in separate steps, the manufacturing cost can be reduced.

  Referring to FIG. 4A, after removing the etching mask 40, the insulating film 12 made of a silicon oxide film or a silicon nitride film is formed on the surface of the semiconductor substrate 11 including the inner walls of the through hole 23 and the connection hole 27. Form.

  Referring to FIG. 4B, next, by removing the insulating film 12 covering the bottom of the connection hole 27, the exposed portion 28 where the semiconductor substrate 11 is exposed inside the connection hole 27 is formed. For etching the insulating film 12 covering the bottom of the connection hole 27, anisotropic etching is preferable. That is, since the bottom part is etched rather than the side wall of the connection hole 27, only the bottom part can be exposed. Depending on the etching method, the insulating film 12 on the surface may be left and the insulating film 12 covering the bottom and side walls of the connection hole 27 may be removed. In this way, the contact resistance of the subsequent connection electrode can be greatly reduced.

  In the case of using an etching mask, the insulating film 12 formed on the main surface of the semiconductor substrate 11 is covered with an etching mask (not shown), and then anisotropic dry etching is performed, so that it is positioned at the bottom of the connection hole 27. The insulating film 12 to be removed is removed.

  When an etching mask is not used, the following method is preferable. That is, although the thickness of the insulating film 12 is shown uniformly in the drawing, the insulating film 12 formed inside the connection hole 27 is actually thinner than the insulating film 12 formed on the upper surface of the semiconductor substrate 11. For example, the thickness of the insulating film 12 covering the bottom of the connection hole 27 is about half that of the insulating film 12 formed on the upper surface of the semiconductor substrate 11. Accordingly, when dry etching is performed uniformly from the upper surface of the semiconductor substrate 11 without using an etching mask, the insulating film 12 at the bottom of the connection hole 27 is removed before the insulating film 12 formed on the upper surface of the semiconductor substrate 11 is removed. Can be removed.

  Referring to FIG. 4C, a metal film 29 made of, for example, copper (Cu) is formed so as to cover the inside of the through hole 23 and the connection hole 27 and the upper surface and the back surface of the semiconductor substrate 11.

  Specifically, first, a barrier layer is formed on the inner walls of the through holes 23 and the connection holes 27 and on the upper surface and the back surface of the semiconductor substrate 11 in order to prevent the diffusion of copper (Cu). This barrier layer is made of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum nitride (TaN), or the like, and is formed by sputtering or CVD. Further, a seed layer made of a metal film having a thickness of about several hundreds of nanometers is formed on the upper surface of the barrier layer by sputtering or CVD, and electrolytic plating is performed by using this seed layer as an electrode. A metal film 29 having a thickness of about several μm is formed.

  Here, although the connection hole 27 is embedded with a metal film, it may be formed in a thin film state on the side wall of the connection hole 27 as shown in the through hole 13 of FIG. That is, the inner wall of the connection hole 27 may be covered with a metal film to form a cavity inside. The through hole 23 may be filled with the metal film 29 by performing a filling plating method. In the state where the cavity is formed inside, since there is a Cu film on the surface, a conductive material (solder, W or Al) different from the metal film 29 made of Cu is embedded in the connection hole 27 and the through hole 23. But it ’s okay.

  4D, next, the first conductive pattern 14 and the second conductive pattern 15 are formed by patterning the metal film 29 formed on the top surface and the back surface of the semiconductor substrate 11 by etching or the like. Form. Further, the first conductive pattern 14 and the second conductive pattern 15 are covered with a coating resin except for the electrical connection portion. A circuit board that can be used as an interposer is formed by the above steps.

  Here, the conductive pattern is composed of one layer, but thereafter, the formation of the insulating film, the formation of the conductive material, and the patterning may be repeated several times to form a plurality of stacked conductive patterns.

<Third Embodiment>
In this embodiment, a method for manufacturing a circuit board according to another embodiment will be described with reference to FIG. Specifically, a method of manufacturing a circuit board having a connection electrode 16 extending from the upper surface of the semiconductor substrate 11 to the inside and a connection electrode 17 extending from the lower surface to the inside will be described. That is, a method for manufacturing the circuit device 10 having the structure shown in FIG. Here, since the basic manufacturing method is the same as that of the second embodiment described above, the description will focus on the differences.

  With reference to FIG. 5A, first, a through hole 23 and a connection hole 27 are formed from one main surface of the semiconductor substrate 11. Since this is the same as that of the second embodiment, particularly the method of FIGS.

  Next, referring to FIG. 5B, connection holes 32 are formed from the other main surface of the semiconductor substrate 11. Here, the front and back of the semiconductor substrate 11 are reversed, and the connection hole 27 formed in the above process is located on the lower surface of the semiconductor substrate 11. The lower surface of the semiconductor substrate 11 is bonded to a support substrate 44 made of glass or the like via an adhesive 43 made of epoxy resin or the like.

  Further, the upper surface of the semiconductor substrate 11 is covered with an etching mask 34 having an opening 33. Here, the through hole 23 is also covered with the etching mask 34 and is protected from the etching in this step. The width of the opening 33 formed in the etching mask 34 is about 10 μm, similar to the second opening 42 described above.

  By etching the semiconductor substrate 11 through the etching mask 34, the etching proceeds from the opening 33, and the connection hole 32 is formed. The depth of the through hole 32 is set so as not to penetrate the semiconductor substrate 11. In this step, dry etching similar to the etching performed when forming the through hole 23 is employed. After this step is completed, the semiconductor substrate 11 is separated from the support substrate 44.

  Referring to FIG. 5C, next, an insulating film 12 made of a silicon oxide film or a silicon nitride film is formed on the surface of the semiconductor substrate 11. Specifically, the upper surface and the back surface of the semiconductor substrate 11 are covered with the insulating film 12, and the inner walls of the connection holes 27, the connection holes 32, and the through holes 23 are also covered with the insulating film 12.

  In general, when the insulating film 12 is formed, a film such as a CVD method is generally used. In this case, since the wafer to be the semiconductor substrate 11 is placed on the wafer table in the chamber, no film is deposited on the back surface. Therefore, in this case, two film forming steps are required for the front and back sides. If films are formed under substantially the same conditions, the films formed on the side walls of the connection holes 27 and 32 have substantially the same film thickness, and the film thicknesses of the front and back insulating films 12 are also substantially the same. However, the side wall of the through-hole 23 is formed to be thicker than the connection holes 27 and 28 because the film is formed twice.

  4B, the insulating film 12 covering the bottoms of the connection hole 27 and the connection hole 32 is removed by etching. Therefore, the semiconductor substrate 11 is exposed at the bottoms of the connection hole 27 and the connection hole 32.

  Subsequently, as shown in FIG. 5D, a barrier layer and a metal film are formed so as to cover the inside of the through hole 23 and the connection holes 27 and 32 and the upper surface and the back surface of the semiconductor substrate 11. This specific method is the same as in the case of FIG.

  Again, as described above, when the barrier film is formed on the wafer table in the chamber, the barrier film formed in the through hole 23 is thicker than the barrier film formed in the connection holes 27 and 32. It is formed.

  Further, when the metal film is formed by plating, it can be formed with substantially the same film thickness because it is immersed in the plating solution. Then, the first conductive pattern 14 and the second conductive pattern 15 are formed on the upper surface and the rear surface of the semiconductor substrate 11 by patterning the metal film and the barrier film. In this step, the conductive film is also formed inside the connection hole 27, the connection hole 32, and the through hole 23, and the connection electrode 17, the connection electrode 16, and the through electrode 13 are formed.

<Fourth embodiment>
In the present embodiment, a method for manufacturing a circuit board having a through electrode 13 that is partially formed wide will be described with reference to FIG.

  Referring to FIG. 6A, first, the semiconductor substrate 11 is etched to form a through hole 23 having a wide width at one end or in the vicinity thereof and a substantially straight connection hole 27. .

  In this step, the upper surface of the semiconductor substrate 11 is covered with an etching mask 40 in which the first opening 41 and the second opening 42 are formed. A support substrate 44 is bonded to the lower surface of the semiconductor substrate 11 with an adhesive 43. When the semiconductor substrate 11 is etched through the etching mask 40 in this state, the etching proceeds through the first opening 41 and the second opening 42. If the over-etching is further performed after the through-hole 23 penetrating the semiconductor substrate 11 reaches the adhesive by this etching, the adhesive becomes an etching mask, and the etching proceeds in the lateral direction, and the lower end of the through-hole 23 and the vicinity thereof. A recess 24 is formed on the surface. The through hole 23 at the location where the recess 24 is formed is wider than the other locations. Further, the etching that proceeds from the second opening 42 has a lower etching rate than the etching that proceeds from the first opening 41, and therefore does not reach the lower surface of the semiconductor substrate 11. Further, the thickness of the substrate is such that the connection hole 27 does not reach the lower surface of the semiconductor substrate even when overetching is performed.

  Referring to FIG. 6B, first, the etching mask 40 is removed, and then the adhesive is melted and the support substrate 44 is peeled off. Thereafter, the insulating film 12 is formed on the surface of the semiconductor substrate 11 including the inner walls of the connection hole 27 and the through hole 23. As can be said in all the embodiments, the insulating film 12 is generally formed by a CVD method, but may be formed by a thermal oxidation method as another method.

  Subsequently, as described with reference to FIG. 4B, the insulating film 12 located at the bottom of the connection hole 27 is removed by etching, and the semiconductor substrate 11 is exposed from the exposed portion 28.

  Next, referring to FIG. 6C, a metal film 29 is formed on the surface of the semiconductor substrate 11. A metal film 29 is formed inside the connection hole 27 to form the connection electrode 16.

  Here, first, the semiconductor substrate 11 is provided on a table in a deposition chamber, and a barrier layer is formed from the upper surface. Here, the barrier layer is made of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), tantalum nitride (TaN), or the like, and is formed by sputtering or CVD. Therefore, a barrier film is formed except for the back surface of the semiconductor substrate 11.

  Subsequently, the semiconductor substrate 11 is inverted on the wafer table, and a barrier film is formed from the back surface of the substrate 11. Therefore, a barrier film is formed on all of the connection hole 27, the through hole 23, and the front and back of the substrate. However, since the barrier film is formed on the back and front, the barrier film in the through hole 23 is formed thicker than the connection hole 27.

  Subsequently, Cu is electroplated using the barrier layer as a seed layer to form a metal film 29. Then, a desired patterning is performed using a photoetching method. At this time, since the metal film 29 is also formed in the recess 24, an anchor effect is generated, and the adhesion strength between the through electrode 13 and the semiconductor substrate 11 is improved.

  Finally, referring to FIG. 6D, the first conductive pattern 14 and the second conductive pattern 15 are formed by patterning the metal film 29 formed on the top surface and the back surface of the semiconductor substrate 11. . Here, patterning is not possible at the same time for the front and back sides, so it is performed separately for the front and back sides.

<Fifth embodiment>
A fifth embodiment will be described with reference to FIG. In this embodiment, a method for manufacturing a circuit board in which through holes and connection holes are formed by etching from both main surfaces of the semiconductor substrate 11 will be described.

  With reference to FIG. 7A, first, the front surface and the back surface of the semiconductor substrate 11 are covered with a first etching mask 45 and a second etching mask 46.

  The first etching mask 45 is provided with two first openings 47 and 48, and the second etching mask 46 is provided with second openings 49 and 50. The first opening 47 is provided to form a through hole that penetrates the semiconductor substrate 11. The first opening 48 is provided to form a connection hole extending partway from the upper surface of the semiconductor substrate 11.

  The width (W1) of the first opening 47 and the width (W2) of the first opening 48 may be approximately the same, for example, 10 to 40 μm. In this embodiment, since the through hole is formed by etching performed from both the upper surface and the back surface of the semiconductor substrate 11, the etching that proceeds from the upper surface of the semiconductor substrate 11 only needs to reach the vicinity of the central portion in the thickness direction of the semiconductor substrate 11. .

  The second etching mask 46 is provided with two second openings 50 and 49. The second opening 50 is formed to provide a through-hole penetrating the semiconductor substrate 11, and its planar position overlaps with the first opening 47 provided in the first etching mask 45. Yes. Thus, a through hole can be formed by etching that proceeds downward from the first opening 47 and etching that proceeds upward from the second opening 50.

  The width (W3) of the second opening 50 and the width (W4) of the second opening 49 are formed to be approximately the same, for example, 10 to 40 μm. Furthermore, the planar size of the second openings 49 and 50 provided in the second etching mask 46 may be equal to that of the first openings 47 and 48 provided in the first etching mask 45.

  Referring to FIG. 7B, next, the semiconductor substrate 11 is etched through the first etching mask 45 and the second etching mask 46, and the through hole 23 and the connection hole 27 extending to the middle, 32 is formed.

  In this embodiment, etching may be performed simultaneously from the upper surface and the back surface of the semiconductor substrate 11, or etching may be performed from one main surface of the semiconductor substrate 11 and then etching from the other main surface.

  As described above, the planar position of the first opening 47 provided in the first etching mask 45 and the second opening 50 provided in the second etching mask coincide. Accordingly, when etching is performed from the upper surface and the back surface of the semiconductor substrate 11, the etching that proceeds downward from the first opening 47 and the etching that proceeds upward from the second opening 50 penetrate through the semiconductor substrate 11. A hole 23 is formed. When the first opening 47 and the second opening 50 are equal in size and the planar positions of the two are the same, the through-hole 23 having a straight side surface is formed. However, there may be a case where the through-hole is displaced due to the displacement of the photomask.

  Here, by forming either the first opening 47 or the second opening 50 larger than the other, the through-hole 23 is formed even when the positions of both openings are shifted. Can do. For example, if the width of the first opening 47 is formed to 100 μm and the width of the second opening 50 is formed to 50 μm, even if the relative positions of both are formed shifted by about 40 μm, the second opening The part 50 is located below the first opening 47. Therefore, the through-hole 23 can be formed by etching that proceeds from both openings.

  The connection hole 27 is formed by etching the semiconductor substrate 11 from the first opening 48 provided in the first etching mask 45. The depths of the connection holes 27 and 32 are slightly deeper than half the thickness of the substrate 11.

  Next, referring to FIG. 7C, an insulating film 12 is formed on the surface of the semiconductor substrate 11. Specifically, the insulating film 12 is formed on the surface of the semiconductor substrate 11 so as to cover the inner walls of the connection holes 27, the connection holes 32, and the through holes 23. Further, the insulating film 12 covering the bottom surfaces of the connection holes 27 and the connection holes 32 is removed, and the semiconductor substrate 11 is exposed from the bottom surfaces thereof.

  Referring to FIG. 7D, next, a metal film is formed on the surface of the semiconductor substrate 11, and this metal film is patterned, whereby the first conductive pattern 14 is formed on the upper surface and the back surface of the semiconductor substrate 11. Then, the second conductive pattern 15 is formed. By forming a metal film inside the connection hole 27, the connection electrode 16 that connects the first conductive pattern 14 and the semiconductor substrate 11 is formed. By forming a metal film inside the connection hole 32, the connection electrode 17 that connects the second conductive pattern 15 and the semiconductor substrate 11 is formed. Further, a through electrode 13 that connects the first conductive pattern 14 and the second conductive pattern 15 is formed in the through hole 23.

It is a figure which shows the circuit board of this invention, (A)-(C) is sectional drawing. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the circuit apparatus by which the circuit circuit board of this invention was employ | adopted, (A) and (B) are sectional drawings. It is a figure which shows the manufacturing method of the circuit board of this invention, (A)-(C) is sectional drawing. It is a figure which shows the manufacturing method of the circuit board of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit board of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit board of this invention, (A)-(D) is sectional drawing. It is a figure which shows the manufacturing method of the circuit board of this invention, (A)-(D) is sectional drawing. It is sectional drawing which shows the conventional circuit board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Circuit board 11 Semiconductor substrate 12 Insulation film 13 Through electrode 14 1st conductive pattern 15 2nd conductive pattern 16 Connection electrode 17 Connection electrode 18 Circuit element 18A Chip element 18B Semiconductor element 19 Bump electrode 20A, 20B Circuit apparatus 21 External electrode DESCRIPTION OF SYMBOLS 22 Covering layer 23 Through-hole 24 Recessed part 25 Metal fine wire 26 Bonding agent 27 Connection hole 28 Exposed part 29 Metal film 30 Mounting substrate 31 Conductive path 32 Connection hole 33 Opening part 34 Etching mask 35 Barrier film 36 Underfill 37 Sealing resin 40 Etching Mask 41 First opening 42 Second opening 43 Adhesive 44 Support substrate 45 First etching mask 46 Second etching mask 47, 48 First opening 49, 50 Second opening

Claims (28)

A semiconductor substrate;
A through electrode provided through the semiconductor substrate in the thickness direction;
A circuit board, comprising: a connection electrode that extends partway along a thickness direction of the semiconductor substrate and is electrically connected to the semiconductor substrate.   The circuit board according to claim 1, wherein the connection electrode is formed thinner than the through electrode.   2. The circuit board according to claim 1, wherein the semiconductor substrate is made of a semiconductor into which impurities are introduced.   The circuit board according to claim 1, wherein the semiconductor substrate is connected to a ground potential through the connection electrode.   The circuit board according to claim 1, wherein the through electrode is insulated from the semiconductor substrate by an insulating film provided on an inner wall of the through hole. A conductive pattern is formed on at least one main surface of the semiconductor substrate via an insulating layer,
The circuit board according to claim 1, wherein the conductive pattern and the semiconductor substrate are set to the same potential via the connection portion.   The circuit board according to claim 1, wherein the connection electrode and the semiconductor substrate are electrically connected via a barrier film. A circuit element is fixed to one main surface of the circuit board,
The circuit board according to claim 1, wherein the other main surface of the circuit board is fixed to a mounting board. A circuit comprising a through electrode embedded in a through hole penetrating a semiconductor substrate, and a connection electrode embedded in a connection hole extending partway in the thickness direction of the semiconductor substrate and electrically connected to the semiconductor substrate In the manufacturing method of the device,
The method for manufacturing a circuit board, wherein the through hole and the connection hole are formed by etching performed from one main surface of the semiconductor substrate. Preparing a semiconductor substrate; and
Covering one main surface of the semiconductor substrate with an etching mask having a first opening and a second opening smaller than the first opening;
By etching the semiconductor substrate from one main surface through the etching mask, a through hole penetrating the semiconductor substrate is formed from the first opening, and further, the semiconductor substrate is extended halfway in the thickness direction. Forming an existing connection hole from the second opening;
Forming a through electrode by forming a conductive material inside the through hole, and forming a connection electrode electrically connected to the semiconductor substrate by forming a conductive material inside the connection hole; A method of manufacturing a circuit board, comprising: A step of covering the inner wall of the through hole and the connection hole with an insulating film;
10. The semiconductor substrate and the connection electrode are electrically connected by forming the connection electrode after removing the insulating film located at the bottom of the connection hole. 10. A method for manufacturing a circuit board according to 10.   11. The method of manufacturing a circuit board according to claim 10, wherein an etching rate of etching proceeding from the second opening is smaller than an etching rate of etching proceeding from the first opening. A circuit comprising a through electrode embedded in a through hole penetrating a semiconductor substrate, and a connection electrode embedded in a connection hole extending partway in the thickness direction of the semiconductor substrate and electrically connected to the semiconductor substrate In the manufacturing method of the device,
A method of manufacturing a circuit board, wherein the through hole is formed by etching performed from both main surfaces of the semiconductor substrate. Preparing a semiconductor substrate; and
One main surface of the semiconductor substrate is covered with a first etching mask provided with a first opening, and the other main surface of the semiconductor substrate is covered with a second etching mask provided with a second opening. Coating with,
By etching the semiconductor from both main surfaces, etching proceeds from both the first opening and the second opening to form a through-hole penetrating the semiconductor substrate, and the first opening Forming a connection hole extending partway in the thickness direction of the semiconductor substrate by etching that proceeds from a portion or the second opening, and
Forming a through electrode by forming a conductive material inside the through hole, and forming a connection electrode electrically connected to the semiconductor substrate by forming a conductive material inside the connection hole; A method of manufacturing a circuit board, comprising:   15. The method of manufacturing a circuit device according to claim 13, wherein the connection hole and the through hole are simultaneously formed by simultaneously etching both main surfaces of the semiconductor substrate.   15. The method for manufacturing a circuit board according to claim 13, wherein etching performed from one main surface of the semiconductor substrate and etching performed from the other main surface are performed separately.   2. The through hole is formed by etching performed from both main surfaces of the semiconductor substrate by overlapping a planar position of the first opening and the second opening. Item 15. A method for manufacturing a circuit device according to Item 14.   15. The method for manufacturing a circuit device according to claim 14, wherein the first opening and the second opening are different in planar size. A step of covering the inner wall of the through hole and the connection hole with an insulating film;
14. The semiconductor substrate and the connection electrode are electrically connected by forming the connection electrode after removing the insulating film located at the bottom of the connection hole. 14. A method for manufacturing a circuit board according to 14. A method for manufacturing a semiconductor device in which a semiconductor substrate is prepared, etched through a plurality of etching regions having different sizes, and a plurality of holes are formed.
Due to the difference in etching speed due to the size of the etching area,
A method of manufacturing a semiconductor device, wherein the first hole penetrates the semiconductor substrate and the second hole does not penetrate. At least the sides of the first hole and the second hole are insulated;
In the first hole, a conductive film that electrically connects device electrodes to be formed on the front and back of the semiconductor substrate is formed,
21. The method of manufacturing a semiconductor device according to claim 20, wherein the second hole is provided with a conductive film for connecting a GND or Vcc electrode on the front or back of the semiconductor substrate to the semiconductor substrate.   21. The method of manufacturing a semiconductor device according to claim 20, wherein a wiring is formed in a plurality of layers on at least one surface of the semiconductor substrate, and a circuit element is mounted using the semiconductor substrate as a mounting substrate.   21. The method of manufacturing a semiconductor device according to claim 20, wherein the semiconductor substrate is mounted on a flexible sheet having electrodes. A semiconductor mounting substrate made of substantially the same material as the substrate of the semiconductor element;
A front electrode and a back electrode provided through a through electrode penetrating the semiconductor mounting substrate;
A semiconductor device comprising: the semiconductor element electrically connected to the surface electrode and provided on a semiconductor mounting substrate.   25. The semiconductor device according to claim 24, wherein a sealing material that covers at least a semiconductor element is provided on the semiconductor mounting substrate.   25. The semiconductor device according to claim 24, further comprising a flexible substrate having electrodes on the back surface of the semiconductor mounting substrate.   25. The semiconductor device according to claim 24, further comprising an electrode that exposes the semiconductor mounting substrate and is fixed to GND or Vcc. 28. The semiconductor device according to claim 27, wherein the electrode fixed to GND or Vcc is connected to an exposed portion formed of a recessed portion of the semiconductor mounting substrate.

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