JP2005188949A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with a built-in test circuit capable of measuring fluctuations of delay time by the influence of a cross-talk caused by parallel wiring under various conditions. <P>SOLUTION: This semiconductor integrated circuit includes at least one circuit block 10 connected between an input terminal and an output terminal. The circuit block comprises a first circuit 11 buffering a signal to be inputted to the circuit block; a first signal line 12 connected to the output of the first circuit; at least one second circuit 13 to which a signal outputted from the first circuit is inputted through the first signal line; a second signal line 14 having a part arranged along the first signal line; and a third circuit 15 selectively supplying a signal inputted to the circuit block to the second signal line in a positive phase or a reverse phase based on a control signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention generally relates to semiconductor integrated circuits, and in particular, is used in layout design of ASICs (Application Specific ICs) such as gate arrays and standard cells designed by arranging and wiring a plurality of cells. The present invention relates to a semiconductor integrated circuit used for creating a delay library.

  In a semiconductor integrated circuit such as an ASIC, layout design is performed by arranging a plurality of cells for realizing various logic circuits in a layout area and wiring between these cells. In the layout design of a semiconductor integrated circuit, it is necessary to verify whether or not the circuit operates normally in consideration of the delay time in each cell. As the delay time, a delay time due to circuit elements such as transistors and a delay time due to wiring are included, but when there are a plurality of parallel wirings, the delay time is caused by the influence of crosstalk caused by parallel wiring. Will fluctuate. It is also conceivable to control the delay time by actively providing parallel wiring.

  Therefore, it is desirable to equip a library used for layout design of a semiconductor integrated circuit with a delay model that takes into account fluctuations in delay time due to the influence of crosstalk caused by parallel wiring, and to use it for simulation of circuit operation. In order to create such a delay model, it is necessary to create a semiconductor integrated circuit incorporating a measurement circuit actually provided with parallel wiring and measure the delay time.

  By the way, the following Patent Document 1 discloses a crosstalk delay measurement circuit that is mounted on a semiconductor integrated device having a built-in test circuit for testing delay time variations due to manufacturing process variations and can measure delay due to crosstalk. Yes. In this crosstalk delay measurement circuit, the signal under measurement propagating through the signal line is inverted by the signal inversion circuit and then output to the adjacent parallel line, so that the signal opposite in phase to the measured signal is propagated to the adjacent parallel line. The crosstalk is intentionally generated.

However, this crosstalk delay measurement circuit can measure the case where the delay time of the signal under test increases due to crosstalk between the signal under test and the signal out of phase, but the delay time of the signal under test changes depending on the conditions. It is not possible to measure the case where the value decreases. In addition, since only one buffer is provided on the signal line, it is impossible to measure the influence of fan-out on the delay time in the presence of crosstalk.
JP 2003-215207 A (pages 1 and 2, FIG. 1)

  Therefore, in view of the above points, the present invention provides a semiconductor integrated circuit including a test circuit capable of measuring a variation in delay time due to the influence of crosstalk caused by parallel wiring under various conditions. Objective.

  In order to solve the above problems, a semiconductor integrated circuit according to a first aspect of the present invention is a semiconductor integrated circuit including at least one circuit block connected between an input terminal and an output terminal. The block has a first circuit that buffers a signal input to the circuit block, a first signal wiring connected to the output of the first circuit, and a signal output from the first circuit is a first signal Based on at least one second circuit inputted through the signal wiring, a second signal wiring having a portion arranged along the first signal wiring, and a control signal, the circuit block is inputted. And a third circuit that selectively supplies the first signal to the second signal wiring in the normal phase or the reverse phase.

  A semiconductor integrated circuit according to a second aspect of the present invention is a semiconductor integrated circuit including a first group of circuit blocks connected in series with each other and a second group of circuit blocks connected in series with each other. The first group and the second group of circuit blocks each have a first circuit for buffering a signal input to the circuit block, a first signal wiring connected to the output of the first circuit, and a first At least one second circuit to which a signal output from the first circuit is input via the first signal wiring, a second signal wiring having a portion arranged along the first signal wiring, and a control And a third circuit that selectively supplies a signal input to the circuit block to the second signal wiring in the normal phase or the reverse phase based on the signal, and the first circuit in each of the second group of circuit blocks. And the length of the second signal wiring is the first group of circuit blocks. Equal to the length of the first and second signal lines in each.

  Furthermore, a semiconductor integrated circuit according to a third aspect of the present invention is a semiconductor integrated circuit including a first group of circuit blocks connected in series with each other and a second group of circuit blocks connected in series with each other. The first group and the second group of circuit blocks each have a first circuit for buffering a signal input to the circuit block, a first signal wiring connected to the output of the first circuit, and a first At least one second circuit to which a signal output from the first circuit is input via the first signal wiring, a second signal wiring having a portion arranged along the first signal wiring, and a control And a third circuit that selectively supplies a signal input to the circuit block to the second signal wiring in a normal phase or a reverse phase based on the signal, and a second circuit in each of the second group of circuit blocks. The number of circuits in each of the first group of circuit blocks Different from the number of the second circuit.

  In the semiconductor integrated circuit according to the second or third aspect of the present invention, switching for supplying a signal input to the input terminal to a selected one of the first group of circuit blocks and the second group of circuit blocks. A circuit may be further included. The semiconductor integrated circuit may further include a switching circuit that supplies a signal output from a selected one of the first group of circuit blocks and the second group of circuit blocks to an output terminal.

  In the above, when the control signal is at the first level, the third circuit supplies the signal input to the circuit block to the second signal wiring in the positive phase, and the control signal is at the second level. Sometimes, a signal input to the circuit block may be supplied to the second signal wiring in reverse phase.

  Alternatively, the third circuit may selectively supply the power supply potential to the second signal wiring based on the control signal, or may selectively set the second signal wiring to the high impedance state. . In that case, it is desirable that the control signal has a plurality of bits.

  According to the first aspect of the present invention, variation in delay time due to the influence of crosstalk caused by parallel wiring can be measured under different phase conditions. Further, according to the second aspect of the present invention, the variation in delay time due to the influence of crosstalk caused by parallel wiring can be measured in the first group and second group circuit blocks having different wiring lengths. . Furthermore, according to the third aspect of the present invention, it is possible to measure the variation in delay time due to the influence of crosstalk caused by parallel wiring in the first and second group circuit blocks having different numbers of fanouts. it can. By using such measurement results, the library used for layout design of semiconductor integrated circuits is equipped with a delay model that takes into account fluctuations in delay time due to the effects of crosstalk caused by parallel wiring, for circuit operation simulations, etc. It can be used.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a part of the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit includes a plurality of circuit blocks 10 connected in series between an input terminal and an output terminal. The reason why the plurality of circuit blocks are connected in series is to increase the measurement accuracy by measuring the total delay time of the signals in each circuit block, and the semiconductor integrated circuit has at least one circuit. It only needs to contain blocks.

  A signal input to the input terminal sequentially passes through these circuit blocks 10 and is supplied to the output terminal from the last circuit block. The control terminal is used to input a control signal S for controlling the operation of the circuit block 10.

  FIG. 2 is a circuit diagram showing an internal circuit of the circuit block in FIG. The circuit block 10 includes a buffer circuit 11 for buffering an input signal IN of the circuit block, a first signal wiring 12 connected to the output of the buffer circuit 11, and an output signal of the buffer circuit 11 as a first signal wiring 12 Based on the control signal S, a plurality of buffer circuits 13 that are input via the first signal wiring 12, a second signal wiring 14 having a portion disposed along the first signal wiring 12 And a crosstalk control circuit 15 that selectively supplies the second signal wiring 14 in reverse phase. One of the plurality of buffer circuits 13 is used to output a signal from the circuit block 10, while the other buffer circuit 13 is for adding a capacity to the first signal wiring 12. It can be omitted.

  The crosstalk control circuit 15 includes an AND circuit 15a that obtains a logical product of the signal A and the control signal S, an inverted input AND circuit 15b that obtains a logical product of the signal B and the control signal S by inverting input thereof, An OR circuit 15c for calculating the logical sum of the output signal of the AND circuit 15a and the output signal of the AND circuit 15b is included.

  FIG. 3 is a truth table for explaining the operation of the crosstalk control circuit shown in FIG. As the signals A and B, the input signal IN of the circuit block 10 is used. When the control signal S is at a high level (1), the crosstalk control circuit 15 outputs the input signal IN of the circuit block 10 as the output signal X and supplies it to the second signal wiring 14. As a result, in-phase crosstalk from the second signal wiring 14 to the first signal wiring 12 occurs, and the signal delay time in the circuit block 10 is minimized.

  On the other hand, when the control signal S is at a low level (0), the crosstalk control circuit 15 inverts the input signal IN of the circuit block 10 and outputs the signal IN bar as the output signal X. 2 is supplied to the second signal wiring 14. As a result, reverse-phase crosstalk from the second signal wiring 14 to the first signal wiring 12 occurs, and the signal delay time in the circuit block 10 is maximized.

  By measuring the signal delay time while changing the control signal to high level or low level, the fluctuation of the delay time due to the influence of crosstalk caused by parallel wiring can be measured under two different phase conditions. Can do. By using such measurement results, the library used for layout design of semiconductor integrated circuits is equipped with a delay model that takes into account fluctuations in delay time due to the effects of crosstalk caused by parallel wiring, for circuit operation simulations, etc. It can be used.

Next, a second embodiment of the present invention will be described.
FIG. 4 is a block diagram showing a part of the configuration of the semiconductor integrated circuit according to the second embodiment of the present invention. As shown in FIG. 4, the semiconductor integrated circuit includes a plurality of circuit blocks 20 connected in series between an input terminal and an output terminal. The reason why the plurality of circuit blocks are connected in series is to increase the measurement accuracy by measuring the total delay time of the signals in each circuit block, and the semiconductor integrated circuit has at least one circuit. It only needs to contain blocks.

  A signal input to the input terminal sequentially passes through these circuit blocks 20 and is supplied to the output terminal from the last circuit block. The two control terminals are used to input 2-bit control signals S1 and S2 for controlling the operation of the circuit block 20.

  FIG. 5 is a circuit diagram showing an internal circuit of the circuit block in FIG. The circuit block 20 includes a buffer circuit 21 that buffers the input signal IN of the circuit block, a first signal wiring 22 connected to the output of the buffer circuit 21, and an output signal of the buffer circuit 21 is a first signal wiring 22. A plurality of buffer circuits 23 input via the first signal wiring 22, a second signal wiring 24 having a portion arranged along the first signal wiring 22, and the input signal IN based on the control signal in the normal phase or reverse phase And a crosstalk control circuit 25 that selectively supplies the second signal wiring 24 in phase. One of the plurality of buffer circuits 23 is used to output a signal from the circuit block 20, but the other buffer circuit 23 is for adding a capacity to the first signal wiring 22. It can be omitted.

The crosstalk control circuit 25 is supplied with the input signal IN of the circuit block 20 as a signal A. The input signal IN is inverted by the crosstalk control circuit 25 to become a signal B. Further, the power supply potential V _DD is supplied as the signal C to the crosstalk control circuit 25, and the power supply potential V _SS (referred to as the ground potential in this embodiment) is supplied as the signal D.

  FIG. 6 is a truth table for explaining the operation of the crosstalk control circuit shown in FIG. When the control signal (S1, S2) is (0, 0), the crosstalk control circuit 25 outputs the input signal IN of the circuit block 20 as the output signal X, and supplies this to the second signal wiring 24. To do. As a result, in-phase crosstalk from the second signal wiring 24 to the first signal wiring 22 occurs, and the signal delay time in the circuit block 20 is minimized.

  On the other hand, the crosstalk control circuit 25 outputs the signal IN bar as the output signal X by inverting the input signal IN of the circuit block 20 when the control signals (S1, S2) are (0, 1). This is supplied to the second signal wiring 24. As a result, reverse-phase crosstalk from the second signal wiring 24 to the first signal wiring 22 occurs, and the signal delay time in the circuit block 20 is maximized.

  Further, when the control signals (S1, S2) are (1, 0), the crosstalk control circuit 25 outputs a high level (1) signal as the output signal X, which is output to the second signal wiring 24. To supply. Further, when the control signal (S1, S2) is (1, 1), the crosstalk control circuit 15 outputs a low level (0) signal as the output signal X, which is output to the second signal wiring 24. To supply. As a result, the second signal wiring 24 functions as a shield for the first signal wiring 22, and the signal delay time in the circuit block 20 becomes standard. Note that the crosstalk control circuit 25 may place the second signal wiring 24 in a high impedance state instead of supplying a high level or low level signal to the second signal wiring 24.

  By measuring the delay time of the signal while changing the control signal, the variation in the delay time due to the influence of crosstalk caused by the parallel wiring can be measured under four different conditions. By using such measurement results, the library used for layout design of semiconductor integrated circuits is equipped with a delay model that takes into account fluctuations in delay time due to the effects of crosstalk caused by parallel wiring, for circuit operation simulations, etc. It can be used.

Next, a third embodiment of the present invention will be described.
FIG. 7 is a block diagram showing a part of the configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. As shown in FIG. 7, this semiconductor integrated circuit includes a first group of circuit blocks 30 connected in series with each other, a second group of circuit blocks 40 connected in series with each other, and a signal input to an input terminal. Switching circuit 50 for supplying a selected one of the first group of circuit blocks 30 and the second group of circuit blocks 40, and the first group of circuit blocks 30 and the second group of circuit blocks 40 And a switching circuit 60 for supplying a signal output from one selected from the output terminal to the output terminal.

  The reason why the plurality of circuit blocks are connected in series is to increase the measurement accuracy by measuring the total delay time of the signals in each circuit block, and the semiconductor integrated circuit has at least two circuits. It only has to contain blocks. Further, the switching circuit 50 may be omitted, and a signal input to the input terminal may be supplied to both the first group of circuit blocks 30 and the second group of circuit blocks 40. Omitted, two signals output from both the first group of circuit blocks 30 and the second group of circuit blocks 40 may be supplied to the two output terminals, respectively.

  A signal input to the input terminal sequentially passes through the first group of circuit blocks 30 or the second group of circuit blocks 40 via the switching circuit 50, and from the last circuit block to the output terminal via the switching circuit 60. Supplied. The two control terminals are used to input 2-bit control signals S1 and S2. Among these, the control signal S1 is used for controlling the phase of the crosstalk signal in the first and second group circuit blocks 30 and 40, and the control signal S2 is used to switch the signals in the switching circuits 50 and 60. Used to control.

  FIG. 8 is a circuit diagram showing an internal circuit of the first group of circuit blocks in FIG. The configuration of the first group of circuit blocks 30 is the same as that of the circuit block 10 shown in FIG. 2, except that the first signal wiring 32 between the output of the buffer circuit 31 and the input of the buffer circuit 33, The length of the second signal wiring 34 having a portion arranged along the signal wiring 32 is shortened. Here, the length in which the first signal wiring 32 and the second signal wiring 34 run in parallel is defined as L1.

  FIG. 9 is a circuit diagram showing an internal circuit of the second group of circuit blocks in FIG. The configuration of the second group of circuit blocks 40 is the same as that of the first group of circuit blocks 30 shown in FIG. 8, except that the first signal wiring 42 between the output of the buffer circuit 41 and the input of the buffer circuit 43 The length of the second signal wiring 44 having a portion arranged along the first signal wiring 42 is long. Here, if the length that the first signal wiring 42 and the second signal wiring 44 run in parallel is L2, at least L2 ≧ 2 × L1, for example, L2 ≧ 10 × L1 may be satisfied.

  By measuring the signal delay time while changing the control signal, the variation in the delay time due to the influence of crosstalk caused by the parallel wiring is measured in the first group and second group circuit blocks having different wiring lengths. can do. For example, it is possible to compare which delay time is smaller when receiving in-phase crosstalk with a long parallel wiring and when receiving reverse-phase crosstalk with a short parallel wiring. By using such measurement results, the library used for layout design of semiconductor integrated circuits is equipped with a delay model that takes into account fluctuations in delay time due to the effects of crosstalk caused by parallel wiring, for circuit operation simulations, etc. It can be used.

Next, a fourth embodiment of the present invention will be described.
FIG. 10 is a block diagram showing a part of the configuration of a semiconductor integrated circuit according to the fourth embodiment of the present invention. As shown in FIG. 10, the semiconductor integrated circuit includes a first group of circuit blocks 70 connected in series with each other, a second group of circuit blocks 80 connected in series with each other, and a signal input to an input terminal. Of the switching circuit 50 for supplying a selected one of the first group of circuit blocks 70 and the second group of circuit blocks 80, and the first group of circuit blocks 70 and the second group of circuit blocks 80 to each other. And a switching circuit 60 for supplying a signal output from one selected from the output terminal to the output terminal.

  The reason why the plurality of circuit blocks are connected in series is to increase the measurement accuracy by measuring the total delay time of the signals in each circuit block, and the semiconductor integrated circuit has at least two circuits. It only has to contain blocks. Further, the switching circuit 50 may be omitted, and a signal input to the input terminal may be supplied to both the first group of circuit blocks 70 and the second group of circuit blocks 80. Omitted, two signals output from both the first group of circuit blocks 70 and the second group of circuit blocks 80 may be supplied to the two output terminals, respectively.

  A signal input to the input terminal sequentially passes through the first group of circuit blocks 70 or the second group of circuit blocks 80 via the switching circuit 50, and from the last circuit block to the output terminal via the switching circuit 60. Supplied. The two control terminals are used to input 2-bit control signals S1 and S2. Among these, the control signal S1 is used for controlling the phase of the crosstalk signal in the first and second group circuit blocks 30 and 40, and the control signal S2 is used to switch the signals in the switching circuits 50 and 60. Used to control.

  FIG. 11 is a circuit diagram showing an internal circuit of the first group of circuit blocks in FIG. The configuration of the first group of circuit blocks 70 is the same as that of the circuit block 10 shown in FIG. 2, but the number of buffer circuits 73 connected to the output of the buffer circuit 71 via the first signal wiring 72 is small. The load capacity of the buffer circuit 71 is small. Here, the number of buffer circuits 73 is N1.

  FIG. 12 is a circuit diagram showing an internal circuit of the second group of circuit blocks in FIG. The configuration of the second group of circuit blocks 80 is the same as that of the first group of circuit blocks 70 shown in FIG. 11 except that the buffer circuit 83 connected to the output of the buffer circuit 81 via the first signal wiring 82. Since the number is large, the load capacity of the buffer circuit 81 is large. Here, assuming that the number of buffer circuits 83 is N2, at least N2 ≧ 2 × N1, for example, N2 ≧ 10 × N1, specifically, N1 = 1 and N2 = 10.

  By measuring the delay time of the signal while changing the control signal, the variation in the delay time due to the influence of the crosstalk caused by the parallel wiring is detected in the circuit blocks of the first group and the second group with different numbers of fan-outs. Can be measured. For example, it is possible to compare which delay time is smaller when the fan-out number is small and subjected to reverse-phase crosstalk and when the fan-out number is large and subjected to in-phase crosstalk. By using such measurement results, the library used for layout design of semiconductor integrated circuits is equipped with a delay model that takes into account fluctuations in delay time due to the effects of crosstalk caused by parallel wiring, for circuit operation simulations, etc. It can be used. A plurality of the embodiments described above may be combined.

  The present invention can be used in a semiconductor integrated circuit used for creating a delay library used in ASIC layout design such as a gate array and a standard cell designed by arranging and wiring a plurality of cells. is there.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. The circuit diagram which shows the internal circuit of the circuit block in FIG. 3 is a truth table for explaining the operation of the crosstalk control circuit shown in FIG. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. FIG. 5 is a circuit diagram showing an internal circuit of the circuit block in FIG. 4. 6 is a truth table for explaining the operation of the crosstalk control circuit shown in FIG. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on the 3rd Embodiment of this invention. FIG. 8 is a circuit diagram showing an internal circuit of a first group of circuit blocks in FIG. 7. FIG. 8 is a circuit diagram showing an internal circuit of a second group of circuit blocks in FIG. 7. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. FIG. 11 is a circuit diagram showing an internal circuit of a first group of circuit blocks in FIG. 10. FIG. 11 is a circuit diagram showing an internal circuit of a second group of circuit blocks in FIG. 10.

Explanation of symbols

10, 20, 30, 40, 70, 80 Circuit block 11, 13, 21, 23, 31, 33, 41, 43, 71, 73, 81, 83 Buffer circuit 12, 22, 32, 42, 72, 82, first signal wiring, 14, 24, 34, 44 second signal wiring, 15, 25 crosstalk control circuit, 15a AND circuit, 15b inverting input AND circuit, 15c OR circuit, 50, 60 switching circuit

Claims (9)

A semiconductor integrated circuit including at least one circuit block connected between an input terminal and an output terminal, the circuit block comprising:
A first circuit for buffering a signal input to the circuit block;
A first signal line connected to the output of the first circuit;
At least one second circuit in which a signal output from the first circuit is input via the first signal wiring;
A second signal wiring having a portion disposed along the first signal wiring;
A third circuit for selectively supplying a signal input to the circuit block to the second signal wiring in a normal phase or a reverse phase based on a control signal;
A semiconductor integrated circuit comprising: A semiconductor integrated circuit including a first group of circuit blocks connected in series with each other and a second group of circuit blocks connected in series with each other, wherein each of the first group and the second group of circuit blocks includes:
A first circuit for buffering a signal input to the circuit block;
A first signal line connected to the output of the first circuit;
At least one second circuit in which a signal output from the first circuit is input via the first signal wiring;
A second signal wiring having a portion disposed along the first signal wiring;
A third circuit for selectively supplying a signal input to the circuit block to the second signal wiring in a normal phase or a reverse phase based on a control signal;
And the lengths of the first and second signal lines in each of the second group of circuit blocks are the same as the lengths of the first and second signal lines in each of the first group of circuit blocks. Different semiconductor integrated circuit. A semiconductor integrated circuit including a first group of circuit blocks connected in series with each other and a second group of circuit blocks connected in series with each other, wherein each of the first group and the second group of circuit blocks includes:
A first circuit for buffering a signal input to the circuit block;
A first signal line connected to the output of the first circuit;
At least one second circuit in which a signal output from the first circuit is input via the first signal wiring;
A second signal wiring having a portion disposed along the first signal wiring;
A third circuit for selectively supplying a signal input to the circuit block to the second signal wiring in a normal phase or a reverse phase based on a control signal;
And the number of the second circuits in each of the second group of circuit blocks is different from the number of the second circuits in each of the first group of circuit blocks.   4. The semiconductor integrated circuit according to claim 2, further comprising a switching circuit for supplying a signal input to an input terminal to a selected one of the first group of circuit blocks and the second group of circuit blocks.   5. The switching circuit according to claim 2, further comprising a switching circuit that supplies a signal output from a selected one of the first group of circuit blocks and the second group of circuit blocks to an output terminal. Semiconductor integrated circuit.   When the control signal is at the first level, the third circuit supplies the signal input to the circuit block to the second signal wiring in the positive phase, and the control signal is at the second level. 6. The semiconductor integrated circuit according to claim 1, wherein a signal input to the circuit block is supplied to the second signal wiring in reverse phase.   The semiconductor integrated circuit according to claim 1, wherein the third circuit selectively supplies a power supply potential to the second signal wiring based on a control signal.   The semiconductor integrated circuit according to claim 1, wherein the third circuit selectively sets the second signal wiring to a high impedance state based on a control signal.   9. The semiconductor integrated circuit according to claim 7, wherein the control signal has a plurality of bits.

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