JP2005183677A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of adjusting the propagation delay time of a signal on a critical path on the basis of a measurement result of an influence of variations of propagation delay time caused by crosstalk due to parallel wirings on a circuit operation. <P>SOLUTION: The semiconductor integrated circuit comprises a first circuit 13 for buffering a signal input from the preceding stage circuit, a first signal wiring 151 for supplying an output signal of the first circuit to the next stage circuit, a second signal wiring 152 having a part disposed along the first signal wiring, a second circuit 153 for selectively supplying a signal input into the first circuit to the second signal wiring in positive phase or opposite phase; and holding means 40 for holding a judgement signal to be supplied to the second circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention generally relates to a semiconductor integrated circuit, and more particularly to an ASIC (Application Specific IC) such as a gate array or a standard cell designed by arranging and wiring a plurality of cells.

  In a semiconductor integrated circuit, a signal propagation delay occurs due to an influence of a parasitic capacitance or the like in a circuit element such as a transistor or a wiring between elements. Therefore, for critical paths in which signal propagation delays have a significant effect on circuit operation, the size of the buffer that transmits signals from the preceding circuit to the succeeding circuit can be adjusted, or between the preceding and succeeding circuits. The propagation delay time is adjusted by inserting a repeater.

  By the way, when a plurality of wirings run in parallel, a phenomenon occurs in which the signal propagation delay time fluctuates due to the influence of crosstalk caused by parallel wiring. Conversely, it is conceivable to control the signal propagation delay time in the critical path by actively providing parallel wiring.

Patent Document 1 below discloses a delay adjustment circuit device for a semiconductor integrated circuit that can adjust a signal delay in units of several picoseconds without increasing the circuit scale. In this delay adjustment circuit device, adjacent wiring is formed adjacent to the signal wiring, and a signal that changes in response to the signal wiring is input to the adjacent wiring by the control circuit, thereby utilizing crosstalk. The signal delay time of the signal wiring can be changed. However, Patent Document 1 does not disclose how to generate a control signal for controlling the control circuit.
Japanese Patent Laying-Open No. 2003-224188 (first page, FIG. 3)

  Therefore, in view of the above points, the present invention adjusts the propagation delay time of a signal in a critical path based on the result of measuring the influence of fluctuations in propagation delay time due to crosstalk caused by parallel wiring on circuit operation. An object of the present invention is to provide a semiconductor integrated circuit capable of performing

  In order to solve the above problems, a semiconductor integrated circuit according to a first aspect of the present invention includes a first circuit that buffers a signal input from a preceding circuit, and an output signal of the first circuit that is output to the next stage. A first signal wiring supplied to the circuit, a second signal wiring having a portion arranged along the first signal wiring, and a signal input to the first circuit based on the determination signal Alternatively, a second circuit that selectively supplies the second signal wiring in a reverse phase and a holding unit that holds a determination signal to be supplied to the second circuit are provided. Here, the holding means may include a fuse or a nonvolatile memory.

  The semiconductor integrated circuit according to the second aspect of the present invention includes a first circuit that buffers a signal input from a preceding circuit, and a first circuit that supplies an output signal of the first circuit to a subsequent circuit. Signal wiring, a second signal wiring having a portion arranged along the first signal wiring, and a signal input to the first circuit based on the determination signal in the second phase in the normal phase or the reverse phase. A second circuit for selectively supplying the signal wiring to the first and second signal wirings, and a first and a second for latching a signal input to the data input terminal in synchronization with the clock signal and outputting the latched signal from the data output terminal A flip-flop and at least one circuit block connected between the data output terminal of the first flip-flop and the data input terminal of the second flip-flop, and buffering a signal input to the circuit block 3 circuits, A third signal line connected to the output of the third circuit, a fourth signal line having a portion arranged along the third signal line, and a signal input to the circuit block based on the control signal Generating a control block to be supplied to the fourth circuit by generating a circuit block including a fourth circuit that selectively supplies the fourth signal wiring to the fourth signal wiring in a normal phase or a reverse phase. And a determination circuit that generates a determination signal to be supplied to the second circuit by measuring the influence of the positive-phase or negative-phase crosstalk to the signal wiring of the third signal wiring on the output signal of the second flip-flop. To do. Here, the determination circuit may generate the determination signal based on the result of detecting the coincidence between the state of the input signal of the first flip-flop and the state of the output signal of the second flip-flop.

  Furthermore, a semiconductor integrated circuit according to a third aspect of the present invention includes a first circuit that buffers a signal input from a preceding circuit, and a first circuit that supplies an output signal of the first circuit to a subsequent circuit. Signal wiring, a second signal wiring having a portion arranged along the first signal wiring, and a signal input to the first circuit based on the determination signal in the second phase in the normal phase or the reverse phase. A second circuit that selectively supplies the signal wiring to the first signal wiring, and a first to fourth latch circuit that latches a signal input to the data input terminal in synchronization with the clock signal and outputs the latched signal from the data output terminal. M circuit blocks (M is a natural number) connected between the flip-flop and the data output terminal of the first flip-flop and the data input terminal of the second flip-flop, each circuit block being a circuit The signal input to the block is Based on a control circuit, a third signal line connected to the output of the third circuit, a fourth signal line having a portion arranged along the third signal line, and a control signal And a fourth circuit for selectively supplying a signal input to the circuit block to the fourth signal wiring in the normal phase or the reverse phase, and the data output of the third flip-flop. N circuit blocks connected between the terminal and the data input terminal of the fourth flip-flop (N is an integer greater than M), and each circuit block buffers a signal input to the circuit block And a fifth signal line connected to the output of the fifth circuit, a sixth signal line having a portion arranged along the fifth signal line, and a control signal The signal input to the circuit block Control signals to be supplied to the N circuit blocks and the fourth and sixth circuits, including a sixth circuit that selectively supplies the first signal wiring to the third signal wiring. The influence of the positive-phase or negative-phase crosstalk on the signal wiring on the output signal of the second flip-flop and the positive-phase or negative-phase crosstalk from the sixth signal wiring to the fifth signal wiring are the fourth. And a determination circuit for generating a determination signal to be supplied to the second circuit by measuring the influence of the signal on the output signal of the flip-flop. Here, the determination circuit detects the coincidence between the state of the input signal of the first flip-flop and the state of the output signal of the second flip-flop, the state of the input signal of the third flip-flop, and the fourth state. The determination signal may be generated by comparing the result of detecting the coincidence with the state of the output signal of the flip-flop.

  In the above, when the determination signal is in the first state, the second circuit supplies the signal input to the first circuit to the second signal wiring in the positive phase, and the determination signal is in the second state. In this case, the signal input to the first circuit may be supplied to the second signal wiring in reverse phase. Alternatively, the second circuit may selectively supply the power supply potential to the second signal wiring based on the determination signal, or the second signal wiring may be selectively set to the high impedance state. You may do it. In that case, the determination signal desirably has a plurality of bits.

  According to the first aspect of the present invention, the signal propagation delay time in the critical path is adjusted based on the result of previously measuring the influence of the fluctuation of the propagation delay time caused by the crosstalk caused by the parallel wiring on the circuit operation. Can do. According to the second aspect of the present invention, the signal propagation delay in the critical path is determined based on the result of measuring the influence of the variation in the propagation delay time due to the crosstalk caused by the parallel wiring on the circuit operation at a desired time. The time can be adjusted. Furthermore, according to the third aspect of the present invention, the influence of propagation delay time on circuit operation can be measured over a wide range.

Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a part of the configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. As shown in FIG. 1, in this semiconductor integrated circuit, a circuit 10 is configured to adjust a propagation delay time of a signal in a critical path according to a determination signal SA, and a variation in propagation delay time due to crosstalk caused by parallel wiring. A circuit to be measured 20 that is formed to measure the influence on the circuit, a determination circuit 30 that generates the determination signal SA by measuring the influence using the circuit to be measured 20, and a holding circuit that holds the determination signal SA 40. A plurality of circuits to be adjusted 10 may be provided in one semiconductor chip. Further, the determination circuit 30 may hold the determination signal for a predetermined period, and the holding circuit 40 may be omitted.

  The adjusted circuit 10 includes a flip-flop 11 that inputs a signal output from another circuit to the data input terminal D, a logic circuit 12 that operates based on a signal output from the data output terminal Q of the flip-flop 11, A buffer circuit 13 for buffering an input signal IN from the logic circuit 12, a flip-flop 14 for inputting a signal output from the buffer circuit 13 to the data input terminal D via the first signal wiring 151, and a first signal And a delay correction circuit 15 that corrects the propagation delay time of the signal in the wiring 151.

  Both flip-flops 11 and 14 operate in synchronization with the clock signal CK. However, if the signal propagation delay time in the circuit or wiring between the flip-flop 11 and the flip-flop 14, particularly the first signal wiring 151, which has a great influence, varies or fluctuates, a hold error or setup occurs in the flip-flop 14. An error occurs and correct data is not output from the flip-flop 14. Therefore, in the present embodiment, by providing the delay correction circuit 15 for correcting the propagation delay time in the path from the buffer circuit 13 to the flip-flop 14 that is a critical path, such an error is reduced. Yes.

  The delay correction circuit 15 includes a second signal wiring 152 having a portion arranged along the first signal wiring 151, and the second signal wiring 152 with the input signal IN in the normal phase or the reverse phase according to the determination signal SA. And a crosstalk control circuit 153 that selectively supplies the signal.

  The crosstalk control circuit 153 includes an AND circuit 153a that obtains a logical product of the signal A and the determination signal SA, an inverted input AND circuit 153b that obtains a logical product of the signal B and the determination signal SA by inverting input thereof, An OR circuit 153c that calculates the logical sum of the output signal of the AND circuit 153a and the output signal of the AND circuit 153b is included. The determination signal SA to be supplied to the crosstalk control circuit 153 is generated by the determination circuit 30 by measuring the influence of the signal propagation delay time on the circuit operation in the circuit under test 20, and the holding circuit 40 holds the determination signal SA. .

  The circuit under test 20 includes flip-flops 21 and 22 that operate in synchronization with the clock signal CK, and a plurality of circuit blocks 23 connected in series between the flip-flop 21 and the flip-flop 22. The reason why the plurality of circuit blocks are connected in series in this way is to expand and measure the influence on the circuit operation by summing the propagation delay times of the signals in each circuit block. It suffices to include at least one circuit block.

  A signal output from the data output terminal Q of the flip-flop 21 sequentially passes through these circuit blocks 23 and is supplied from the last circuit block to the data input terminal D of the flip-flop 22. A control signal SB for controlling the operation of the circuit block 23 is input from the determination circuit 30 to each circuit block 23. Since the flip-flops 21 and 22 latch the input data in synchronization with the clock signal CK, if the alternating data that is inverted in synchronization with the rising edge of the clock signal CK is input to the data input terminal D of the flip-flop 21, the flip-flop The data output from the 22 data output terminals Q should also have the same waveform.

  FIG. 2 is a circuit diagram showing an internal circuit of a circuit block included in the circuit under test in FIG. The circuit block 23 includes a buffer circuit 231 that buffers the input signal IN of the circuit block, a first signal wiring 232 connected to the output of the buffer circuit 231, and an output signal of the buffer circuit 231 is a first signal wiring 232. A plurality of buffer circuits 233 input via the first signal wiring 232, a second signal wiring 234 having a portion arranged along the first signal wiring 232, and the input signal IN based on the control signal SB And a crosstalk control circuit 235 that selectively supplies the second signal wiring 234 in reverse phase. One of the plurality of buffer circuits 233 is used for outputting a signal from the circuit block 23, while the other buffer circuit 233 is for adding a capacity to the first signal wiring 232, It can be omitted.

  The crosstalk control circuit 235 has the same configuration as the crosstalk control circuit 153 of the circuit to be adjusted shown in FIG. 1, and includes an AND circuit 235a that obtains a logical product of the signal A and the control signal SB, and the signal B and the control. An inverting input AND circuit 235b that obtains the logical product of these signals by inverting the signal SB and an OR circuit 235c that obtains the logical sum of the output signal of the AND circuit 235a and the output signal of the AND circuit 235b are included.

  FIG. 3 is a truth table for explaining the operation of the crosstalk control circuit shown in FIGS. As the signals A and B, the input signal IN is used. The crosstalk control circuit 153 shown in FIG. 1 outputs the input signal IN as the output signal X when the determination signal SA is at the high level (1), and supplies this to the second signal wiring 152. As a result, in-phase crosstalk from the second signal wiring 152 to the first signal wiring 151 occurs, and the signal propagation delay time in the delay correction circuit 13 is minimized.

  Further, when the determination signal SA is at a low level (0), the crosstalk control circuit 153 outputs the signal IN bar as the output signal X by inverting the input signal IN, and this is output to the second signal wiring. 152. As a result, reverse-phase crosstalk from the second signal wiring 152 to the first signal wiring 151 occurs, and the signal propagation delay time in the delay correction circuit 13 is maximized.

  Similarly, the crosstalk control circuit 235 shown in FIG. 2 outputs the input signal IN as the output signal X when the control signal SB is at the high level (1), and supplies this to the second signal wiring 234. . As a result, in-phase crosstalk from the second signal wiring 234 to the first signal wiring 232 occurs, and the signal propagation delay time in the circuit block 23 is minimized.

  Further, the crosstalk control circuit 235 outputs the signal IN bar as the output signal X by inverting the input signal IN when the control signal SB is at the low level (0), and this is output to the second signal wiring. 234. As a result, reverse-phase crosstalk from the second signal wiring 234 to the first signal wiring 232 occurs, and the signal propagation delay time in the circuit block 23 is maximized.

  In general, in D flip-flops, the time required to latch input data in synchronization with the rising edge of the clock signal after the input data changes (setup time), and input in synchronization with the rising edge of the clock signal There is a time (hold time) during which input data must be held after data is latched.

  If the input data changes immediately after the rising edge of the clock signal, the hold time cannot be secured and a hold error occurs. On the other hand, if the input data changes immediately before the rising edge of the clock signal, the setup time cannot be secured and a setup error occurs. Therefore, when a hold error occurs, the delay time of the input data is increased to ensure the hold time, and when a setup error occurs, the delay time of the input data is decreased to ensure the setup time.

  Therefore, the determination circuit 30 shown in FIG. 1 changes the control signal SB to a high level or a low level, thereby maximizing or minimizing the signal propagation delay time in the circuit block 23 of the circuit under test 20. By detecting the coincidence between the state of the input signal input to the data input terminal D and the state of the output signal output from the data output terminal Q of the flip-flop 22, it is determined under which conditions the error increases. taking measurement.

  For example, when the error (setup error) increases when the signal propagation delay time in the circuit block 23 is maximized, the determination circuit 30 sets the determination signal SA to high level, and the holding circuit 40 holds this. . In the adjusted circuit 10, the crosstalk control circuit 153 outputs the input signal IN as the output signal X based on the determination signal SA, and supplies this to the second signal wiring 152. Thereby, in-phase crosstalk from the second signal wiring 152 to the first signal wiring 151 occurs, and the propagation delay time in the critical path decreases. As a result, setup errors can be reduced.

  On the other hand, when the error (hold error) increases when the signal propagation delay time in the circuit block 23 is minimized, the determination circuit 30 sets the determination signal SA to the low level, and the holding circuit 40 holds this. To do. In the adjusted circuit 10, the crosstalk control circuit 153 outputs the inverted input signal IN bar as the output signal X based on the determination signal SA, and supplies this to the second signal wiring 152. As a result, reverse-phase crosstalk from the second signal wiring 152 to the first signal wiring 151 occurs, and the propagation delay time in the critical path increases. As a result, hold errors can be reduced.

  The error measurement as described above is performed, for example, when a device in which a semiconductor integrated circuit is incorporated is turned on, and the holding circuit 40 holds the determination signal SA while the power is turned on. good. As the holding circuit 40, a flip-flop or a volatile memory (RAM or the like) can be used.

Alternatively, an error may be measured at the wafer test stage, and the determination signal SA obtained as a result may be held in a holding circuit 40 realized by a fuse or a non-volatile memory (E ² PROM or the like). In that case, the circuit under test 20 and the determination circuit 30 do not need to be formed in the same chip as the circuit to be adjusted 10. For example, they may be formed in a scribe region in the same wafer as the circuit to be adjusted 10. .

Next, the operation of the semiconductor integrated circuit according to the present embodiment will be described with reference to FIGS. FIG. 4 is a flowchart for explaining the operation of the semiconductor integrated circuit according to the first embodiment of the present invention.
First, in step S1, the determination circuit 30 determines the degree of influence of in-phase or reverse-phase crosstalk in the circuit block 23 of the circuit under test 20 on the circuit operation while changing the control signal SB to a high level or a low level. As a result, the determination signal SA is generated. Next, in step S2, the holding circuit 40 holds the determination signal SA.

  In step S <b> 3, the determination signal SA held by the holding circuit 40 is input to the delay correction circuit 15 of the adjusted circuit 10. Thus, in step S4, the crosstalk control circuit 153 included in the delay correction circuit 15 selects the polarity of the signal to be supplied to the second signal wiring 152 adjacent to the first signal wiring 151.

  If the influence on the circuit operation is large when the propagation delay time in the circuit block 23 is maximized, the crosstalk control circuit 153 supplies a positive-phase signal to the second signal wiring 152 in step S5. Reduce the propagation delay time in the critical path. As a result, in step S6, it is possible to suppress a timing error when an increase in delay occurs in a part other than the delay correction circuit 15.

  On the other hand, if the influence on the circuit operation is large when the propagation delay time in the circuit block 23 is minimized, the crosstalk control circuit 153 supplies a reverse phase signal to the second signal wiring 152 in step S7. Increase the propagation delay time in the critical path. As a result, in step S8, it is possible to suppress a timing error in the case where a decrease in delay occurs other than in the delay correction circuit 15.

  Next, a second embodiment of the present invention will be described. The second embodiment of the present invention is obtained by changing the crosstalk control circuits 153 and 235 in FIGS. 1 and 2 of the first embodiment, and the other configurations are the same as those of the first embodiment.

  FIG. 5 is a diagram showing a crosstalk control circuit used in the second embodiment of the present invention. The crosstalk control circuit 300 can receive 2-bit determination signals (or control signals) S1 and S2 and can set the output terminal to four states.

An input signal IN is supplied as a signal A to the crosstalk control circuit 300. The input signal IN is inverted by the crosstalk control circuit 300 to become a signal B. Further, the power supply potential V _DD is supplied as the signal C to the crosstalk control circuit 300, and the power supply potential V _SS (referred to as the ground potential in this embodiment) is supplied as the signal D.

  FIG. 6 is a truth table for explaining the operation of the crosstalk control circuit shown in FIG. The crosstalk control circuit 300 outputs the input signal IN as the output signal X when the determination signals (S1, S2) are (0, 0). By supplying this to the second signal wiring adjacent to the first signal wiring, in-phase crosstalk from the second signal wiring to the first signal wiring occurs, and signal propagation in the first signal wiring is caused. Delay time is minimized.

  On the other hand, the crosstalk control circuit 300 outputs the signal IN bar as the output signal X by inverting the input signal IN when the determination signals (S1, S2) are (0, 1). By supplying this to the second signal wiring adjacent to the first signal wiring, reverse-phase crosstalk from the second signal wiring to the first signal wiring occurs, and the signal in the first signal wiring Propagation delay time is maximized.

  The crosstalk control circuit 300 outputs a high level (1) signal as the output signal X when the determination signal (S1, S2) is (1, 0), and the determination signal (S1, S2) When (1, 1), a low level (0) signal is output as the output signal X. As a result, the second signal wiring adjacent to the first signal wiring works as a shield for the first signal wiring, and the signal propagation delay time in the first signal wiring becomes standard. Note that the crosstalk control circuit 300 may place the second signal wiring in a high impedance state instead of supplying a high level or low level signal to the second signal wiring.

  In this embodiment, by generating a 2-bit decision signal based on the result of measuring the signal propagation delay time while changing the control signal in four ways, the signal propagation delay time in the critical path is made four ways. Can be adjusted.

  Next, a third embodiment of the present invention will be described. The third embodiment of the present invention is obtained by changing the circuit under test 20 and the determination circuit 30 in FIG. 1 of the first embodiment, and other configurations are the same as those of the first embodiment.

  FIG. 7 is a block diagram showing a part of the configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. As shown in FIG. 7, the circuit under test 50 includes flip-flops 51 and 52 that operate in synchronization with the clock signal CK, and M circuit blocks connected in series between the flip-flop 51 and the flip-flop 52. 23. The circuit under test 60 includes flip-flops 61 and 62 that operate in synchronization with the clock signal CK, and M circuit blocks 23 connected in series between the flip-flop 61 and the flip-flop 62. Yes. Here, M is a natural number, and N is an integer larger than M. The reason for changing the number of circuit blocks 23 in the circuit under test 50 and the circuit under test 60 in this way is that by changing the propagation delay time in the vicinity of two types of propagation delay times that are greatly different in the circuit under test, respectively. This is for measuring a change in error in the circuit under test.

  In the circuit under test 50, a signal output from the data output terminal Q of the flip-flop 51 sequentially passes through the M circuit blocks 23 and is supplied from the last circuit block to the data input terminal D of the flip-flop 52. . Similarly, in the circuit under test 60, the signal output from the data output terminal Q of the flip-flop 61 passes through the N circuit blocks 23 in order, and passes from the last circuit block to the data input terminal D of the flip-flop 62. Supplied. A control signal SB for controlling the operation of the circuit block 23 is input from the determination circuit 70 to each circuit block 23.

  Since the flip-flops 51 and 52 latch input data in synchronization with the clock signal CK, if alternating data that is inverted in synchronization with the rising edge of the clock signal CK is input to the data input terminal D of the flip-flop 51, the flip-flop 52 The data output from the data output terminal Q should also have the same waveform. Similarly, since the flip-flops 61 and 62 latch input data in synchronization with the clock signal CK, if alternating data that is inverted in synchronization with the rising edge of the clock signal CK is input to the data input terminal D of the flip-flop 61, The data output from the data output terminal Q of the flip-flop 62 should also have the same waveform.

  The determination circuit 70 includes an exclusive OR circuit 71 for detecting a match between a signal input to the data input terminal D of the flip-flop 51 and a signal output from the data output terminal Q of the flip-flop 52, An exclusive OR circuit 72 for detecting a match between a signal input to the data input terminal D and a signal output from the data output terminal Q of the flip-flop 62, and an output signal of the exclusive OR circuit 71 and the exclusive OR circuit 72 And a comparison / determination unit 73 that outputs a determination signal SA based on the result of comparison with the output signal.

  Here, since the circuit under test 50 has a small number of circuit blocks 23 connected between the flip-flops 51 and 52 and a short propagation delay time, the signal propagation delay time in the circuit block 23 is minimized. It is suitable for measuring the hold error that sometimes increases. On the other hand, since the circuit under test 60 has a large number of circuit blocks 23 connected between the flip-flops 61 and 62 and a large propagation delay time, the signal propagation delay time in the circuit block 23 is maximized. Suitable for measuring setup errors that increase rapidly. When the determination circuit 70 compares the measurement results and a hold error is more likely to occur, the determination circuit 70 increases the propagation delay time in the critical path of the circuit to be adjusted 10 (see FIG. 1) and If this is likely to occur, the propagation delay time in the critical path of the circuit to be adjusted 10 is reduced.

  The present invention can be used in a general semiconductor integrated circuit or an ASIC such as a gate array or a standard cell designed by arranging and wiring a plurality of cells.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. The circuit diagram which shows the internal circuit of the circuit block of the to-be-measured circuit in FIG. A truth table for explaining the operation of the crosstalk control circuit shown in FIGS. FIG. 3 is a flowchart for explaining the operation of the semiconductor integrated circuit according to the first embodiment of the present invention. The figure which shows the crosstalk control circuit in the 2nd Embodiment of this invention. 6 is a truth table for explaining the operation of the crosstalk control circuit shown in FIG. The block diagram which shows the structure of the semiconductor integrated circuit which concerns on the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Circuit to be adjusted, 11, 14, 21, 22, 51, 52, 61, 62 Flip-flop, 12 Logic circuit, 13 Buffer circuit, 15 Delay correction circuit, 20 Circuit to be measured, 23 Circuit block, 30, 70 Determination circuit , 40 holding circuit, 71, 72 exclusive OR circuit, 73 comparison judgment unit, 151 first signal wiring, 152 second signal wiring, 153 crosstalk control circuit, 153a AND circuit, 153b inverting input AND circuit, 153c OR Circuit, 231 and 233 buffer circuit, 232 first signal wiring, 234 second signal wiring, 235 crosstalk control circuit, 235a AND circuit, 235b AND circuit of inverting input, 235c OR circuit

Claims (10)

A first circuit for buffering a signal input from the preceding circuit;
A first signal wiring for supplying an output signal of the first circuit to a circuit of a next stage;
A second signal wiring having a portion disposed along the first signal wiring;
A second circuit that selectively supplies a signal input to the first circuit to the second signal wiring in a normal phase or a reverse phase based on a determination signal;
Holding means for holding a determination signal to be supplied to the second circuit;
A semiconductor integrated circuit comprising:   The semiconductor integrated circuit according to claim 1, wherein the holding unit includes a fuse or a nonvolatile memory. A first circuit for buffering a signal input from the preceding circuit;
A first signal wiring for supplying an output signal of the first circuit to a circuit of a next stage;
A second signal wiring having a portion disposed along the first signal wiring;
A second circuit that selectively supplies a signal input to the first circuit to the second signal wiring in a normal phase or a reverse phase based on a determination signal;
A first flip-flop that latches a signal input to the data input terminal in synchronization with the clock signal, and outputs the latched signal from the data output terminal;
At least one circuit block connected between the data output terminal of the first flip-flop and the data input terminal of the second flip-flop, and buffering a signal input to the circuit block; And a third signal wiring connected to the output of the third circuit, a fourth signal wiring having a portion arranged along the third signal wiring, and a control signal, The circuit block including a fourth circuit that selectively supplies a signal input to the circuit block to the fourth signal wiring in a normal phase or a reverse phase;
A control signal to be supplied to the fourth circuit is generated, and positive-phase or negative-phase crosstalk from the fourth signal wiring to the third signal wiring affects the output signal of the second flip-flop. A determination circuit that generates a determination signal to be supplied to the second circuit by measuring an influence; and
A semiconductor integrated circuit comprising:   4. The semiconductor according to claim 3, wherein the determination circuit generates a determination signal based on a result of detecting a match between a state of an input signal of the first flip-flop and a state of an output signal of the second flip-flop. Integrated circuit. A first circuit for buffering a signal input from the preceding circuit;
A first signal wiring for supplying an output signal of the first circuit to a circuit of a next stage;
A second signal wiring having a portion disposed along the first signal wiring;
A second circuit that selectively supplies a signal input to the first circuit to the second signal wiring in a normal phase or a reverse phase based on a determination signal;
A first to a fourth flip-flop that latches a signal input to the data input terminal in synchronization with the clock signal and outputs the latched signal from the data output terminal;
M circuit blocks (M is a natural number) connected between the data output terminal of the first flip-flop and the data input terminal of the second flip-flop, and each circuit block is the circuit block. A third circuit for buffering a signal input to the first signal line; a third signal line connected to the output of the third circuit; and a fourth line having a portion disposed along the third signal line. The M circuits including a signal wiring and a fourth circuit that selectively supplies a signal input to the circuit block to the fourth signal wiring in a normal phase or a reverse phase based on a control signal. Block,
N circuit blocks connected between the data output terminal of the third flip-flop and the data input terminal of the fourth flip-flop (N is an integer greater than M), and each circuit block includes A fifth circuit for buffering a signal input to the circuit block; a fifth signal line connected to the output of the fifth circuit; and a portion disposed along the fifth signal line. A sixth circuit having a sixth signal wiring, and a sixth circuit that selectively supplies a signal input to the circuit block to the sixth signal wiring in a normal phase or a reverse phase based on a control signal, N circuit blocks;
A control signal to be supplied to the fourth and sixth circuits is generated, and a positive-phase or negative-phase crosstalk from the fourth signal wiring to the third signal wiring is output from the second flip-flop. Measuring the influence on the signal and the influence of the positive or negative phase crosstalk from the sixth signal wiring to the fifth signal wiring on the output signal of the fourth flip-flop, A determination circuit for generating a determination signal to be supplied to the second circuit;
A semiconductor integrated circuit comprising:   The determination circuit detects a match between the state of the input signal of the first flip-flop and the state of the output signal of the second flip-flop, the state of the input signal of the third flip-flop, and the 6. The semiconductor integrated circuit according to claim 5, wherein the determination signal is generated by comparing the result of detecting the coincidence with the state of the output signal of the fourth flip-flop.   When the determination signal is in the first state, the second circuit supplies the signal input to the first circuit to the second signal wiring in the positive phase, and the determination signal is in the second state. 7. The semiconductor integrated circuit according to claim 1, wherein a signal input to the first circuit is supplied to the second signal wiring in reverse phase.   The semiconductor integrated circuit according to claim 1, wherein the second circuit selectively supplies a power supply potential to the second signal wiring based on a determination signal.   The semiconductor integrated circuit according to claim 1, wherein the second circuit selectively places the second signal wiring in a high impedance state based on a determination signal.   The semiconductor integrated circuit according to claim 8, wherein the determination signal has a plurality of bits.

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