JP2005183706A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2005183706A
JP2005183706A JP2003423162A JP2003423162A JP2005183706A JP 2005183706 A JP2005183706 A JP 2005183706A JP 2003423162 A JP2003423162 A JP 2003423162A JP 2003423162 A JP2003423162 A JP 2003423162A JP 2005183706 A JP2005183706 A JP 2005183706A
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Japan
Prior art keywords
semiconductor chip
base member
wiring board
mounting
semiconductor device
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JP2003423162A
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Japanese (ja)
Inventor
Masaharu Imai
雅晴 今井
Kenichiro Matsuzaki
賢一郎 松崎
Kiyoaki Takahashi
喜代昭 高橋
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YASHIRO DENKI KK
Sumitomo Electric Industries Ltd
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YASHIRO DENKI KK
Sumitomo Electric Industries Ltd
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Priority to JP2003423162A priority Critical patent/JP2005183706A/en
Publication of JP2005183706A publication Critical patent/JP2005183706A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device such that a mount member for a semiconductor chip and a base member are formed in one member in extremely inexpensive integral structure and electrically connected with a low resistance value of only resistance that metal has. <P>SOLUTION: This semiconductor device is equipped with a wiring board 12 where wires are formed, the semiconductor chip 13 which is electrically connected to the wires, and the metallic base member 15 where the wiring board 12 and semiconductor chip 13 are mounted. A mount area 14 for the semiconductor chip 13 is formed integrally with the base member 15 to project to the mount surface side of the wiring board 12. The mount area 14 for the semiconductor chip is formed by pressing the base member 12 and a groove 20 indicating the position where the semiconductor chip is mounted is provided on the mount surface 14a of the mount area 14 for the semiconductor chip. Further, the mount area 14 for the semiconductor chip has corners rounded. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、配線基板、半導体素子を金属製のベース上に搭載実装してなる半導体装置に関する。   The present invention relates to a semiconductor device formed by mounting and mounting a wiring board and a semiconductor element on a metal base.

ミリ波乃至マイクロ波帯の高周波領域で使用される半導体素子、例えば、バイポーラトランジスタ、電界効果型トランジスタ（ＦＥＴ）等を実装する場合、単に半導体素子を接続しても、安定な電気的接続が必ずしも保証されているわけではない。また、ＦＥＴを超高周波で動作させる場合は、必然的に動作電流を大きくしなければならず、発熱も大きくなり、実装面においては発熱対策も重要になってくる。   When a semiconductor element used in a high frequency region of the millimeter wave to microwave band, for example, a bipolar transistor, a field effect transistor (FET) or the like is mounted, a stable electrical connection is not necessarily achieved even if the semiconductor element is simply connected. It is not guaranteed. In addition, when the FET is operated at an ultra-high frequency, the operating current must be increased inevitably, the heat generation becomes large, and a countermeasure against heat generation becomes important on the mounting surface.

従来、半導体素子（以下、半導体チップという）を熱伝導性及び導電性のよい搭載部材を介して金属製のベース部材に搭載するとともに、配線用の配線基板をベース部材に搭載してなる半導体装置が知られている（例えば、特許文献１及び特許文献２参照）。図４（Ａ）は特許文献１に開示の半導体装置の概略を説明する図、図４（Ｂ）は特許文献２に開示の半導体装置の概略を説明する図である。図中、１は半導体装置、２は配線基板、３は半導体チップ、４は搭載部材、４ａはチップ搭載面、４ｂは土台部、４ｃはチップ搭載部、５はベース部材、６は穴、７は開孔、８はボンディングワイヤ、９は導電性接着剤、１０は溝を示す。   2. Description of the Related Art Conventionally, a semiconductor device in which a semiconductor element (hereinafter referred to as a semiconductor chip) is mounted on a metal base member via a mounting member having good thermal conductivity and conductivity, and a wiring board for wiring is mounted on the base member. Is known (see, for example, Patent Document 1 and Patent Document 2). 4A is a diagram for explaining the outline of the semiconductor device disclosed in Patent Document 1, and FIG. 4B is a diagram for explaining the outline of the semiconductor device disclosed in Patent Document 2. FIG. In the figure, 1 is a semiconductor device, 2 is a wiring board, 3 is a semiconductor chip, 4 is a mounting member, 4a is a chip mounting surface, 4b is a base portion, 4c is a chip mounting portion, 5 is a base member, 6 is a hole, 7 Is an opening, 8 is a bonding wire, 9 is a conductive adhesive, and 10 is a groove.

図４（Ａ）において、半導体チップ３を搭載する搭載部材４は、熱伝導性及び導電性のよい銅などの金属から構成され、その表面に金メッキが施されている。搭載部材４の側面とベース部材５の穴６の内壁面とは同一形状で、搭載部材４はベース部材５に圧入により嵌め込まれる。ベース部材５の穴６の内壁面と搭載部材４の側面とは、密接して摩擦作用により接合されるので、締り嵌めの関係でベース部材５に対して確実に固定され、搭載部材４とベース部材５との間の熱抵抗を低減させることができるとされている。また、搭載部材４の側面とベース部材５の穴６は、角がない長円形状で形成することにより、密接度を一層高めることができ、ベース部材５に対する搭載部材４の固定を一層確実にすることができるともされている。   In FIG. 4A, the mounting member 4 on which the semiconductor chip 3 is mounted is made of a metal such as copper having good thermal conductivity and conductivity, and its surface is plated with gold. The side surface of the mounting member 4 and the inner wall surface of the hole 6 of the base member 5 have the same shape, and the mounting member 4 is fitted into the base member 5 by press fitting. Since the inner wall surface of the hole 6 of the base member 5 and the side surface of the mounting member 4 are intimately joined by frictional action, they are securely fixed to the base member 5 due to an interference fit, and the mounting member 4 and the base It is supposed that the thermal resistance between the members 5 can be reduced. Further, by forming the side surface of the mounting member 4 and the hole 6 of the base member 5 into an oval shape without corners, the closeness can be further increased, and the mounting member 4 can be more securely fixed to the base member 5. It can also be done.

搭載部材４の下面はベース部材５の下面とは面一にされ、搭載部材４の上面のチップ搭載面４ａは、配線基板２を搭載するためのベース部材５の上面から所定高さで突出し、配線基板２の上面と実質的に同じ高さになるように設定されている。配線基板２は、ベース部材５とほぼ同形の大きさの板状で、上面に配線導体が形成されており、ボンディングワイヤ８を介して半導体チップ３に信号伝送のための電気的接続が行なわれる。この配線基板２は、開孔７に搭載部材４を挿通させた状態で、ベース部材５の上面に搭載され、導電性接着剤９により接着固定される。配線基板２とベース部材５とを半田付けでなく導電性接着剤９により接着されているため、半田付に伴うフラックスの塗布や洗浄工程が不要となり、製造工程の簡略化が可能となるとされている。   The lower surface of the mounting member 4 is flush with the lower surface of the base member 5, and the chip mounting surface 4 a on the upper surface of the mounting member 4 protrudes from the upper surface of the base member 5 for mounting the wiring board 2 at a predetermined height, The height is set to be substantially the same as the upper surface of the wiring board 2. The wiring board 2 is a plate having a size substantially the same as that of the base member 5, and a wiring conductor is formed on the upper surface thereof, and electrical connection for signal transmission is performed to the semiconductor chip 3 via the bonding wires 8. . The wiring board 2 is mounted on the upper surface of the base member 5 in a state where the mounting member 4 is inserted through the opening 7, and is bonded and fixed by the conductive adhesive 9. Since the wiring board 2 and the base member 5 are bonded not by soldering but by the conductive adhesive 9, it is not necessary to apply a flux or perform a cleaning process accompanying soldering, and the manufacturing process can be simplified. Yes.

半導体チップ３は、例えば、半導体基板上にゲート領域、ソース領域及びドレイン領域を形成したＦＥＴなどの半導体素子である。この半導体チップ３は、搭載部材４のチップ搭載面４ａに載置され、金錫合金（ＡｕＳｎ）により半田付されている。チップ搭載面４ａには溝１０が設けられていて、半田付した際に、余分な半田材は溝１０に流れ込んで、半田材がチップ搭載面４ａの全面に広がるのを抑制している。この結果、半田材の影響を受けることなくワイヤボンディングを施すことが可能となって電気的な接続をより確実なものとすることができるとされている。   The semiconductor chip 3 is a semiconductor element such as an FET in which a gate region, a source region, and a drain region are formed on a semiconductor substrate. The semiconductor chip 3 is placed on the chip mounting surface 4a of the mounting member 4 and soldered with a gold-tin alloy (AuSn). A groove 10 is provided on the chip mounting surface 4a, and when soldering, excess solder material flows into the groove 10 to prevent the solder material from spreading over the entire surface of the chip mounting surface 4a. As a result, wire bonding can be performed without being affected by the solder material, and electrical connection can be made more reliable.

図４（Ｂ）は、図４（Ａ）の搭載部材４が、チップ搭載部４ｃと土台部４ｂとで構成されている点で異なる例である。土台部４ｂの高さは、ベース部材５の厚さと同じになるように設定され、土台部４ｂの外形は配線基板２の開孔７より大きくされている。ベース部材５の穴６は、土台部４ｂが図４（Ａ）の場合と同様に圧入により嵌め込まれて、密接固定するように形成されている。また、搭載部材４の土台部４ｂとベース部材５の穴６は、角がない長円形状で形成することにより、密接度を高めるようにもしている。   FIG. 4B is an example different in that the mounting member 4 of FIG. 4A is composed of a chip mounting portion 4c and a base portion 4b. The height of the base portion 4 b is set to be the same as the thickness of the base member 5, and the outer shape of the base portion 4 b is larger than the opening 7 of the wiring board 2. The hole 6 of the base member 5 is formed so that the base portion 4b is fitted and press-fitted in the same manner as in the case of FIG. Further, the base portion 4b of the mounting member 4 and the hole 6 of the base member 5 are formed in an oval shape having no corners, thereby increasing the closeness.

配線基板２は、導電性接着剤９によりベース部材５上に接着固定される。導電性接着剤９は、ベース部材５上のみならず、搭載部材４の土台部４ｂの上面まで塗布され、搭載部材４、ベース部材５及び配線基板２の裏面が電気的に導通されている。これにより、土台部４ｂとベース部材５の摩擦接触による抵抗値にバラツキがあっても、電気的に安定した導通を図ることができ、高周波に対して安定した特性を得ることができるとされている。
特開２００３−３１７４１号公報 特開２００３−２５８１４６号公報 The wiring board 2 is bonded and fixed on the base member 5 with the conductive adhesive 9. The conductive adhesive 9 is applied not only on the base member 5 but also to the upper surface of the base portion 4b of the mounting member 4, so that the mounting member 4, the base member 5 and the back surface of the wiring board 2 are electrically connected. Thereby, even if the resistance value due to the frictional contact between the base portion 4b and the base member 5 varies, it is possible to achieve electrically stable conduction and obtain stable characteristics against high frequencies. Yes.
JP 2003-31741 A JP 2003-258146 A

図４（Ａ）及び図４（Ｂ）のいずれの構成においても、搭載部材４とベース部材５は、圧入による嵌め込みで電気的な導通と機械的な固定が形成されている。しかしながら、良好な電気的な導通と機械的な固定を得るには、搭載部材４の嵌入部分（図４（Ｂ）においては土台部４ｂの部分）とベース部材５の穴６が高精度で形成されていることが必要である。このため、高精度の機械加工と組立てを必要とし、コスト的には不利となっている。また、図４（Ｂ）のように、搭載部材４とベース部材５を導電性接着剤９により導通させるとしても、導電性接着剤９は、金属導体と比べて導電率が必ずしもよいとは言えず、低抵抗接続に対しても十分ではない。   4A and 4B, the mounting member 4 and the base member 5 are electrically connected and mechanically fixed by being fitted by press-fitting. However, in order to obtain good electrical continuity and mechanical fixation, the fitting portion of the mounting member 4 (the portion of the base portion 4b in FIG. 4B) and the hole 6 of the base member 5 are formed with high accuracy. It is necessary to be. This requires high-precision machining and assembly, which is disadvantageous in terms of cost. 4B, even if the mounting member 4 and the base member 5 are electrically connected by the conductive adhesive 9, it can be said that the conductive adhesive 9 does not necessarily have a higher conductivity than the metal conductor. Neither is it sufficient for low resistance connections.

本発明は、上述した実情に鑑みてなされたもので、半導体チップの搭載部材とベース部材とが、極めて安価な一体構造で一部材で形成され、且つ、電気的にも金属の有する抵抗のみの低抵抗値で導通された構成の半導体装置の提供を課題とする。   The present invention has been made in view of the above-described circumstances, and the mounting member and the base member of the semiconductor chip are formed as a single member with an extremely inexpensive integrated structure, and only the resistance of the metal electrically is also included. It is an object of the present invention to provide a semiconductor device having a structure in which conduction is low.

本発明による半導体装置は、配線が形成された配線基板と、配線に電気的に接続される半導体チップと、配線基板と半導体チップが搭載される金属製のベース部材とを備えた半導体装置であって、半導体チップの搭載領域部は、配線基板の搭載面側に突き出るようにベース部材と一体に一部材で形成される。また、半導体チップの搭載領域部は、ベース部材をプレス成形して形成される。また、半導体チップの搭載領域部の搭載面には、半導体チップの搭載位置を示す溝が設けられる。さらに、半導体チップの搭載領域部は、角部が円弧状に形成されている。   A semiconductor device according to the present invention is a semiconductor device including a wiring board on which wiring is formed, a semiconductor chip electrically connected to the wiring, and a metal base member on which the wiring board and the semiconductor chip are mounted. Thus, the semiconductor chip mounting area is integrally formed with the base member so as to protrude toward the mounting surface of the wiring board. The semiconductor chip mounting area is formed by press-molding the base member. Further, a groove indicating the mounting position of the semiconductor chip is provided on the mounting surface of the mounting area portion of the semiconductor chip. Further, the corner area of the semiconductor chip mounting area is formed in an arc shape.

本発明の構成によれば、半導体チップの搭載領域部は金属製のベース部材と機械的な結合がない一体構造に一部材で形成されるため、結合のための機械加工や嵌め込み作業がなく、極めて安価に製造することができる。また、半導体チップの搭載領域部とベース部材は、一体構造で一部材であるため、導通抵抗が低く高周波に対する電気的特性の安定したものとすることができる。   According to the configuration of the present invention, the mounting region portion of the semiconductor chip is formed as a single member in an integrated structure that is not mechanically coupled to the metal base member, so there is no machining or fitting work for coupling, It can be manufactured at a very low cost. In addition, since the semiconductor chip mounting area and the base member are an integral structure and a single member, the conduction resistance is low and the electrical characteristics with respect to high frequencies can be stabilized.

図により本発明の実施の形態を説明する。図１は本発明による半導体装置の概略を説明する図、図２（Ａ）は半導体チップ搭載部の第１の実施形態を示す図、図２（Ｂ）は半導体チップ搭載部の第２の実施形態を示す図である。図中、１１は半導体装置、１２は配線基板、１３は半導体チップ、１４はチップ搭載部、１４ａはチップ搭載面、１５はベース部材、１６は凹部、１７は開孔、１８はボンディングワイヤ、１９は半田材、２０は溝、２１はカバー、２２は配線導体、２３は回路素子、２４は端子、２５はポッティング樹脂を示す。   Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram for explaining an outline of a semiconductor device according to the present invention, FIG. 2 (A) is a diagram showing a first embodiment of a semiconductor chip mounting portion, and FIG. 2 (B) is a second embodiment of a semiconductor chip mounting portion. It is a figure which shows a form. In the figure, 11 is a semiconductor device, 12 is a wiring board, 13 is a semiconductor chip, 14 is a chip mounting portion, 14a is a chip mounting surface, 15 is a base member, 16 is a recess, 17 is an opening, 18 is a bonding wire, 19 Is a solder material, 20 is a groove, 21 is a cover, 22 is a wiring conductor, 23 is a circuit element, 24 is a terminal, and 25 is a potting resin.

本発明による半導体装置１１は、図１に示すように配線基板１２とこれに接続される半導体チップ１３と、これらを搭載するベース部材１５を備えている。これをカバー２１により全体を覆い、外部接続用の端子２４等を接続し、通常ハイブリット集積回路モジュールとも言われている半導体装置である。また、発熱のある半導体チップ１３等に対しては導熱性の部材を用いてベース部材１５を通して放熱が行なわれるように構成される。更に、必要に応じて、モジュール全体は、放熱フィンを備えた放熱器等に搭載して使用される。   As shown in FIG. 1, the semiconductor device 11 according to the present invention includes a wiring board 12, a semiconductor chip 13 connected to the wiring board 12, and a base member 15 on which these are mounted. This is a semiconductor device which is generally referred to as a hybrid integrated circuit module by covering the whole with a cover 21 and connecting an external connection terminal 24 and the like. Further, the heat generating semiconductor chip 13 and the like are configured to radiate heat through the base member 15 using a heat conductive member. Furthermore, if necessary, the entire module is used by being mounted on a radiator or the like provided with a radiation fin.

配線基板１２は、エポキシ樹脂等の樹脂材料で多層に形成され基板上に、所定のパターンで配線導体２２を形成し、例えば、コンデンサ、抵抗、インダクタ等の複数の回路素子２３等を、別工程で予め３００℃程度で溶融するソルダリングにより搭載しておく。また、発熱のある半導体チップ等を搭載する部分には、開孔１７が設けられている。この配線基板１２には、外部回路への接続ための端子２４が接続され、また、必要に応じてスルホールを設けて基板下面側に接地接続のための導体が形成されている。   The wiring board 12 is formed in multiple layers of a resin material such as an epoxy resin, and the wiring conductor 22 is formed in a predetermined pattern on the board. For example, a plurality of circuit elements 23 such as capacitors, resistors, inductors, etc. In advance, it is mounted by soldering that melts at about 300 ° C. An opening 17 is provided in a portion where a semiconductor chip or the like that generates heat is mounted. A terminal 24 for connection to an external circuit is connected to the wiring board 12, and a through hole is provided if necessary, and a conductor for ground connection is formed on the lower surface side of the board.

ベース部材１５は、銅などの熱伝導性のよい金属板から形成され、配線基板１２を搭載し得る形状の外形を有し、両端に取付け部１５ａを設け、表面にニッケルメッキ等を施して外装ケースの底板としての機能を備えている。このベース部材１５は、例えば、幅２０ｍｍ、長さ５０ｍｍで厚さ２.０ｍｍの銅板を、プレス加工等で所望の位置に半導体チップ１３の搭載領域部（以下、チップ搭載部という）１４が突き出るように加工する。例えば、このプレス加工でチップ搭載部１４の厚さを元の厚さの２.０ｍｍとし、他の部分を１.２ｍｍ程度の薄さになるようにプレスする。これにより、チップ搭載部１４は、接合のための機械加工や嵌め込みを行なうことなく、ベース部材１５と一体に一部材で形成される。なお、取付け部１５ａ、或いは、カバー２１との結合用耳片等の形状、構造については任意であって、また、これらの加工形態も本発明の範囲外で、任意な形態で実施することができる。   The base member 15 is formed of a metal plate having good thermal conductivity such as copper, has an outer shape that allows the wiring board 12 to be mounted, is provided with attachment portions 15a at both ends, and is plated with nickel or the like on the surface. It functions as the bottom plate of the case. The base member 15 is, for example, a copper plate having a width of 20 mm, a length of 50 mm, and a thickness of 2.0 mm, and a mounting region portion (hereinafter referred to as a chip mounting portion) 14 of the semiconductor chip 13 protrudes to a desired position by pressing or the like. To be processed. For example, the thickness of the chip mounting portion 14 is set to 2.0 mm, which is the original thickness, and the other portions are pressed to a thickness of about 1.2 mm by this pressing. Thus, the chip mounting portion 14 is formed as a single member integrally with the base member 15 without performing machining or fitting for bonding. It should be noted that the shape and structure of the attachment portion 15a or the ear piece for coupling with the cover 21 are arbitrary, and these processing forms are also outside the scope of the present invention and can be carried out in any form. it can.

チップ搭載部１４の上面のチップ搭載面１４ａは、平坦度が要求されることから０.２ｍｍ程度研磨して、表面を平坦にする。この結果、厚さ１.８ｍｍとなり、他の平面部から０.６ｍｍ程度突き出たチップ搭載部１４が形成される。また、チップ搭載面１４ａには、半導体チップ１３を半田付けする際の搭載位置を示すマークとして、例えば、コ字状の溝２０を形成しておく。この溝２０は、刻印用の治具やポンチを用いて簡単に形成することができ、前記したコ字状以外にロ字状、Ｕ字状、単なるバー状などであってもよく、また、プレス加工の前に形成しておいてもよく、後であってもよいものである。   Since the chip mounting surface 14a on the upper surface of the chip mounting portion 14 requires flatness, the surface is polished by about 0.2 mm to flatten the surface. As a result, the chip mounting portion 14 having a thickness of 1.8 mm and projecting about 0.6 mm from the other flat portion is formed. Further, for example, a U-shaped groove 20 is formed on the chip mounting surface 14a as a mark indicating a mounting position when the semiconductor chip 13 is soldered. The groove 20 can be easily formed by using a stamping jig or punch, and may have a U shape, a U shape, a simple bar shape, etc. in addition to the U shape described above, It may be formed before or after the press working.

ベース部材１５は、プレス加工の後、全体を洗浄し全面にＮｉメッキを施し、更に全面にＡｕメッキを施すのが好ましい。しかし、本発明では、チップ搭載面１４ａ、或いは、ベース部材１５の裏面を除く上面側全体というように、限定的にＡｕメッキすることを排除するものではない。チップ搭載部１４は、ベース部材１５を機械的或いは化学的にエッチングすることによっても形成することができる。この場合、比較的精度のよいものを作製することができるが、時間がかかる上にコスト的に高いものとなる。この点、プレス加工によるものは、精度が落ちるが、比較的安価で生産性がよい。   It is preferable that the base member 15 is subjected to press working and then cleaned as a whole, Ni-plated on the entire surface, and Au-plated on the entire surface. However, the present invention does not exclude the limited Au plating such as the chip mounting surface 14a or the entire upper surface side excluding the back surface of the base member 15. The chip mounting portion 14 can also be formed by mechanically or chemically etching the base member 15. In this case, a relatively accurate product can be produced, but it takes time and is expensive. In this respect, the precision of press processing is relatively low, but the productivity is good.

Ａｕメッキが施されたチップ搭載面１４ａ上には、ＦＥＴ等の半導体チップ１３がダイボンディングされる。ダイボンディングに際しては、チップ搭載面１４ａ上にＡｕＳｎの半田粒を載せてベース部材１５の温度を３００℃に昇温し、半田粒を溶融して薄く展延させておき、その上に半導体チップ１３を搭載する。半導体チップ１３側の裏面にもＡｕメッキが施されているので、ベース部材１５上のＡｕメッキ層、ＡｕＳｎ半田層、半導体チップ１３の裏面のＡｕメッキが融合してダイボンディングされる。このとき、コ字状の溝２０をマークとして、その内側に半導体チップ１３をダイボンディングする。これにより、融けたＡｕＳｎ半田は、コ字状の溝２０の外には流れ出ないようにすることができる。   A semiconductor chip 13 such as an FET is die-bonded on the chip mounting surface 14a to which the Au plating is applied. At the time of die bonding, AuSn solder particles are placed on the chip mounting surface 14a, the temperature of the base member 15 is raised to 300 ° C., the solder particles are melted and spread thinly, and the semiconductor chip 13 is formed thereon. Is installed. Since Au plating is also applied to the back surface on the semiconductor chip 13 side, the Au plating layer, the AuSn solder layer on the base member 15 and the Au plating on the back surface of the semiconductor chip 13 are fused and die-bonded. At this time, the U-shaped groove 20 is used as a mark, and the semiconductor chip 13 is die-bonded on the inside. Thereby, the melted AuSn solder can be prevented from flowing out of the U-shaped groove 20.

チップ搭載部１４に半導体チップ１３が搭載された後、図２（Ａ）の第１の実施形態で示すように、ベース部材１５上に配線基板１２を搭載する。ベース部材１５の上面にプレス加工等に突き出るように形成されたチップ搭載部１４は、配線基板１２の開孔１７と一致するように設けられていて、これにより配線基板１２との位置合わせができる。チップ搭載面１４ａ上にダイボンディングされた半導体チップ１３は、配線基板１２の上面に露出する。なお、チップ搭載面１４ａの位置が、配線基板１２の面と同じである必要はなく、多少上下していても後に説明するワイヤボンディングの作業に支障をきたさない範囲であればよい。   After the semiconductor chip 13 is mounted on the chip mounting portion 14, the wiring board 12 is mounted on the base member 15 as shown in the first embodiment of FIG. The chip mounting portion 14 formed on the upper surface of the base member 15 so as to protrude by press working or the like is provided so as to coincide with the opening 17 of the wiring board 12, thereby enabling alignment with the wiring board 12. . The semiconductor chip 13 die-bonded on the chip mounting surface 14 a is exposed on the upper surface of the wiring substrate 12. Note that the position of the chip mounting surface 14a does not have to be the same as the surface of the wiring substrate 12, and may be in a range that does not hinder the wire bonding operation described later even if it is slightly moved up and down.

ベース部材１５には、チップ搭載部１４等の突き出る部分以外の部分に、溶融温度が比較的低い２２０℃位の半田シートを搭載しておき、ベース部材１５全体を２２０℃程度に昇温して溶融し、搭載された配線基板１２の下面側に形成された導体と電気的並びに機械的に接続して一体化する。ベース部材１５の全面に金メッキが施されていると、フラックスを使うことなく半田材１９で配線基板１２との接合が容易に行なうことが可能となる。   On the base member 15, a solder sheet having a relatively low melting temperature of 220 ° C. is mounted on a portion other than the protruding portion such as the chip mounting portion 14, and the entire base member 15 is heated to about 220 ° C. It fuses and integrates electrically and mechanically with the conductor formed in the lower surface side of the mounted wiring board 12. When the entire surface of the base member 15 is plated with gold, the solder material 19 can be easily joined to the wiring board 12 without using a flux.

配線基板１２に予め搭載されている回路素子２３は、３００℃程度の溶融温度が高いソルダリングで搭載しておくことにより、上述の半田シートの溶融接着による影響はない。しかし、配線基板１２をベース部材１５に搭載するのに、使用される周波数帯域、配線基板１２の配線導体の接地抵抗が特性的に許容される範囲においては、特許文献１又は２で開示の導電性接着剤を用いることもできる。   The circuit element 23 mounted in advance on the wiring board 12 is mounted by soldering having a high melting temperature of about 300.degree. However, in mounting the wiring board 12 on the base member 15, the frequency band used and the ground resistance of the wiring conductor of the wiring board 12 are within the range where characteristics are allowed in terms of conductivity. An adhesive can also be used.

ベース部材１５と一体に形成したチップ搭載部１４上に搭載された半導体チップ１３と、配線基板１２上の配線導体２２或いは導電パッドとは、ボンディングワイヤ１８により接続される。この場合、配線基板１２を搭載したベース部材１５全体を１５０℃程度に昇温させ、Ａｕワイヤーを用いたボールボンディングを行なう。なお、半導体チップ１３がＦＥＴである場合、接地電位に接続される端子（通常はソース端子）は、チップ搭載部１４のチップ搭載面１４ａに直接ボンディングされる。このため、上述したように、刻印等の方法によりコ字状に形成された位置決め用の溝２０を利用して、半導体チップ１３を接着固定するＡｕＳｎ半田がチップ搭載面１４ａの所定領域から展延しないようにするのが望ましい。   The semiconductor chip 13 mounted on the chip mounting portion 14 formed integrally with the base member 15 and the wiring conductor 22 or the conductive pad on the wiring substrate 12 are connected by a bonding wire 18. In this case, the entire base member 15 on which the wiring board 12 is mounted is heated to about 150 ° C., and ball bonding using Au wires is performed. When the semiconductor chip 13 is an FET, a terminal (usually a source terminal) connected to the ground potential is directly bonded to the chip mounting surface 14a of the chip mounting portion 14. Therefore, as described above, AuSn solder for bonding and fixing the semiconductor chip 13 is spread from a predetermined region of the chip mounting surface 14a by using the positioning groove 20 formed in a U shape by a method such as engraving. It is desirable not to do so.

また、半導体チップ１３は、例えば、ペア状態で搭載されることがある。この場合、半導体チップ１３の電極等が周囲環境に晒されるため半導体チップ表面を保護する必要がある。このため、ワイヤボンディング後にシリコン系のポッティング樹脂２５等で封止する。この工程を通常、ポッティングと言っている。ポッティングは、半導体チップ１３の表面のみならず、チップ搭載面１４ａ及び配線基板１２上のワイヤボンディングされた個所の全体を覆うように行なわれる。これにより、ポッティング樹脂２５は、半導体チップ表面の保護だけでなく、ボンディングワイヤ１８の機械的保護も兼ねることができる。   The semiconductor chip 13 may be mounted in a pair state, for example. In this case, since the electrodes of the semiconductor chip 13 are exposed to the surrounding environment, it is necessary to protect the surface of the semiconductor chip. For this reason, after wire bonding, sealing is performed with a silicon-based potting resin 25 or the like. This process is usually called potting. Potting is performed not only on the surface of the semiconductor chip 13 but also on the chip mounting surface 14a and the whole wire-bonded portion on the wiring substrate 12. Thereby, the potting resin 25 can serve not only for the protection of the surface of the semiconductor chip but also for the mechanical protection of the bonding wire 18.

次に、図２（Ｂ）により、第２の実施形態を説明する。図２（Ａ）では、チップ搭載部１４のような突き出る部分以外をプレス等で薄くすることで、結果的に凸部を形成（プレス加工分野で、フルピアス型とも言う）している。これに対し、図２（Ｂ）では、裏面側を押し出して表面側に凸部を形成する（プレス加工分野で、ハーフピアス型とも言う）例で、ベース部材１５の厚みを厚くできる構成の例である。   Next, a second embodiment will be described with reference to FIG. In FIG. 2 (A), a protruding portion is formed as a result by thinning a portion other than the protruding portion such as the chip mounting portion 14 with a press or the like (also referred to as a full piercing type in the press working field). On the other hand, in FIG. 2B, an example of a configuration in which the thickness of the base member 15 can be increased in an example in which the rear surface side is extruded to form a convex portion on the front surface side (also referred to as a half-piercing type in the press working field). It is.

銅板を用いた熱抵抗特性についてシミュレーションしてみると、図３のような結果が得られる。すなわち、銅板の厚さが厚くなればなるほど熱抵抗は小さくなる（放熱特性がよくなる）ことを示している。しかし、銅板の厚みが２.０ｍｍ前後を越えると、熱抵抗の低下の度合いは小さくなる。すなわち、銅板の厚みを２.０ｍｍより厚くしても、その厚くした効果が次第に希薄になってくる。図３からは、銅板の厚さが２.０ｍｍのときの熱抵抗が３.３５℃／Ｗ程度であるのに対し、銅板の厚さが１.２ｍｍの場合は３.４℃／Ｗ程度に上昇する。   When a simulation is performed on the thermal resistance characteristics using a copper plate, a result as shown in FIG. 3 is obtained. That is, as the thickness of the copper plate increases, the thermal resistance decreases (heat dissipation characteristics improve). However, when the thickness of the copper plate exceeds about 2.0 mm, the degree of decrease in thermal resistance becomes small. That is, even if the thickness of the copper plate is made thicker than 2.0 mm, the effect of increasing the thickness gradually diminishes. From FIG. 3, the thermal resistance when the thickness of the copper plate is 2.0 mm is about 3.35 ° C./W, whereas when the thickness of the copper plate is 1.2 mm, it is about 3.4 ° C./W. To rise.

半導体装置１１の熱源がチップ搭載部１４のような凸部である場合、図３の平板を想定して算出された熱抵抗とは多少異なる（差が少なくなる）ことが想定されるが、ベース部材１５が厚い方が好ましいことは明らかである。したがって、同じ材料で同じ厚さのベース部材を用いるとすれば、チップ搭載部１４をハーフピアス型で一体に形成することが好ましい。この場合、図２（Ａ）の例と同程度の突き出し高さ（０.６ｍｍ）を得るには、平坦度確保のための０.２ｍｍを削り分とすると、０.８ｍｍの突き出しを行なうこととなる。   When the heat source of the semiconductor device 11 is a convex portion such as the chip mounting portion 14, it is assumed that the thermal resistance is slightly different from the thermal resistance calculated assuming the flat plate of FIG. Obviously, the thicker member 15 is preferred. Accordingly, if base members having the same material and the same thickness are used, it is preferable to integrally form the chip mounting portion 14 in a half pierce type. In this case, in order to obtain a protrusion height (0.6 mm) similar to that in the example of FIG. 2 (A), a protrusion of 0.8 mm should be performed if 0.2 mm for securing flatness is taken as a part of the cut. It becomes.

この場合、ベース部材１５の裏面側に深さが０.８ｍｍの凹部１６が生じる。凹部１６が生じることにより、放熱器の熱伝導面で０.８ｍｍの空隙が生じ、熱抵抗を増加させる結果となる。しかし、凹部１６内にサーマルオイル（グリス等）を介在させることにより、実質上、これによる熱抵抗増加は抑制することができる。また、その他の面は、放熱器と密接に接触され、また、ベース部材１５の厚みが減じられていない分だけ、放熱器との間の熱抵抗が小さく放熱特性を向上させることができる。   In this case, a recess 16 having a depth of 0.8 mm is formed on the back side of the base member 15. As a result of the formation of the recess 16, a 0.8 mm gap is formed on the heat conducting surface of the radiator, resulting in an increase in thermal resistance. However, by increasing the thermal oil (such as grease) in the recess 16, an increase in the thermal resistance due to this can be substantially suppressed. In addition, the other surface is in close contact with the radiator, and the heat resistance between the radiator and the radiator is small as much as the thickness of the base member 15 is not reduced.

図２（Ｂ）のハーフピアス型と図２（Ａ）のフルピアス型では、ベース部材１５とチップ搭載部１４の一体形成方法が異なるだけで、他の構成については両者同じあるので、その他の構成については説明を省略する。なお、フルピアス型及びハーフピアス型のいずれの場合も、チップ搭載部１４は、角部が円弧状に形成されていることが好ましい。このため、平面形状として、楕円状、長円状、卵状というようなものになるが、角部が円弧状となっている限り、特に形状を限定するものではない。   The half piercing type in FIG. 2B and the full piercing type in FIG. 2A are the same except for the method of integrally forming the base member 15 and the chip mounting portion 14, and the other configurations are the same. Description of is omitted. In both cases of the full piercing type and the half piercing type, it is preferable that the chip mounting portion 14 has a corner portion formed in an arc shape. Therefore, the planar shape is an ellipse, an ellipse, or an egg, but the shape is not particularly limited as long as the corners are arcuate.

チップ搭載部１４の角部を円弧状とすることにより、プレス加工時に角部における応力集中を緩和することができる。この結果、チップ搭載部１４のチップ搭載面１４ａの平坦度確保のための調整厚さは、０.２ｍｍ程度とすることができる。   By making the corner portion of the chip mounting portion 14 into an arc shape, stress concentration at the corner portion can be reduced during press working. As a result, the adjustment thickness for ensuring the flatness of the chip mounting surface 14a of the chip mounting portion 14 can be set to about 0.2 mm.

本発明による半導体装置の概略を説明する図である。It is a figure explaining the outline of the semiconductor device by this invention. 本発明の実施形態を説明する図である。It is a figure explaining embodiment of this invention. 熱抵抗と銅板の厚さとの関係を説明する図である。It is a figure explaining the relationship between thermal resistance and the thickness of a copper plate. 従来の技術を説明する図である。It is a figure explaining the prior art.

符号の説明Explanation of symbols

１１…半導体装置、１２…配線基板、１３…半導体チップ、１４…チップ搭載部、１４ａ…チップ搭載面、１５…ベース部材、１６…凹部、１７…開孔、１８…ボンディングワイヤ、１９…半田材、２０…溝、２１…カバー、２２…配線導体、２３…回路素子、２４…端子、２５…ポッティング樹脂。 DESCRIPTION OF SYMBOLS 11 ... Semiconductor device, 12 ... Wiring board, 13 ... Semiconductor chip, 14 ... Chip mounting part, 14a ... Chip mounting surface, 15 ... Base member, 16 ... Recessed part, 17 ... Opening, 18 ... Bonding wire, 19 ... Solder material 20 ... groove, 21 ... cover, 22 ... wiring conductor, 23 ... circuit element, 24 ... terminal, 25 ... potting resin.

Claims (6)

配線が形成された配線基板と、前記配線に電気的に接続される半導体チップと、前記配線基板と前記半導体チップが搭載される金属製のベース部材とを備えた半導体装置であって、
前記半導体チップの搭載領域部は、前記配線基板の搭載面側に突き出るように前記ベース部材と一体に形成されていることを特徴とする半導体装置。 A semiconductor device comprising: a wiring board on which wiring is formed; a semiconductor chip electrically connected to the wiring; and a metal base member on which the wiring board and the semiconductor chip are mounted,
The semiconductor device is characterized in that the mounting area portion of the semiconductor chip is formed integrally with the base member so as to protrude to the mounting surface side of the wiring board. 前記半導体チップの搭載領域部は、前記ベース部材をプレス成形して形成されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the mounting region portion of the semiconductor chip is formed by press-molding the base member. 前記ベース部材の前記半導体チップの搭載領域部に対応する裏面部分が、窪んでいることを特徴とする請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein a back surface portion of the base member corresponding to the mounting region portion of the semiconductor chip is recessed. 前記半導体チップの搭載領域部の搭載面に、前記半導体チップの搭載位置を示す溝が設けられていることを特徴とする請求項１〜３のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a groove indicating a mounting position of the semiconductor chip is provided on a mounting surface of the mounting region portion of the semiconductor chip. 前記ベース部材の表面にＡｕメッキが施されていることを特徴とする請求項１〜４のいずれか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein a surface of the base member is Au plated. 前記半導体チップの搭載領域部は、角部が円弧状に形成されていることを特徴とする請求項２又は３に記載の半導体装置。   4. The semiconductor device according to claim 2, wherein the mounting area of the semiconductor chip has a corner formed in an arc shape. 5.
JP2003423162A 2003-12-19 2003-12-19 Semiconductor device Pending JP2005183706A (en)

Priority Applications (1)

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JP2003423162A JP2005183706A (en) 2003-12-19 2003-12-19 Semiconductor device

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JP2003423162A JP2005183706A (en) 2003-12-19 2003-12-19 Semiconductor device

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JP2005183706A true JP2005183706A (en) 2005-07-07

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