JP2005182825A - マルチスレッド式マイクロプロセッサのスレッドにまたがるアウト・オブ・オーダー命令ディスパッチ - Google Patents

マルチスレッド式マイクロプロセッサのスレッドにまたがるアウト・オブ・オーダー命令ディスパッチ Download PDF

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JP2005182825A
JP2005182825A JP2004367833A JP2004367833A JP2005182825A JP 2005182825 A JP2005182825 A JP 2005182825A JP 2004367833 A JP2004367833 A JP 2004367833A JP 2004367833 A JP2004367833 A JP 2004367833A JP 2005182825 A JP2005182825 A JP 2005182825A
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instruction
thread
threads
circuit
buffer
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JP2005182825A5 (enExample
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Simon S Moy
サイモン・エス・モイ
John E Lindholm
ジョン・エリック・リンドホルム
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Nvidia Corp
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Nvidia Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3888—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple threads [SIMT] in parallel

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP2004367833A 2003-12-18 2004-12-20 マルチスレッド式マイクロプロセッサのスレッドにまたがるアウト・オブ・オーダー命令ディスパッチ Pending JP2005182825A (ja)

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US10/742,514 US7310722B2 (en) 2003-12-18 2003-12-18 Across-thread out of order instruction dispatch in a multithreaded graphics processor

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JP2005182825A true JP2005182825A (ja) 2005-07-07
JP2005182825A5 JP2005182825A5 (enExample) 2007-12-27

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US (3) US7310722B2 (enExample)
EP (1) EP1555610B1 (enExample)
JP (1) JP2005182825A (enExample)
DE (1) DE602004026819D1 (enExample)
SG (1) SG112989A1 (enExample)
TW (1) TWI425418B (enExample)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810017B1 (ko) 2005-11-30 2008-03-07 인터내셔널 비지네스 머신즈 코포레이션 서로 다른 스레드에 대한 비대칭 하드웨어 멀티스레딩지원을 갖는 디지털 데이터 처리 장치
JP2009512917A (ja) * 2005-09-26 2009-03-26 イマジネイション テクノロジーズ リミテッド スケーラブルなマルチスレッド型メディア処理アーキテクチャ
JP2011505633A (ja) * 2007-11-30 2011-02-24 クゥアルコム・インコーポレイテッド グラフィックスシステムにおいて２次プロセッサを使用するための方法及びシステム
KR20120058605A (ko) * 2009-09-03 2012-06-07 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Ｇｐｕ 워크의 하드웨어 기반 스케쥴링
JP2013196300A (ja) * 2012-03-19 2013-09-30 Fujitsu Ltd 試験方法、試験装置及びプログラム
JP2013537993A (ja) * 2010-09-20 2013-10-07 クゥアルコム・インコーポレイテッド マルチプルプロセッサ計算プラットフォームにおけるプロセッサ間通信技法
JP2013250988A (ja) * 2013-07-22 2013-12-12 Panasonic Corp マルチスレッドプロセッサ
JP2014504416A (ja) * 2010-12-15 2014-02-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 組み合わせたｃｐｕ／ｇｐｕアーキテクチャシステムにおけるデバイスの発見およびトポロジーのレポーティング
WO2015155894A1 (ja) 2014-04-11 2015-10-15 株式会社Ｍｕｒａｋｕｍｏ プロセッサーおよび方法
KR20170015231A (ko) * 2015-07-31 2017-02-08 에이알엠 리미티드 그래픽 처리 시스템
KR20220026117A (ko) * 2020-08-25 2022-03-04 주식회사 엔씨소프트 게시판 서비스 제공 장치 및 방법, 게시판 서비스 요청 장치 및 방법

Families Citing this family (199)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7228486B2 (en) * 2003-07-17 2007-06-05 Lucent Technologies Inc. Methods and devices for randomizing burst errors
US8643659B1 (en) 2003-12-31 2014-02-04 3Dlabs Inc., Ltd. Shader with global and instruction caches
US7418576B1 (en) * 2004-11-17 2008-08-26 Nvidia Corporation Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operations
US7631130B2 (en) * 2005-02-04 2009-12-08 Mips Technologies, Inc Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
US7664936B2 (en) * 2005-02-04 2010-02-16 Mips Technologies, Inc. Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages
US7613904B2 (en) * 2005-02-04 2009-11-03 Mips Technologies, Inc. Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler
US7681014B2 (en) * 2005-02-04 2010-03-16 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US7506140B2 (en) * 2005-02-04 2009-03-17 Mips Technologies, Inc. Return data selector employing barrel-incrementer-based round-robin apparatus
US7752627B2 (en) * 2005-02-04 2010-07-06 Mips Technologies, Inc. Leaky-bucket thread scheduler in a multithreading microprocessor
US7657891B2 (en) * 2005-02-04 2010-02-02 Mips Technologies, Inc. Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
US7657883B2 (en) * 2005-02-04 2010-02-02 Mips Technologies, Inc. Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor
US7853777B2 (en) * 2005-02-04 2010-12-14 Mips Technologies, Inc. Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions
US7490230B2 (en) * 2005-02-04 2009-02-10 Mips Technologies, Inc. Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor
US7478276B2 (en) * 2005-02-10 2009-01-13 International Business Machines Corporation Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor
US7409589B2 (en) * 2005-05-27 2008-08-05 International Business Machines Corporation Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor
US7689735B2 (en) * 2005-10-03 2010-03-30 Arm Limited Instruction stream control
US7797467B2 (en) * 2005-11-01 2010-09-14 Lsi Corporation Systems for implementing SDRAM controllers, and buses adapted to include advanced high performance bus features
CN103646009B (zh) 2006-04-12 2016-08-17 索夫特机械公司 对载明并行和依赖运算的指令矩阵进行处理的装置和方法
KR100837400B1 (ko) * 2006-07-20 2008-06-12 삼성전자주식회사 멀티스레딩/비순차 병합 기법에 따라 처리하는 방법 및장치
US20080024510A1 (en) * 2006-07-27 2008-01-31 Via Technologies, Inc. Texture engine, graphics processing unit and video processing method thereof
US7990989B2 (en) * 2006-09-16 2011-08-02 Mips Technologies, Inc. Transaction selector employing transaction queue group priorities in multi-port switch
US7773621B2 (en) * 2006-09-16 2010-08-10 Mips Technologies, Inc. Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch
US7760748B2 (en) * 2006-09-16 2010-07-20 Mips Technologies, Inc. Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch
US7961745B2 (en) * 2006-09-16 2011-06-14 Mips Technologies, Inc. Bifurcated transaction selector supporting dynamic priorities in multi-port switch
US7859548B1 (en) 2006-10-19 2010-12-28 Nvidia Corporation Offloading cube map calculations to a shader
US7830387B2 (en) * 2006-11-07 2010-11-09 Microsoft Corporation Parallel engine support in display driver model
EP2523101B1 (en) 2006-11-14 2014-06-04 Soft Machines, Inc. Apparatus and method for processing complex instruction formats in a multi- threaded architecture supporting various context switch modes and virtualization schemes
US7958333B2 (en) 2007-05-30 2011-06-07 XMOS Ltd. Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected
EP2169538A4 (en) * 2007-06-20 2010-12-01 Fujitsu Ltd INSTRUCTIONS PROCESSOR
JP5177141B2 (ja) 2007-06-20 2013-04-03 富士通株式会社 演算処理装置、演算処理方法
US20090037918A1 (en) * 2007-07-31 2009-02-05 Advanced Micro Devices, Inc. Thread sequencing for multi-threaded processor with instruction cache
US8006073B1 (en) * 2007-09-28 2011-08-23 Oracle America, Inc. Simultaneous speculative threading light mode
US8073558B2 (en) 2007-10-05 2011-12-06 Honeywell International Inc Critical resource notification system and interface device
US8082420B2 (en) * 2007-10-24 2011-12-20 International Business Machines Corporation Method and apparatus for executing instructions
KR101335001B1 (ko) * 2007-11-07 2013-12-02 삼성전자주식회사 프로세서 및 인스트럭션 스케줄링 방법
US8174534B2 (en) * 2007-12-06 2012-05-08 Via Technologies, Inc. Shader processing systems and methods
TWI462011B (zh) * 2007-12-28 2014-11-21 Accton Technology Corp 程序之執行緒群組管理方法
US8086825B2 (en) 2007-12-31 2011-12-27 Advanced Micro Devices, Inc. Processing pipeline having stage-specific thread selection and method thereof
US7793080B2 (en) 2007-12-31 2010-09-07 Globalfoundries Inc. Processing pipeline having parallel dispatch and method thereof
US8015379B2 (en) 2008-02-01 2011-09-06 International Business Machines Corporation Wake-and-go mechanism with exclusive system bus response
US8516484B2 (en) 2008-02-01 2013-08-20 International Business Machines Corporation Wake-and-go mechanism for a data processing system
US8250396B2 (en) 2008-02-01 2012-08-21 International Business Machines Corporation Hardware wake-and-go mechanism for a data processing system
US8788795B2 (en) 2008-02-01 2014-07-22 International Business Machines Corporation Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors
US8341635B2 (en) 2008-02-01 2012-12-25 International Business Machines Corporation Hardware wake-and-go mechanism with look-ahead polling
US8171476B2 (en) 2008-02-01 2012-05-01 International Business Machines Corporation Wake-and-go mechanism with prioritization of threads
US8386822B2 (en) 2008-02-01 2013-02-26 International Business Machines Corporation Wake-and-go mechanism with data monitoring
US8127080B2 (en) 2008-02-01 2012-02-28 International Business Machines Corporation Wake-and-go mechanism with system address bus transaction master
US8612977B2 (en) 2008-02-01 2013-12-17 International Business Machines Corporation Wake-and-go mechanism with software save of thread state
US8725992B2 (en) 2008-02-01 2014-05-13 International Business Machines Corporation Programming language exposing idiom calls to a programming idiom accelerator
US8145849B2 (en) 2008-02-01 2012-03-27 International Business Machines Corporation Wake-and-go mechanism with system bus response
US8316218B2 (en) 2008-02-01 2012-11-20 International Business Machines Corporation Look-ahead wake-and-go engine with speculative execution
US8312458B2 (en) 2008-02-01 2012-11-13 International Business Machines Corporation Central repository for wake-and-go mechanism
US8732683B2 (en) 2008-02-01 2014-05-20 International Business Machines Corporation Compiler providing idiom to idiom accelerator
US8452947B2 (en) 2008-02-01 2013-05-28 International Business Machines Corporation Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms
US8640141B2 (en) 2008-02-01 2014-01-28 International Business Machines Corporation Wake-and-go mechanism with hardware private array
US8225120B2 (en) 2008-02-01 2012-07-17 International Business Machines Corporation Wake-and-go mechanism with data exclusivity
US8880853B2 (en) 2008-02-01 2014-11-04 International Business Machines Corporation CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock
US8082315B2 (en) 2009-04-16 2011-12-20 International Business Machines Corporation Programming idiom accelerator for remote update
US8145723B2 (en) 2009-04-16 2012-03-27 International Business Machines Corporation Complex remote update programming idiom accelerator
US8886919B2 (en) 2009-04-16 2014-11-11 International Business Machines Corporation Remote update programming idiom accelerator with allocated processor resources
US8230201B2 (en) 2009-04-16 2012-07-24 International Business Machines Corporation Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system
US9690625B2 (en) * 2009-06-16 2017-06-27 Oracle America, Inc. System and method for out-of-order resource allocation and deallocation in a threaded machine
JP5463076B2 (ja) * 2009-05-28 2014-04-09 パナソニック株式会社 マルチスレッドプロセッサ
US9137050B2 (en) 2009-07-17 2015-09-15 Honeywell International Inc. Demand response system incorporating a graphical processing unit
US8782190B2 (en) * 2009-07-17 2014-07-15 Honeywell International, Inc. Demand response management system
US8671167B2 (en) * 2009-07-17 2014-03-11 Honeywell International Inc. System for providing demand response services
US8676953B2 (en) 2009-07-17 2014-03-18 Honeywell International Inc. Use of aggregated groups for managing demand response resources
US8572230B2 (en) 2009-07-17 2013-10-29 Honeywell International Inc. System for using attributes to deploy demand response resources
US9818073B2 (en) 2009-07-17 2017-11-14 Honeywell International Inc. Demand response management system
US8667132B2 (en) 2009-07-17 2014-03-04 Honeywell International Inc. Arrangement for communication about and management of a resource using a mobile device
US8671191B2 (en) 2009-07-17 2014-03-11 Honeywell International Inc. Installation system for demand response resources
US9124535B2 (en) 2009-07-17 2015-09-01 Honeywell International Inc. System for using attributes to deploy demand response resources
US8607234B2 (en) * 2009-07-22 2013-12-10 Empire Technology Development, Llc Batch scheduling with thread segregation and per thread type marking caps
US8799912B2 (en) * 2009-07-22 2014-08-05 Empire Technology Development Llc Application selection of memory request scheduling
US8839255B2 (en) * 2009-07-23 2014-09-16 Empire Technology Development Llc Scheduling of threads by batch scheduling
JP2011065489A (ja) * 2009-09-17 2011-03-31 Sony Corp 情報処理装置、データ表示方法及びプログラム
US9189242B2 (en) * 2009-09-24 2015-11-17 Nvidia Corporation Credit-based streaming multiprocessor warp scheduling
US8370671B2 (en) * 2009-12-02 2013-02-05 International Business Machines Corporation Saving power by powering down an instruction fetch array based on capacity history of instruction buffer
TWI574155B (zh) * 2010-03-29 2017-03-11 威盛電子股份有限公司 資料預取方法、電腦程式產品以及微處理器
TWI474280B (zh) * 2010-04-21 2015-02-21 Via Tech Inc 增進繪圖處理單元之總處理量的方法與系統
US20110276784A1 (en) * 2010-05-10 2011-11-10 Telefonaktiebolaget L M Ericsson (Publ) Hierarchical multithreaded processing
US9058675B2 (en) 2010-05-29 2015-06-16 Intel Corporation Non-volatile storage for graphics hardware
CN102063289B (zh) * 2010-09-07 2013-10-16 中国科学技术大学 串行程序线程级推测执行能力评估方法和评估器
WO2012037491A2 (en) 2010-09-17 2012-03-22 Soft Machines, Inc. Single cycle multi-branch prediction including shadow cache for early far branch prediction
US8904115B2 (en) 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US8630744B2 (en) 2011-01-28 2014-01-14 Honeywell International Inc. Management and monitoring of automated demand response in a multi-site enterprise
US9153001B2 (en) 2011-01-28 2015-10-06 Honeywell International Inc. Approach for managing distribution of automated demand response events in a multi-site enterprise
US8626354B2 (en) 2011-01-28 2014-01-07 Honeywell International Inc. Approach for normalizing automated demand response events in energy management control systems
EP2689330B1 (en) 2011-03-25 2022-12-21 Intel Corporation Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
CN103547993B (zh) 2011-03-25 2018-06-26 英特尔公司 通过使用由可分割引擎实例化的虚拟核来执行指令序列代码块
CN108108188B (zh) 2011-03-25 2022-06-28 英特尔公司 用于通过使用由可分区引擎实例化的虚拟核来支持代码块执行的存储器片段
KR101639854B1 (ko) 2011-05-20 2016-07-14 소프트 머신즈, 인크. 복수의 엔진에 의해 명령어 시퀀스들의 실행을 지원하기 위한 상호접속 구조
CN107729267B (zh) 2011-05-20 2022-01-25 英特尔公司 资源的分散分配以及用于支持由多个引擎执行指令序列的互连结构
US9129060B2 (en) * 2011-10-13 2015-09-08 Cavium, Inc. QoS based dynamic execution engine selection
US9128769B2 (en) 2011-10-13 2015-09-08 Cavium, Inc. Processor with dedicated virtual functions and dynamic assignment of functional resources
DE102012220365A1 (de) * 2011-11-10 2013-05-16 Nvidia Corp. Aufgabe-Thread-Feld-Granularität-Ausführung-Präemption
CN102495726B (zh) * 2011-11-15 2015-05-20 无锡德思普科技有限公司 机会多线程方法及处理器
CN104040491B (zh) 2011-11-22 2018-06-12 英特尔公司 微处理器加速的代码优化器
KR101703401B1 (ko) 2011-11-22 2017-02-06 소프트 머신즈, 인크. 다중 엔진 마이크로프로세서용 가속 코드 최적화기
US20130141447A1 (en) * 2011-12-06 2013-06-06 Advanced Micro Devices, Inc. Method and Apparatus for Accommodating Multiple, Concurrent Work Inputs
US8933942B2 (en) 2011-12-08 2015-01-13 Advanced Micro Devices, Inc. Partitioning resources of a processor
US8949575B2 (en) 2011-12-14 2015-02-03 International Business Machines Corporation Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency
US8639882B2 (en) * 2011-12-14 2014-01-28 Nvidia Corporation Methods and apparatus for source operand collector caching
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
CN108681519B (zh) * 2012-03-30 2022-04-08 英特尔公司 用于从多线程发送请求至加速器的机制
US20140208074A1 (en) * 2012-03-30 2014-07-24 Boris A. Babayan Instruction scheduling for a multi-strand out-of-order processor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
JP5894496B2 (ja) * 2012-05-01 2016-03-30 ルネサスエレクトロニクス株式会社 半導体装置
US9875105B2 (en) 2012-05-03 2018-01-23 Nvidia Corporation Checkpointed buffer for re-entry from runahead
KR20130123645A (ko) * 2012-05-03 2013-11-13 삼성전자주식회사 그래픽 처리 장치를 위한 동적 로드 밸런싱 장치 및 방법
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US9645929B2 (en) 2012-09-14 2017-05-09 Nvidia Corporation Speculative permission acquisition for shared memory
US20140081704A1 (en) 2012-09-15 2014-03-20 Honeywell International Inc. Decision support system based on energy markets
US11013993B2 (en) 2012-09-28 2021-05-25 Sony Interactive Entertainment Inc. Pre-loading translated code in cloud based emulated applications
US9849372B2 (en) * 2012-09-28 2017-12-26 Sony Interactive Entertainment Inc. Method and apparatus for improving efficiency without increasing latency in emulation of a legacy application title
US10001996B2 (en) 2012-10-26 2018-06-19 Nvidia Corporation Selective poisoning of data during runahead
US9740553B2 (en) 2012-11-14 2017-08-22 Nvidia Corporation Managing potentially invalid results during runahead
TWI462020B (zh) * 2012-11-28 2014-11-21 Htc Corp 執行緒管理方法及其電子裝置
US9389850B2 (en) 2012-11-29 2016-07-12 Honeywell International Inc. System and approach to manage versioning of field devices in a multi-site enterprise
US9632976B2 (en) 2012-12-07 2017-04-25 Nvidia Corporation Lazy runahead operation for a microprocessor
US9569214B2 (en) 2012-12-27 2017-02-14 Nvidia Corporation Execution pipeline data forwarding
US20140189310A1 (en) 2012-12-27 2014-07-03 Nvidia Corporation Fault detection in instruction translations
US9823931B2 (en) 2012-12-28 2017-11-21 Nvidia Corporation Queued instruction re-dispatch after runahead
US9547602B2 (en) 2013-03-14 2017-01-17 Nvidia Corporation Translation lookaside buffer entry systems and methods
US10108424B2 (en) 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
WO2014150806A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for populating register view data structure by using register template snapshots
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9442755B2 (en) * 2013-03-15 2016-09-13 Nvidia Corporation System and method for hardware scheduling of indexed barriers
US9569216B2 (en) 2013-03-15 2017-02-14 Soft Machines, Inc. Method for populating a source view data structure by using register template snapshots
WO2014150971A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for dependency broadcasting through a block organized source view data structure
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
KR101708591B1 (ko) 2013-03-15 2017-02-20 소프트 머신즈, 인크. 블록들로 그룹화된 멀티스레드 명령어들을 실행하기 위한 방법
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
WO2014150991A1 (en) 2013-03-15 2014-09-25 Soft Machines, Inc. A method for implementing a reduced size register view data structure in a microprocessor
EP2972836B1 (en) 2013-03-15 2022-11-09 Intel Corporation A method for emulating a guest centralized flag architecture by using a native distributed flag architecture
CN104063270B (zh) * 2013-03-22 2017-06-23 斯克林集团公司 加标签方法、加标签装置以及缺陷检查装置
JP6152034B2 (ja) * 2013-03-22 2017-06-21 株式会社Ｓｃｒｅｅｎホールディングス ラベリング方法、ラベリング装置および欠陥検査装置
US9792252B2 (en) 2013-05-31 2017-10-17 Microsoft Technology Licensing, Llc Incorporating a spatial array into one or more programmable processor cores
US9691076B2 (en) 2013-07-11 2017-06-27 Honeywell International Inc. Demand response system having a participation predictor
US10346931B2 (en) 2013-07-11 2019-07-09 Honeywell International Inc. Arrangement for communicating demand response resource incentives
US9989937B2 (en) 2013-07-11 2018-06-05 Honeywell International Inc. Predicting responses of resources to demand response signals and having comfortable demand responses
US9582280B2 (en) 2013-07-18 2017-02-28 Nvidia Corporation Branching to alternate code based on runahead determination
US10062135B2 (en) * 2013-07-31 2018-08-28 National Technology & Engineering Solutions Of Sandia, Llc Graphics processing unit management system for computed tomography
KR20150019349A (ko) * 2013-08-13 2015-02-25 삼성전자주식회사 다중 쓰레드 실행 프로세서 및 이의 동작 방법
US20150074353A1 (en) * 2013-09-06 2015-03-12 Futurewei Technologies, Inc. System and Method for an Asynchronous Processor with Multiple Threading
US9417920B2 (en) * 2013-10-04 2016-08-16 Freescale Semiconductor, Inc. Method and apparatus for dynamic resource partition in simultaneous multi-thread microprocessor
GB2521155B (en) * 2013-12-10 2021-06-02 Advanced Risc Mach Ltd Configuring thread scheduling on a multi-threaded data processing apparatus
GB2521151B (en) 2013-12-10 2021-06-02 Advanced Risc Mach Ltd Configurable thread ordering for a data processing apparatus
US9589311B2 (en) * 2013-12-18 2017-03-07 Intel Corporation Independent thread saturation of graphics processing units
US9471307B2 (en) * 2014-01-03 2016-10-18 Nvidia Corporation System and processor that include an implementation of decoupled pipelines
US20150220343A1 (en) * 2014-02-05 2015-08-06 Mill Computing, Inc. Computer Processor Employing Phases of Operations Contained in Wide Instructions
US9558000B2 (en) 2014-02-06 2017-01-31 Optimum Semiconductor Technologies, Inc. Multithreading using an ordered list of hardware contexts
US9766894B2 (en) 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Method and apparatus for enabling a processor to generate pipeline control signals
US9665078B2 (en) 2014-03-25 2017-05-30 Honeywell International Inc. System for propagating messages for purposes of demand response
US20160364237A1 (en) * 2014-03-27 2016-12-15 Intel Corporation Processor logic and method for dispatching instructions from multiple strands
US10902545B2 (en) * 2014-08-19 2021-01-26 Apple Inc. GPU task scheduling
US9824414B2 (en) 2014-12-09 2017-11-21 Intel Corporation Thread dispatching for graphics processors
US10346170B2 (en) 2015-05-05 2019-07-09 Intel Corporation Performing partial register write operations in a processor
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US9720693B2 (en) 2015-06-26 2017-08-01 Microsoft Technology Licensing, Llc Bulk allocation of instruction blocks to a processor instruction window
GB2540543B (en) * 2015-07-20 2020-03-11 Advanced Risc Mach Ltd Graphics processing
TWI564807B (zh) * 2015-11-16 2017-01-01 財團法人工業技術研究院 排程方法及應用其的處理裝置
WO2017100078A1 (en) 2015-12-08 2017-06-15 Rambus Inc. Low power signaling interface
US9977677B2 (en) 2016-04-07 2018-05-22 International Business Machines Corporation Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port
US20170337062A1 (en) * 2016-05-19 2017-11-23 Centipede Semi Ltd. Single-thread speculative multi-threading
US10410097B2 (en) 2016-06-06 2019-09-10 Mutualink, Inc. System and method for distributed intelligent pattern recognition
US10541556B2 (en) 2017-04-27 2020-01-21 Honeywell International Inc. System and approach to integrate and manage diverse demand response specifications for multi-site enterprises
WO2019089816A2 (en) 2017-10-31 2019-05-09 Micron Technology, Inc. System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
US11119782B2 (en) 2018-05-07 2021-09-14 Micron Technology, Inc. Thread commencement using a work descriptor packet in a self-scheduling processor
US11119972B2 (en) 2018-05-07 2021-09-14 Micron Technology, Inc. Multi-threaded, self-scheduling processor
US11074078B2 (en) 2018-05-07 2021-07-27 Micron Technology, Inc. Adjustment of load access size by a multi-threaded, self-scheduling processor to manage network congestion
US11126587B2 (en) 2018-05-07 2021-09-21 Micron Technology, Inc. Event messaging in a system having a self-scheduling processor and a hybrid threading fabric
US11513839B2 (en) 2018-05-07 2022-11-29 Micron Technology, Inc. Memory request size management in a multi-threaded, self-scheduling processor
US11513837B2 (en) 2018-05-07 2022-11-29 Micron Technology, Inc. Thread commencement and completion using work descriptor packets in a system having a self-scheduling processor and a hybrid threading fabric
US11513838B2 (en) 2018-05-07 2022-11-29 Micron Technology, Inc. Thread state monitoring in a system having a multi-threaded, self-scheduling processor
US11513840B2 (en) 2018-05-07 2022-11-29 Micron Technology, Inc. Thread creation on local or remote compute elements by a multi-threaded, self-scheduling processor
US11157286B2 (en) 2018-05-07 2021-10-26 Micron Technology, Inc. Non-cached loads and stores in a system having a multi-threaded, self-scheduling processor
US11132233B2 (en) 2018-05-07 2021-09-28 Micron Technology, Inc. Thread priority management in a multi-threaded, self-scheduling processor
US11068305B2 (en) 2018-05-07 2021-07-20 Micron Technology, Inc. System call management in a user-mode, multi-threaded, self-scheduling processor
US10796472B2 (en) * 2018-06-30 2020-10-06 Intel Corporation Method and apparatus for simultaneously executing multiple contexts on a graphics engine
US10721172B2 (en) 2018-07-06 2020-07-21 Marvell Asia Pte, Ltd. Limiting backpressure with bad actors
US11003457B2 (en) * 2019-01-23 2021-05-11 Mediatek Inc. Power-saving mechanism for memory sub-system in pipelined processor
US11321123B2 (en) * 2019-11-21 2022-05-03 International Business Machines Corporation Determining an optimum number of threads to make available per core in a multi-core processor complex to executive tasks
US10891708B1 (en) 2019-11-25 2021-01-12 Arm Limited Shader program execution in graphics processing
US20210294673A1 (en) * 2020-03-19 2021-09-23 Nvidia Corporation Techniques for orchestrating stages of thread synchronization
US11775185B2 (en) * 2020-09-17 2023-10-03 Micron Technology, Inc. Power budget arbitration for multiple concurrent access operations in a memory device
US20240403056A1 (en) * 2023-06-05 2024-12-05 Advanced Micro Devices, Inc. Shader launch scheduling optimization
US20250307014A1 (en) * 2024-04-02 2025-10-02 Tenstorrent USA, Inc. Processor with dispatch buffer allocation affinity credit adjustment
US12436770B1 (en) * 2024-06-13 2025-10-07 SiFive, Inc. Window-based control for instruction issue in an out-of-order processor

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4834447A (enExample) * 1971-08-31 1973-05-18
JPH05224923A (ja) * 1991-11-22 1993-09-03 Internatl Business Mach Corp <Ibm> ハイブリッドパイプライン接続プロセッサおよびその処理方法
JPH0644089A (ja) * 1992-05-18 1994-02-18 Matsushita Electric Ind Co Ltd 情報処理装置
US6073159A (en) * 1996-12-31 2000-06-06 Compaq Computer Corporation Thread properties attribute vector based thread selection in multithreading processor
WO2001077821A1 (en) * 2000-03-30 2001-10-18 Intel Corporation Method and apparatus for writing instructions into a buffer queue including overwriting invalid entries
WO2002006959A1 (en) * 2000-07-14 2002-01-24 Clearwater Networks, Inc. Instruction fetch and dispatch in multithreaded system
WO2002019101A1 (en) * 2000-08-31 2002-03-07 Hajime Seki Computer system
JP2002268878A (ja) * 2001-03-07 2002-09-20 Hitachi Ltd スレッド間優先度可変プロセッサ
JP2002342163A (ja) * 2001-05-15 2002-11-29 Fujitsu Ltd マルチスレッドプロセッサ用キャッシュ制御方式
US6493741B1 (en) * 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
JP2003516570A (ja) * 1999-12-09 2003-05-13 インテル・コーポレーション マルチスレッド・プロセッサ内の複数のスレッドに入り、出る方法と装置
WO2003058447A2 (en) * 2001-12-31 2003-07-17 Intel Corporation A method and apparatus for suspending execution of a thread until a specified memory access occurs
JP2003223359A (ja) * 2002-01-29 2003-08-08 Fujitsu Ltd 演算処理装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3725871A (en) * 1971-02-11 1973-04-03 Honeywell Inf Systems Multi function polling technique
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
GB2287111B (en) * 1994-03-01 1998-08-05 Intel Corp Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer
JPH08320797A (ja) * 1995-05-24 1996-12-03 Fuji Xerox Co Ltd プログラム制御システム
US6010476A (en) * 1996-12-02 2000-01-04 Angiotrax, Inc. Apparatus for performing transmyocardial revascularization
US6689103B1 (en) * 1999-05-07 2004-02-10 Scimed Life System, Inc. Injection array apparatus and method
US6574725B1 (en) * 1999-11-01 2003-06-03 Advanced Micro Devices, Inc. Method and mechanism for speculatively executing threads of instructions
US7015930B2 (en) * 2003-08-01 2006-03-21 Ati Technologies Inc. Method and apparatus for interpolating pixel parameters based on a plurality of vertex values
US6897871B1 (en) 2003-11-20 2005-05-24 Ati Technologies Inc. Graphics processing architecture employing a unified shader
US7418576B1 (en) * 2004-11-17 2008-08-26 Nvidia Corporation Prioritized issuing of operation dedicated execution unit tagged instructions from multiple different type threads performing different set of operations
US20070030280A1 (en) * 2005-08-08 2007-02-08 Via Technologies, Inc. Global spreader and method for a parallel graphics processor

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4834447A (enExample) * 1971-08-31 1973-05-18
JPH05224923A (ja) * 1991-11-22 1993-09-03 Internatl Business Mach Corp <Ibm> ハイブリッドパイプライン接続プロセッサおよびその処理方法
JPH0644089A (ja) * 1992-05-18 1994-02-18 Matsushita Electric Ind Co Ltd 情報処理装置
US6073159A (en) * 1996-12-31 2000-06-06 Compaq Computer Corporation Thread properties attribute vector based thread selection in multithreading processor
US6493741B1 (en) * 1999-10-01 2002-12-10 Compaq Information Technologies Group, L.P. Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit
JP2003516570A (ja) * 1999-12-09 2003-05-13 インテル・コーポレーション マルチスレッド・プロセッサ内の複数のスレッドに入り、出る方法と装置
WO2001077821A1 (en) * 2000-03-30 2001-10-18 Intel Corporation Method and apparatus for writing instructions into a buffer queue including overwriting invalid entries
WO2002006959A1 (en) * 2000-07-14 2002-01-24 Clearwater Networks, Inc. Instruction fetch and dispatch in multithreaded system
JP2004518183A (ja) * 2000-07-14 2004-06-17 クリアウオーター・ネツトワークス・インコーポレイテツド マルチスレッド・システムにおける命令のフェッチとディスパッチ
WO2002019101A1 (en) * 2000-08-31 2002-03-07 Hajime Seki Computer system
JP2002268878A (ja) * 2001-03-07 2002-09-20 Hitachi Ltd スレッド間優先度可変プロセッサ
JP2002342163A (ja) * 2001-05-15 2002-11-29 Fujitsu Ltd マルチスレッドプロセッサ用キャッシュ制御方式
WO2003058447A2 (en) * 2001-12-31 2003-07-17 Intel Corporation A method and apparatus for suspending execution of a thread until a specified memory access occurs
JP2006500639A (ja) * 2001-12-31 2006-01-05 インテル コーポレイション 指定されたメモリアクセスが発生するまでスレッドの実行をサスペンドする方法及び装置
JP2003223359A (ja) * 2002-01-29 2003-08-08 Fujitsu Ltd 演算処理装置

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009512917A (ja) * 2005-09-26 2009-03-26 イマジネイション テクノロジーズ リミテッド スケーラブルなマルチスレッド型メディア処理アーキテクチャ
KR100810017B1 (ko) 2005-11-30 2008-03-07 인터내셔널 비지네스 머신즈 코포레이션 서로 다른 스레드에 대한 비대칭 하드웨어 멀티스레딩지원을 갖는 디지털 데이터 처리 장치
JP2011505633A (ja) * 2007-11-30 2011-02-24 クゥアルコム・インコーポレイテッド グラフィックスシステムにおいて２次プロセッサを使用するための方法及びシステム
US8922565B2 (en) 2007-11-30 2014-12-30 Qualcomm Incorporated System and method for using a secondary processor in a graphics system
KR101587201B1 (ko) 2009-09-03 2016-01-20 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Ｇｐｕ 워크의 하드웨어 기반 스케쥴링
KR20120058605A (ko) * 2009-09-03 2012-06-07 어드밴스드 마이크로 디바이시즈, 인코포레이티드 Ｇｐｕ 워크의 하드웨어 기반 스케쥴링
JP2013504127A (ja) * 2009-09-03 2013-02-04 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Ｇｐｕワークのハードウエアベースでのスケジューリング
US9645866B2 (en) 2010-09-20 2017-05-09 Qualcomm Incorporated Inter-processor communication techniques in a multiple-processor computing platform
JP2013537993A (ja) * 2010-09-20 2013-10-07 クゥアルコム・インコーポレイテッド マルチプルプロセッサ計算プラットフォームにおけるプロセッサ間通信技法
US9626234B2 (en) 2010-09-20 2017-04-18 Qualcomm Incorporated Inter-processor communication techniques in a multiple-processor computing platform
JP2014504416A (ja) * 2010-12-15 2014-02-20 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 組み合わせたｃｐｕ／ｇｐｕアーキテクチャシステムにおけるデバイスの発見およびトポロジーのレポーティング
JP2013196300A (ja) * 2012-03-19 2013-09-30 Fujitsu Ltd 試験方法、試験装置及びプログラム
JP2013250988A (ja) * 2013-07-22 2013-12-12 Panasonic Corp マルチスレッドプロセッサ
WO2015155894A1 (ja) 2014-04-11 2015-10-15 株式会社Ｍｕｒａｋｕｍｏ プロセッサーおよび方法
KR20170015231A (ko) * 2015-07-31 2017-02-08 에이알엠 리미티드 그래픽 처리 시스템
KR102676410B1 (ko) 2015-07-31 2024-06-19 에이알엠 리미티드 그래픽 처리 시스템
KR20220026117A (ko) * 2020-08-25 2022-03-04 주식회사 엔씨소프트 게시판 서비스 제공 장치 및 방법, 게시판 서비스 요청 장치 및 방법
KR102449109B1 (ko) * 2020-08-25 2022-09-29 주식회사 엔씨소프트 게시판 서비스 제공 장치 및 방법, 게시판 서비스 요청 장치 및 방법

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