JP2005182312A - Device control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quicken device control processing by eliminating or decreasing the WAIT of a CPU at the time of controlling a device control circuit. <P>SOLUTION: Device control circuits 21 to 2N control a slave control target circuit 8 based on control data received by polling from a CPU 10. Then, FIFO memories 5 and 6 write and store the control data corresponding to the address of the same device and the address of the device based on a write enable signal WE from the CPU, and reads the stored data to the control target circuit based on a data request signal from the control target circuit. An up-down counter 7 counts up according to the writing in the FIFO memory, and counts down according to the data request signal from the device, and outputs the count value as a response signal to the CPU. When a response signal ACK is contents to notify write control stop, the output of the write enable signal WE is stopped. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a device control circuit that controls a device based on control data received from a CPU and outputs status data from the device to the CPU.

  An example of a conventional device control apparatus of this type is shown in FIG. 6 (not related to the literature known invention). This device control apparatus comprises a CPU 10 and n device control circuits 31 to 3n. The CPU 10 and n device control circuits 31 to 3n include a data bus DBU, an address bus ABU, a write enable signal WE and Multiple connections are made by the read enable signal RE.

  The CPU 10 polls the device control circuits 31 to 3n by sequentially sending addresses for designating the device control circuits 31 to 3n together with the control data. The device control circuits 31 to 3n control non-intelligent devices (not shown) such as subordinate optical amplifiers based on control data received from the CPU. Also, when status data indicating the status of the device is received from the device, it is read out to the CPU 10. Note that the reference numeral 30 is used in the following when describing the device control circuits 31 to 3n in general.

  The data bus DBU is used by the CPU 10 to write control data to the device control circuit 30 or read status data from the device control circuit 30. The address bus ABU is used to select the device control circuit 30 that the CPU 10 accesses. The write enable signal WE is a timing for writing control data to the device control circuit 30, and the read enable signal RE is a timing for reading state data from the device control circuit 30.

  FIG. 7 shows the write control timing of control data to the device control circuits 31, 32, and 33 shown in FIG. When the device control circuits 31, 32, and 33 constantly monitor the address bus ABU and detect an address value indicating its own circuit, the control data 31, 32, and 33 on the data bus DBU at the falling change point of the write enable signal WE. Capture. The device control circuits 31, 32, and 33 control the subordinate devices based on the control data 31, 32, and 33.

  FIG. 8 shows the timing for reading the status data from the device control circuits 31, 32, and 33 shown in FIG. When the device control circuits 31, 32, and 33 constantly monitor the address bus ABU and detect an address value indicating its own circuit, the device control circuits 31, 32, and 33 output the output data 31, 32, and 33 to the data bus DBU while the read enable signal RE is at the LOW level. Output to data bus DBU. The CPU 10 can take in data on the data bus DBU as status data and detect the status of the device control circuits 31, 32, and 33.

  FIG. 9 and FIG. 10 show timings when write control and read control are continuously performed on the device control circuit 30 shown in FIG.

  FIG. 9 shows a case where data processing in the device based on the control data 31 is fast and the next control is possible without WAIT. In this case, since the status data 31 can be read in the next cycle after the control by the control data 31 for the device control circuit 31 is completed, it is possible to immediately shift to the control by the control data 32 for the device control circuit 32.

  FIG. 10 shows a case where data processing in the device based on the control data 31 is slow and WAIT is necessary for the next control. In this case, since it is necessary to wait for the status data 31 to be read until the control by the control data 31 for the device control circuit 31 is completed, the control by the control data 32 for the device control circuit 32 has been stopped until then. Show.

  As to what seems to be related to the present invention, a FIFO memory connected between two microprocessors for transferring data by mutual DMA transfer, and counting up when one microprocessor writes data to the FIFO memory, One having an up / down counter that counts down when the other microprocessor reads data from the FIFO memory is known (see, for example, Patent Document 1).

Also, a technique related to a FIFO memory control circuit that includes a FIFO memory and an up / down counter and can perform asynchronous read / write when the higher one of the write clock frequency and the read clock frequency is not already known is also known (see, for example, Patent Document 2). )
2-11205 (1st page-4th page, Fig. 1) JP 2001-307476 (first page-first page, FIG. 1)

  In the above-described conventional technology, the CPU side writes control data to a certain device control circuit, and then waits for execution of control for the next device control circuit until the device control circuit side receives a result of completion of control (WAIT processing) Therefore, when the control speed on the CPU side is faster than the processing speed on the device control circuit side, when controlling many device control circuits by polling, one of many device control circuits is required. There is a first problem that the control of all the device control circuits is slow only by the low speed of the device.

  In addition, if WAIT is added to the CPU process to solve the first problem, the second problem is that even if WAIT is not required due to improvements on the device control circuit side, the speed cannot be increased unless software is updated. is there. This is because CPU WAIT is generally controlled by a program.

  A main object of the present invention is to speed up device control processing by eliminating or reducing CPU WAIT during control of a device control circuit.

  The invention described in Patent Document 1 aims to eliminate waiting due to a data transfer collision on the data bus in DMA transfer. The invention described in Patent Document 2 is used when the frequency of the write clock and that of the read clock are different. The object is to prevent twice reading of the same data lost due to data overwriting.

  According to the first aspect of the present invention, each device control circuit (21 to 2N in FIG. 1) controls the subordinate device (8 in FIG. 2) based on control data received by polling from the CPU (10 in FIG. 1). In the FIFO memory (FIG. 2), the control data and the corresponding address of the device are written and held corresponding to the address of the same device based on the write enable signal WE from the CPU, and the held data is read to the device by the data request signal from the device. 5) and 6), and an up / down counter (7 in FIG. 2) that counts up by writing to the FIFO memory, counts down by a data request signal from the device, and outputs the count value to the CPU as a response signal. If the response signal ACK is the content that informs the write control stop, the write enable signal WE from the CPU in the write cycle concerned. A device control circuit, wherein the output is stopped.

  The invention according to claim 2 is the device control circuit according to claim 1, wherein the count value when the output of the write enable signal from the CPU is stopped is the depth number of the FIFO memory. is there.

  In the control circuit according to the present invention, a response signal ACK is output from the device control circuit to the CPU in addition to the data bus, address bus, write enable signal, and read enable signal between the CPU and the device control circuit. In addition, the device control circuit side includes a FIFO memory that holds data and addresses from the CPU, and an up / down counter that monitors the use status of the FIFO memory and outputs a response signal ACK. The effect of reducing the CPU WAIT is obtained by the function of this circuit.

  By adopting the configuration as described above, it becomes possible to eliminate or reduce the WAIT of the CPU when controlling the device control circuit, and to increase the speed during the polling control.

  Further, since the CPU side can control the WAIT during the control only by the state of the response signal ACK from the device control circuit, it is possible to omit the software adjustment accompanying the change in the hardware operation speed.

  The present invention provides each device control circuit that controls a subordinate device based on control data received by polling from the CPU, and controls the control data and the device's address corresponding to the address of the same device based on the write enable signal WE from the CPU. Write and hold the address, FIFO memory that reads the retained data to the device by the data request signal from the device, and counts up by writing to the FIFO memory, counts down by the data request signal from the device, and counts the count value An up / down counter that outputs to the CPU as a response signal is provided, and when the response signal ACK is a content to notify the stop of the write control, the output of the write enable signal WE from the CPU is stopped in the write cycle. .

  In order to clarify the above objects, features and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows a configuration example of a device control apparatus of the present invention.

  This device control apparatus comprises a CPU 10 and n device control circuits 21 to 2n. The CPU 10 and n device control circuits 21 to 2N include a data bus DBU, an address bus ABU, a write enable signal WE and Multiple connections are made by the read enable signal RE. In addition, response signals ACK1 to ACKN are individually output from the device control circuits 21 to 2N to the CPU 10.

  The CPU 10 polls the device control circuits 21 to 2N by sequentially sending addresses for designating the device control circuits 21 to 2N together with the control data. The device control circuits 21 to 2N control non-intelligent devices such as subordinate optical amplifiers based on the control data received from the CPU 10. When the status data from the device is received, it is read out to the CPU 10.

  The response signals ACK1 to ACKN notify the CPU 10 that the control data can be written to the device control circuits 21 to 2N. When the response signals ACK1 to ACKN are contents for notifying write control stop, the CPU 10 suppresses the output of the write enable signal WE in the write cycle. Note that the reference numeral 20 is used in the following description when describing the device control circuits 21 to 2N in general.

  The data bus DBU is used for the CPU 10 to write control data to the device control circuit 20 or read status data from the device control circuit 20. The address bus ABU is used to select the device control circuit 20 that the CPU 10 accesses. The write enable signal WE is a timing for writing control data to the device control circuit 20, and the read enable signal RE is a timing for reading state data from the device control circuit 20. The response signal ACK is used to notify the CPU 10 whether or not the processing of the control data written from the CPU 10 is completed in the device control side circuit 20.

  FIG. 2 shows details of an embodiment of the device control circuit 20 together with a control target circuit 8 which is a device. The device control circuit 20 includes a bidirectional buffer 1, an address decoder 2, an OR gate 3, an OR gate 4, a data holding FIFO memory 5, an address holding FIFO memory 6, and an up / down counter 7. The OR gate 3 and the OR gate 4 substantially function as AND gates.

  The bidirectional buffer 1 writes control data from the CPU 10 via the data bus DBU to the data holding FIFO memory 5 and sends output data from the control target circuit 8 to the CPU 10 via the data bus DBU as status data. Switching between data writing and reading directions is performed by a read enable signal REN from the OR gate 4.

  The address decoder 2 decodes the address on the address bus ABU and identifies whether the address value indicates its own circuit. The OR circuit 3 indicates the write enable signal WEN as the data holding FIFO memory 5 and the address holding FIFO when the output of the address decoder 2 indicates its own circuit and the write enable signal WE defining the data write timing is valid. Output to the memory 6 and up / down counter 7. That is, the write enable signal WE is a signal for the CPU 10 to perform the write control of the device control circuit 20, whereas the write enable signal WEN is generated from the output of the address decoder 2 and the write enable signal WE, and the device control circuit This is a signal for performing write control in 20 circuits.

  The OR circuit 4 indicates the read enable signal REN as the bidirectional buffer 1 and the control target when the output of the address decoder 2 indicates its own circuit and the read enable signal RE defining the data read timing is valid. Output to circuit 8. That is, the read enable signal RE is a signal for the CPU 10 to perform the read control of the device control circuit 20, whereas the read enable signal REN is generated from the output of the address decoder 2 and the read enable signal RE, and the device control circuit This is a signal for performing read control in 20 circuits.

  The data holding FIFO memory 5 is a FIFO (First In First Out) memory having a depth of m stages for temporarily holding control data from the bidirectional buffer 1. The data holding FIFO memory 5 writes the control data in response to the write enable signal WEN, and reads the control data to the control target circuit 8 in response to the data request signal from the control target circuit 8.

  The address holding FIFO memory 6 is a FIFO having the same depth as the data holding FIFO memory 5 that temporarily holds an address (control address) synchronized with the control data. The address holding FIFO memory 6 writes the address on the address bus ABU in response to the write enable signal WEN, and reads the control address to the control target circuit 8 in response to the data request signal from the control target circuit 8. The control address is an address that designates a location to be controlled by the control data in the control target circuit 8.

  The up / down counter 7 counts up in response to the write enable signal WEN and counts down in response to the data request signal from the control target circuit 8. Accordingly, the up / down counter 7 counts the number of control data written in the data holding FIFO memory 5 from 0 to m, and notifies the CPU 10 of the counted value as a response signal ACK.

  The control target circuit 8 requests the device control circuit 20 for the next control data every time the control by the control data read from the data holding FIFO memory 5 is completed. This request is made by sending a data request signal to the data holding FIFO memory 5 and the address holding FIFO memory 6. Further, in response to the read enable signal REN, the control target circuit 8 sends the output data at the address specified by the address on the address bus ABU at that time to the bidirectional buffer 1. The output data is data as a result of control in the control target circuit 8 by the control data.

  FIG. 3 is a flowchart when writing control data to the data holding FIFO memory 5 and an address to the holding FIFO memory 6. In the following description, negative logic is adopted, and “0” of the signal means valid and “1” means invalid.

  The address decoder 2 detects that the address on the address bus ABU is an address of its own circuit (Y in step S1 in FIG. 3), the write enable signal WEN is “0” (step S2), and is up If the count value of the down counter 7 is not the maximum value m (N in step S3), the up / down counter 7 does not indicate that the response signal ACK is a write control stop notification (step S4). Thereby, since the CPU 10 outputs the write enable signal WE, it is possible to synchronously write the control data to the data holding FIFO memory 5 and the address to the address holding FIFO memory 6 (step S5). In response to the write enable signal WEN, the count value of the up / down counter 7 is incremented by 1 (step S6).

  When the result of determination in step S1, S2 or S3 is different from the above, that is, when the address on the address bus ABU is not the address of its own circuit (N in step S1), or when the write enable signal WEN is “1” (Step S2), or when the count value of the up / down counter 7 is the maximum value m (Y in Step S3), the writing of control data to the data holding FIFO memory 5 and the writing of the address to the address holding FIFO memory 6 Is not done.

  This is because writing to the FIFO memories 5 and 6 is performed up to m bits in the depth of the FIFO memories 5 and 6, so if all m stages of the FIFO memories 5 and 6 are filled with data, the up / down counter 7 responds. Since the signal ACK “1” is output, this means that the control on the device control circuit 20 is stopped on the CPU 10 side.

  However, even if writing to the FIFO memories 5 and 6 is not performed in the specific device control circuit 20, the flow of FIG. 3 returns to step S1, and the conditions of steps S1 to S3 are changed for the other device control circuits 20 again. It is examined whether it meets. As a result, if these conditions can be cleared, writing to the FIFO memories 5 and 6 is performed in step S5, and the count value of the up / down counter 7 is incremented by 1 in step S6. In this way, even if writing control to the FIFO memories 5 and 6 is stopped by one device control circuit 20, writing to the FIFO memories 5 and 6 is unconditionally performed even in other device control circuits 20. It does not stop the control.

  FIG. 4 is a flowchart for reading control data from the data holding FIFO memory 5 and reading a control address from the address holding FIFO memory 6.

  When a data request signal is input from the control target circuit 8 (Y in step T1 in FIG. 4), the control data from the data holding FIFO memory 5 and the control address from the holding FIFO memory 6 to the control target circuit 8 by one stage respectively. Read (step T2). Further, the count value of the up / down counter 7 is decremented by 1 (step T3).

  FIG. 5 shows operation timings in writing control and reading control from the CPU 10 to the device control circuit 20. Here, it is assumed that the depth of the FIFO memory is 3 stages, the response signal ACK is 2 bits, and all control is for the device control circuit 20. Therefore, WE and WEN are the same. Initially, the data holding FIFO memory 5 and the address holding FIFO memory 6 are empty, the count value of the up / down counter 7 is “0”, and the response signal ACK is “00”.

  When the write enable signal WE = WEN becomes “0” at timing t1 while the address A0 is sent from the CPU 10 to the address bus ABU and the control data D00 is sent to the data bus DBU, the control data D00, The address A0 is written into the address holding FIFO memory 6. The count value of the up / down counter 7 is “1”, and the response signal ACK is “01”.

  When the data request signal becomes “0” at timing t2, the control data D00 from the data holding FIFO memory 5 and the address A0 from the address holding FIFO memory 6 are read to the control target circuit 8, and the data holding FIFO memory 5 and the address holding FIFO are read. The memory 6 becomes empty. Further, the count value of the countdown counter 7 is reset to “0”, and the response signal ACK is reset to “00”. This shows that the address A0 by the control data D00 is normally performed in the control target circuit 8.

  Next, when the write enable signal WE = WEN becomes “0” at timing t3 while the address A1 is sent from the CPU 10 to the address bus ABU and the control data D01 is sent to the data bus DBU, the data holding FIFO memory 5 is controlled. The address A1 is written to the data D01 and the address holding FIFO memory 6. The count value of the up / down counter 7 is “1”, and the response signal ACK is “01”.

  Before the data request signal becomes “0” in this state, the address bus ABU switches to the address A2, and the data bus DBU switches to the control data D10. When the write enable signal WE = WEN becomes “0” at the timing t4, the data is held. The control data D10 is written in the FIFO memory 5 and the address A2 is written in the address holding FIFO memory 6. Further, the count value of the up / down counter 7 is “2”, and the response signal ACK is “10”. This means that two data are stored in the FIFO memories 5 and 6. In this way, the number of stages (3 in this example) of the FIFO memories 5 and 6 can be continuously written without WAIT.

  Before the data request signal becomes “0” in this state, the address bus ABU switches to the address A0 and the data bus DBU switches to the control data D10. When the write enable signal WE = WEN becomes “0” at the timing t5, The control data D10 is written in the data holding FIFO memory 5 and the address A0 is written in the address holding FIFO memory 6. Further, the count value of the up / down counter 7 is “3”, and the response signal ACK is “11”. In this way, even if the reading is not performed, the number of stages (3 in this example) of the FIFO memories 5 and 6 can be continuously written without WAIT.

  However, when the count value of the up / down counter 7 reaches “3” and the response signal ACK reaches “11”, three data are stored in the FIFO memories 5 and 6 and become full. If not, write control is stopped. Until the FIFO memories 5 and 6 are vacant, the write control for this circuit is stopped.

  Since the data request signal is “0” at timing t 6, the count value of the up / down counter 7 is “2”, the response signal ACK is “10”, and 1 is stored in the FIFO memories 5 and 6. There are two spaces. Therefore, when the write enable signal WE = WEN becomes “0” at timing t7, the control data D00 at this time is written in the data holding FIFO memory 5 and the address A3 at this time is written in the address holding FIFO memory 6.

  Next, even when the write control is prohibited, if the CPU 10 sets the read enable signal RE to “0”, the state of the control target circuit 8 can be read. That is, in FIG. 2, when the CPU 10 sets the read enable signal REN to “0”, an output control signal is input from the OR gate 4 to the control target circuit 8. The address to be read is the address on the address buffer ABU at this time, and is supplied to the control target circuit 8 as an output address. In response to this, the control target circuit 8 outputs output data, which is state data, to the bidirectional buffer 1. Since this status data appears on the data buffer DBU, the CPU 10 can capture it.

  As described above, since the reading of the state data is performed regardless of the writing of the control data, WAIT is not necessary. The timing chart in this case is the same as that in the case of the prior art shown in FIGS. Further, by checking the value of the response signal ACK at the time of reading, it is possible to know whether or not the data to be read has already been controlled. In the device control circuit 20 of FIG. 2, if the response signal ACK is “00”, all the control performed by the CPU 10 is completed.

  It should be noted that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.

The block diagram which shows the structural example of the device control apparatus of this invention The block diagram which shows one Example of the device control circuit of this invention Flowchart at the time of data writing to the FIFO memory in the device control circuit shown in FIG. Flowchart when reading data from FIFO memory in device control circuit shown in FIG. Control timing chart in write control and read control from CPU for device control circuit shown in FIG. Block diagram showing a configuration example of a conventional device control apparatus Write control timing chart to the device control circuit shown in FIG. Read control timing chart from the device control circuit shown in FIG. Timing chart when writing / reading to the device control circuit shown in FIG. 6 continuously without WAIT Timing chart when writing / reading to the device control circuit shown in FIG.

Explanation of symbols

1 Bidirectional buffer 2 Address decoder 3 OR gate 4 OR gate 5 Data holding FIFO memory 6 Address holding FIFO memory 7 Up / down counter 8 Control target circuit
10 CPU
21 to 2N device control circuit
ABU address bus
ACK response signal
DBU data bus
RE Read enable signal
REN Read enable signal
WE Write enable signal
WEN Write enable signal

Claims (2)

In each device control circuit that controls subordinate devices based on the control data received by polling from the CPU,
Based on a write enable signal from the CPU, a FIFO memory that writes and holds the control data and the address of the device corresponding to the address of the same device, and reads the held data to the device by a data request signal from the device;
Counting up by writing to the FIFO memory, counting down by a data request signal from the device, and having an up / down counter that outputs the count value to the CPU as a response signal,
The device control circuit according to claim 1, wherein when the response signal has a content for notifying the stop of the write control, the output of the write enable signal from the CPU is stopped in the write cycle. 2. The device control circuit according to claim 1, wherein the count value when the output of the write enable signal from the CPU is stopped is a depth number of the FIFO memory.

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