JP2005175365A - Capacity variable substrate and substrate parasitic capacity adjustment method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a capacity variable substrate that can decrease parasitic capacity of a substrate, as well as adjusting its parasitic capacity, and to obtain a substrate parasitic capacity adjustment method for adjusting substrate's parasitic capacity. <P>SOLUTION: On this capacity variable substrate a dielectric layer 2 is formed between a wiring conductor 3 and a ground layer 4, and its dielectric constant is made variable by producing a depletion layer 10 in this dielectric layer 2, thus forming a semiconductor 12 that can adjust the parasitic capacity, which is parasitic on the wiring conductor 3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a substrate on which a high-frequency circuit is formed, and more particularly to a variable capacitance substrate that makes the parasitic capacitance of the substrate variable, and a substrate parasitic capacitance adjustment method that adjusts the parasitic capacitance of the substrate.

In general, in a high-frequency circuit board on which a high-frequency circuit that handles high-frequency signals is formed, the parasitic capacitance of a portion where wiring conductors such as wiring and pads are formed affects the circuit characteristics. For this reason, it is not easy to obtain a high-frequency circuit having desired characteristics. Therefore, it is desired to reduce the parasitic capacitance of the substrate and to adjust the parasitic capacitance of the substrate to a predetermined value.
Conventionally, as a method for reducing and adjusting the parasitic capacitance of a substrate, a method of forming a void or vacuum space as a low dielectric portion between a capacitor formed inside the substrate and a ground layer, A method of embedding a material having a lower dielectric constant than the material of the substrate has been proposed (see, for example, Patent Document 1).

In addition, a method has been proposed in which a portion of the ground layer provided with the wiring conductor is arranged so that the distance between the wiring conductor and the ground layer is increased to reduce parasitic capacitance (for example, see Patent Document 2). ).
Japanese Patent Laid-Open No. 7-307575 (pages 2, 3 and 1) Japanese Patent Laid-Open No. 10-013163 (pages 3, 4 and 1)

However, the method of Patent Document 1 has an unsolved problem that it is difficult to accurately match the parasitic capacitance with the initially expected value after the completion of the substrate fabrication.
Further, the method of Patent Document 2 has an unsolved problem similar to the method of Patent Document 1 and an unsolved problem that the thickness of the substrate is increased.
The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a variable capacitance substrate that can adjust the parasitic capacitance of the substrate and a substrate parasitic capacitance adjustment method that adjusts the parasitic capacitance of the substrate.

In the capacitance variable substrate according to the first aspect of the present invention, a dielectric layer is formed between the wiring conductor and the ground layer, and the dielectric constant is varied by generating a depletion layer in the dielectric layer, thereby making the wiring conductor parasitic. Since the semiconductor element capable of adjusting the parasitic capacitance is formed, the parasitic capacitance parasitic on the wiring conductor can be adjusted.
In the capacitance variable substrate according to the second invention, the semiconductor element has a bias voltage application electrode to which a bias voltage is applied, and the amount of depletion layer generated by changing the bias voltage applied to the bias voltage application electrode. Therefore, the amount of the depletion layer can be increased or decreased by changing the bias voltage applied to the semiconductor element, and the parasitic capacitance can be adjusted.

In the variable capacitance substrate according to the third aspect of the invention, the semiconductor element is formed by joining a p-type semiconductor and an n-type semiconductor so that the joining direction of the p-type semiconductor and the n-type semiconductor is along the ground layer. Therefore, a depletion layer can be easily generated.
In the capacitance variable substrate according to the fourth invention, the semiconductor element has a transistor structure in which three p-type semiconductors and n-type semiconductors are joined alternately and the bias voltage application electrode is formed on the ground layer side. A depletion layer can be generated in the central semiconductor of the three junction p-type and n-type semiconductors.

In the variable capacitance substrate according to the fifth aspect of the present invention, the bias voltage application electrode is provided on the same plane as the ground layer. Therefore, a semiconductor that generates a depletion layer without increasing the thickness of the dielectric layer. The height in the direction perpendicular to the dielectric layer of the element can be maximized, and the number of depletion layers to be generated can be increased.
In the variable capacitance substrate according to the sixth aspect of the present invention, the transistor structure is a pnp type transistor structure, so that it can be easily manufactured with existing technology.

In the variable capacitance substrate according to the seventh invention, since the transistor structure is an npn type transistor structure, the operation can be made faster than the pnp type.
In the variable capacitance substrate according to the eighth aspect of the invention, since the capacitor is connected to the gate electrode of the npn transistor structure, the gate electrode should be treated as a stable potential with respect to the AC circuit and actively treated as the ground. Make it possible.

In the variable capacitance substrate according to the ninth invention, the semiconductor element has a diode structure in which a plurality of sets of pn junction semiconductors are joined in series. Therefore, the depletion layer can be generated at a plurality of locations along the bonding direction, and the depletion layer can be generated in a wide region.
In the variable capacitance substrate according to the tenth aspect of the invention, since the bias voltage application electrode is exposed from the through hole formed in the ground layer in the semiconductor element, the bias application means can be easily connected. Cost can be reduced.

  According to an eleventh aspect of the present invention, there is provided a substrate parasitic capacitance adjusting method comprising: forming a semiconductor element that generates a depletion layer according to an applied bias voltage in a substrate in which a dielectric layer is formed between a wiring conductor and a ground layer. In addition, since the bias voltage is changed to increase / decrease the amount of depletion layer generated and the dielectric constant is varied to adjust the parasitic capacitance parasitic to the wiring conductor, the parasitic capacitance parasitic to the wiring conductor can be adjusted.

  FIG. 1 is a cross-sectional view for explaining a procedure for manufacturing a variable capacitance substrate according to the first embodiment of the present invention. FIG. 1A shows a state in which a transistor structure 12 as a semiconductor element is built in a high-frequency circuit substrate 11 that is a variable capacitance substrate. The high-frequency circuit board 11 has a substrate body 5 and a transistor structure 12 formed inside the substrate body 5. The substrate body 5 includes a planar dielectric layer 2 made of silicon (silicon) and wiring conductors such as a signal transmission line, a power transmission line, and a pad provided on the first main surface 2 a of the dielectric layer 2. 3 and a ground layer 4 provided over the entire surface of the second main surface 2 b of the dielectric layer 2.

The transistor structure 12 includes a junction structure 12s formed by joining a p-type semiconductor 12a, an n-type semiconductor 12b, and a p-type semiconductor 12c in a pnp type, and bias voltage application formed by electrodes 7, 8, and 9 provided in each semiconductor. It is comprised from the electrode 12t.
In the production of the high-frequency circuit substrate 11, the transistor structure 12 is produced by being embedded in a through hole 2 c formed in a predetermined portion of the substrate body 5. In the transistor structure 12, a pnp-type MOS field effect transistor is manufactured on another substrate by an existing method, and a portion where the transistor is formed is partially cut out. Regarding the semiconductor material, the p-type semiconductors 12a and 12c are manufactured by adding boron as an impurity to high-purity silicon, and the n-type semiconductor 12b is formed by adding phosphorus or arsenic as an impurity to high-purity silicon.

  When the transistor structure 12 is embedded in the dielectric layer 2, the three semiconductors 12 a, 12 b, and 12 c are arranged so that the junction direction is along the main surface of the dielectric layer 2. At this time, one side surface parallel to the joining direction (the upper surface in FIG. 2A) is arranged so as to be flush with the first main surface 2a. A wiring conductor 3 is provided in a portion exposed to the first main surface 2a of the transistor structure 12. The wiring conductor 3 is provided at a position facing the portion where the depletion layer of the junction structure 12s is generated. In the present embodiment, the wiring conductor 3 is provided on the surface of the n-type semiconductor 12b.

  The other side surface (the lower surface in FIG. 2A) of the transistor structure 12 is exposed from the through hole 4 a formed in the ground layer 4. A bias voltage application electrode 12t is disposed on the exposed surface. A source electrode 7 is provided on the p-type semiconductor 12 a, a gate electrode 8 is provided on the n-type semiconductor 12 b, and a drain electrode 9 is provided on the p-type semiconductor 12 c, and a bias composed of the plurality of electrodes 7, 8, 9 is provided. The voltage application electrode 12t is disposed so as to be flush with the ground layer 4. An oxide film layer (not shown) is formed between the n-type semiconductor 12b and the gate electrode 8.

  FIG. 1B shows a state in which bias applying means is connected to the transistor structure 12. The source electrode 7 provided on the p-type semiconductor 12a is connected to the positive electrode of a DC power supply 13 whose negative electrode is grounded. The gate electrode 8 provided on the n-type semiconductor 12 b is grounded by the wiring 14. The drain electrode 9 provided on the p-type semiconductor 12 c is grounded by the wiring 15. The DC power supply 13 and the wirings 14 and 15 constitute a bias applying means 20. The DC power supply 13 applies a positive voltage to the source electrode 7.

  Next, the operation will be described. Before the voltage is applied to the source electrode 7, the PN junction blocks the current, and no current flows between the source electrode 7 and the drain electrode 9. At this time, the dielectric constant of the n-type semiconductor 12b is ε1. However, when a bias voltage is applied to the source electrode 7, electrons in the n-type semiconductor 12b are driven away from the vicinity of the junction surface between the oxide film immediately below the gate electrode 8 and the n-type semiconductor 12b, and a depletion layer 10 is generated in this portion. When the voltage applied to the source electrode 7 is increased, the depletion layer 10 is further generated, holes are attracted to the junction surface, and a thin p-type inversion layer is formed on the n-type semiconductor 12b in contact with the oxide film. Is done. As a result, the source electrode 7 and the drain electrode 9 are electrically connected and a current flows. At this time, the dielectric constant ε2 of the depletion layer 10 formed in the n-type semiconductor 12b is as follows.

From the equation (1), it can be seen that the dielectric constant ε2 of the depletion layer 10 varies with the bias voltage V. Here, the dielectric constant of the entire n-type semiconductor 12b is such that the thickness of the n-type semiconductor 12b in the region where the depletion layer 10 in the direction perpendicular to the substrate body 5 is not formed is d1, and the region where the depletion layer 10 is formed. When the thickness of the n-type semiconductor 12b is d2, the total dielectric constant of the entire n-type semiconductor 12b is (ε1d1 + ε2d2) / (d1 + d2). As the bias voltage V is increased, the generation amount of the depletion layer 10 is increased and the low dielectric constant region is increased, so that the total dielectric constant is decreased.

  Here, the parasitic capacitance parasitic on the wiring conductor 3 can be expressed as follows. The parasitic capacitance C between the wiring conductor 3 and the ground layer 4 in a general high-frequency circuit board in which the transistor structure 12 is not formed is as follows when the base material dielectric constant of the dielectric layer 2 is ε0.

From equation (2), either the base material dielectric constant ε0 of the dielectric layer 2 and the bonding surface area S of the wiring conductor 3 with the dielectric layer 2 are reduced, or the distance between the wiring conductor 3 and the ground layer 4 is reduced. The parasitic capacitance can be reduced by increasing d.
In the present embodiment, by applying a bias voltage to the transistor structure 12, the depletion layer 10 is generated in the n-type semiconductor 12b to reduce the dielectric constant of this portion, thereby reducing the parasitic capacitance parasitic to the wiring conductor 3. can do. Furthermore, the amount of generation of the depletion layer 10 can be increased or decreased by changing the bias voltage. Thereby, the parasitic capacitance parasitic on the wiring conductor 3 can be adjusted.

In this embodiment, since the junction direction of the p-type and n-type semiconductors of the transistor structure 12 is arranged along the main surface 2a, the bias voltage application electrode 12t is used as the second main surface of the transistor structure 12. It can be provided on the 2b side. Furthermore, since the semiconductor element has a pnp transistor structure 12, it can be easily manufactured by an existing method.
Furthermore, since the semiconductor element is the pnp transistor structure 12 and the bias voltage application electrode 12t is provided on the main surface 2a side, a p-type inversion layer can be formed in the vicinity of the oxide film directly under the gate electrode 8, The depletion layer 10 can be generated in this portion.

Since the bias voltage application electrode 12t is provided in the same plane as the ground layer 4, the n-type semiconductor 12b that generates the depletion layer 10 with respect to the substrate 2 without increasing the thickness of the dielectric layer 2. The height in the direction perpendicular to the main surface 2a of the dielectric layer 2 can be maximized, and the number of depletion layers 10 to be generated can be increased.
FIG. 2 is a cross-sectional view for explaining the procedure for manufacturing the variable capacitance substrate according to the second embodiment of the present invention. FIG. 2A shows a state in which a transistor structure 22 as a semiconductor element is built in a high-frequency circuit substrate 21 that is a variable capacitance substrate. In the present embodiment, a concave portion 2d having a thickness of about 1/3 of the substrate thickness is formed in a predetermined portion of the second main surface 2b of the dielectric layer 2, and a pnp transistor structure 22 is embedded in the concave portion 2d. . As in the first embodiment, the transistor structure 22 is fabricated in advance by fabricating a pnp-type MOS field effect transistor on another substrate by an existing method, and partially cutting off the portion where the transistor is formed. Similar to the first embodiment, the transistor structure 22 is arranged such that the bonding directions of the three semiconductors 22a, 22b and 22c constituting the bonding structure 22s are along the first main surface 2a of the dielectric layer 2. The The wiring conductor 3 is provided at a position facing the n-type semiconductor 22 b on the first main surface 2 a of the dielectric layer 2. The main surface 2b side of the transistor structure 22 is exposed from a through hole 4a formed in the ground layer 4, and a bias voltage application electrode 22t composed of a source electrode 7, a gate electrode 8, and a drain electrode 9 is disposed here. .

  As shown in FIG. 2B, the bias applying means 20 is connected to the transistor structure 22 in the same manner as in the first embodiment. The transistor structure 22 operates in the same manner as that of the first embodiment when a bias voltage is applied by the bias applying means 20. Then, the depletion layer 10 is generated in the portion of the n-type semiconductor 22b facing the gate electrode 8, and thereby the dielectric constant of the n-type semiconductor 22b can be adjusted.

  The total dielectric constant from the wiring conductor 3 to the gate electrode 8 is a region where the thickness of the dielectric layer 2 from the wiring conductor 3 in the direction perpendicular to the substrate body 5 to the bottom surface of the recess 2d is d0, and no depletion layer is formed. When the thickness of the n-type semiconductor 22b is d1 and the thickness of the n-type semiconductor 22b in the region where the depletion layer is formed is d2, the total dielectric constant of the entire n-type semiconductor 22b is (ε0d0 + ε1d1 + ε2d2) / (d0 + d1 + d2) It becomes. As the bias voltage V is increased, the generation amount of the depletion layer 10 is increased and the low dielectric constant region is increased, so that the total dielectric constant is decreased.

  As described above, in the present embodiment, the recess 2d is formed in the second main surface 2b of the dielectric layer 2, and the transistor structure 22 is embedded in the recess 2d. Therefore, the hole for embedding the transistor structure 22 does not penetrate on the first main surface 2a side of the high-frequency circuit board 21 and the rigidity of the high-frequency circuit board 21 is improved. Further, in the manufacturing process, even after the wiring conductor 3 is formed on the first main surface 2a in the dielectric layer 2, the recess 2d is formed on the second main surface 2b on the opposite side to the wiring conductor 3, thereby forming a transistor. The structure 22 can be embedded, and the degree of freedom of the manufacturing process is increased.

  FIG. 3 is a cross-sectional view for explaining the procedure for manufacturing the variable capacitance substrate according to the third embodiment of the present invention. FIG. 3A shows a state in which a transistor structure 32 as a semiconductor element is formed inside a high-frequency circuit substrate 31 that is a capacitance variable substrate. In the high-frequency circuit board 31 of the present embodiment, an npn transistor structure 32 is embedded in a through hole 2 c formed in the dielectric layer 2. The transistor structure 32 includes a junction structure 32s formed by joining an n-type semiconductor 32a, a p-type semiconductor 32b, and an n-type semiconductor 32c in an npn type, and bias voltage application formed by electrodes 7, 8, and 9 provided in each semiconductor. It is comprised from the electrode 32t. The transistor structure 32 is fabricated in advance by fabricating an npn-type MOS field effect transistor on another substrate by an existing method, and partially cutting off the portion where the transistor is formed.

Concerning materials, for example, the dielectric layer 2 is silicon (silicon), the p-type semiconductor 32b is a high-purity silicon obtained by adding boron as an impurity, and the n-type semiconductors 32a and 32c are high-purity silicon containing phosphorus or arsenic as an impurity. It is made by adding
The wiring conductor 3 is formed on the surface of the p-type semiconductor 32b exposed at the first main surface 2a side of the transistor structure 32. A source electrode 7 is provided on the n-type semiconductor 32a, a gate electrode 8 is provided on the p-type semiconductor 32b, and a drain electrode 9 is provided on the n-type semiconductor 32c. A bias voltage applied by these electrodes 7, 8, 9 is applied. The electrode 32t is disposed so as to be flush with the ground layer 4.

  FIG. 3B shows a state in which bias applying means is connected to the transistor structure 32. The source electrode 7 is grounded by a wiring 18. A DC power supply 16 is connected to the gate electrode 8. A DC power source 17 is connected to the drain electrode 9. The wiring 18 and the DC power supplies 16 and 17 constitute a bias applying unit 20 that applies a bias voltage to the transistor structure 32. The DC power supply 16 applies a positive voltage to the gate electrode 8. The DC power source 17 applies a positive voltage to the drain electrode 9.

  Next, the operation will be described. In a state before the voltage is applied to the gate electrode 8, the PN junction cuts off the current, and no current flows between the source electrode 7 and the drain electrode 9. However, when a bias voltage is applied to the gate electrode 8, holes in the p-type semiconductor 32b are driven away from the junction surface between the oxide film immediately below the gate electrode 8 and the p-type semiconductor 32b, and a depletion layer 10 is generated there. When the bias voltage applied to the gate electrode 8 is increased, the depletion layer 10 is further generated, and electrons are attracted to the junction surface to form a thin n-type inversion layer, thereby forming the source electrode 7 and the drain electrode 9. Are connected and current flows. At this time, the amount of the depletion layer formed in the p-type semiconductor 32b varies depending on the bias voltage as in the case of the n-type semiconductor 12b of the first embodiment.

  FIG. 3C shows another embodiment of the high-frequency circuit board 31 of this embodiment. In the high frequency circuit board 31 of FIG. 3C, a capacitor 19 is connected to the gate electrode 8. Although the DC voltage is applied to the gate electrode 8 as described above, it is desirable that the gate electrode 8 is at a position facing the wiring conductor 3 and ideally be at a ground potential. Although it cannot be a ground potential, a capacitor 19 is connected to the gate electrode 8 so that the ground potential can be positively handled as a more stable potential with respect to the AC circuit.

In the present embodiment, since the semiconductor element has an npn type transistor structure, the operation can be made faster than the pnp type.
FIG. 4 is a cross-sectional view for explaining the procedure for manufacturing the variable capacitance substrate according to the fourth embodiment of the present invention. FIG. 4A shows a state in which a transistor structure 42 as a semiconductor element is built in a high-frequency circuit substrate 41 which is a variable capacitance substrate. In the present embodiment, a recess 2d is formed in a predetermined portion of the second main surface 2b of the dielectric layer 2, and a transistor structure 42 of an npn MOS field effect transistor is embedded in the recess 2d. The transistor structure 42 includes a junction structure 42s formed by joining an n-type semiconductor 42a, a p-type semiconductor 42b, and an n-type semiconductor 42c in an npn type, and bias voltage application formed by electrodes 7, 8, and 9 provided in each semiconductor. It is comprised from the electrode 42t.

In addition, the electrode structure and the operation when a bias voltage is applied are the same as in the third embodiment. Further, the manner in which the dielectric layer 2 is embedded in the recess 2d is the same as in the second embodiment.
As shown in FIG. 4C, the dielectric constant of the portion of the substrate 41 where the p-type semiconductor 42b is provided is adjusted by changing the bias voltage applied to the gate electrode 8 in this embodiment as well. Accordingly, the parasitic capacitance of this portion of the substrate 41 can be adjusted.

FIG. 4 (c) shows another embodiment of the high-frequency circuit board 41 of this embodiment. In the high-frequency circuit board 41 of FIG. 4C, a capacitor 19 is connected to the gate electrode 8 for the same purpose as that of the third embodiment.
FIG. 5 is a sectional view of a variable capacitance substrate according to a fifth embodiment of the present invention. A diode structure 52 as a semiconductor element is embedded in a high-frequency circuit substrate 51 that is a variable capacitance substrate. The diode structure 52 includes a junction structure 52s formed of a four-layer diode in which two sets of pn-junction semiconductors are connected in series, and flat cathode electrodes 25 provided at both ends in the stacking direction of the four-layer diode. The bias voltage application electrode 52t is composed of the anode electrode 26. The diode structure 52 is embedded in the dielectric layer 2 so that the bonding direction of the bonding structure 52s is along the first main surface 2a of the dielectric layer 2. The wiring conductor 3 is provided at a position facing the bonding structure 52s of the first main surface 2a of the dielectric layer 2. That is, the diode structure 52 is disposed so that the junction structure 52s faces the wiring conductor 3 side.

  Regarding the arrangement of the electrodes 25 and 26 of the diode structure 52, it is desirable to arrange them so that the projected areas projected perpendicularly to the direction of the wiring conductor 3 are minimized. That is, in the present embodiment, it is desirable that the projection area projected perpendicularly to the first main surface 2a is arranged to be the smallest. That is, it is desirable that the main surfaces of the cathode electrode 25 and the anode electrode 26 are arranged so as to be orthogonal to the first main surface 2a. This is because parasitic capacitance is generated between the electrode 25 and the wiring conductor 3 and between the electrode 26 and the wiring conductor 3, and the magnitude thereof is proportional to the opposing area and inversely proportional to the distance. Since the thickness of the electrode 25 and the electrode 26 is very small with respect to the area of the main surface of the wiring conductor 3, the parasitic capacitance generated can be made very small by arranging the electrodes 25 and 26 so as to be orthogonal to the wiring conductor 3. it can.

A DC power source 27 inside the dielectric layer 2 is connected to the cathode electrode 25. The anode electrode 26 is connected to the ground electrode by a wiring 28.
Next, the operation will be described. The DC power source 27 applies a positive voltage to the cathode electrode 25. When a reverse bias voltage is applied, the pn junction p-type semiconductor and n-type semiconductor form a depletion layer near the junction surface. In the present embodiment, the junction surface between the n-type semiconductor 52a and the p-type semiconductor 52b, the junction surface between the p-type semiconductor 52b and the n-type semiconductor 52c, and the junction surface between the n-type semiconductor 52c and the p-type semiconductor 52d are respectively depleted. A layer is generated. The generation amount of this depletion layer increases or decreases according to the reverse bias voltage.

As described above, in the present embodiment, the diode structure 52 has the junction structure 52s formed of a plurality of layers of diodes in which a plurality of sets of pn junction semiconductors are joined in series, and the depletion layer is a pn junction. Since it occurs at a plurality of locations along the direction, the depletion layer can be generated in a wide region.
In each of the embodiments described above, at least three semiconductors are joined to form a junction structure. However, the minimum configuration is a junction structure composed of a pair of p-type semiconductor and n-type semiconductor. Good.

  Further, the semiconductor element applied to the present invention may have either a transistor structure or a diode structure as described above. The transistor structure is not limited to a MOS type field effect transistor, but may be a junction of another field effect transistor. It may be a type field effect transistor or a bipolar transistor. Further, the diode structure may be any of a rectifier diode, a Zener diode, etc. Further, it may be applied to any device having a semiconductor and changing the generation amount of the depletion layer by increasing / decreasing the bias voltage. it can.

Furthermore, a depletion layer is formed by applying a bias voltage to a metal-semiconductor junction FET type high frequency transistor which is a so-called Schottky junction having no pn junction, and can be applied to the present invention. A Schottky barrier diode can also be applied to the present invention for the same reason.
In each of the above-described embodiments, each substrate body 5 has a single dielectric layer 2. However, the same effect can be obtained when a plurality of dielectric layers 2 and ground layers 4 are provided. I can expect.

It is sectional drawing explaining the procedure of preparation of the capacity | capacitance variable substrate of 1st Embodiment of this invention. It is sectional drawing explaining the procedure of preparation of the capacity | capacitance variable substrate of 2nd Embodiment of this invention. It is sectional drawing explaining the procedure of preparation of the capacity | capacitance variable substrate of 3rd Embodiment of this invention. It is sectional drawing explaining the procedure of preparation of the capacity | capacitance variable substrate of 4th Embodiment of this invention. It is sectional drawing of the capacity | capacitance variable board of 5th Embodiment of this invention.

Explanation of symbols

  2 dielectric layer, 2a first main surface, 2b second main surface, 2c through hole, 2d recess, 3 wiring conductor, 4 ground layer, 5 substrate body, 7 source electrode, 8 gate electrode, 9 drain electrode, 10 depletion layer, 12, 22 pnp type transistor structure (semiconductor element), 12s, 22s, 32s, 42s, 52s junction structure, 12t, 22t, 32t, 42t, 52t bias voltage application electrode, 19 capacitor, 20 bias application means, 32, 42 npn type transistor structure (semiconductor element), 52 diode structure (semiconductor element).

Claims (11)

  A dielectric layer is formed between the wiring conductor and the ground layer, and a semiconductor element capable of adjusting a parasitic capacitance parasitic to the wiring conductor by changing a dielectric constant by generating a depletion layer in the dielectric layer. A capacitance variable substrate formed.   The semiconductor element has a bias voltage application electrode to which a bias voltage is applied, and the dielectric constant is varied by adjusting the amount of depletion layer generated by changing the bias voltage applied to the bias voltage application electrode. The variable capacitance substrate according to claim 1, wherein the variable capacitance substrate is configured.   The semiconductor element is configured by joining a p-type semiconductor and an n-type semiconductor, and the joining direction of the p-type semiconductor and the n-type semiconductor is set to be a direction along the ground layer. The capacity variable substrate according to claim 1 or 2.   3. The transistor element according to claim 2, wherein the semiconductor element has a transistor structure in which three p-type semiconductors and n-type semiconductors are alternately joined, and the bias voltage application electrode is formed on the ground layer side. Variable capacity board.   5. The variable capacitance substrate according to claim 2, wherein the bias voltage application electrode is provided on the same plane as the ground layer.   5. The variable capacitance substrate according to claim 4, wherein the transistor structure is a pnp type transistor structure.   5. The capacitance variable substrate according to claim 4, wherein the transistor structure is an npn type transistor structure.   8. The variable capacitance substrate according to claim 7, wherein a capacitor is connected to a gate electrode of the npn transistor structure.   4. The variable capacitance substrate according to claim 3, wherein the semiconductor element has a diode structure in which a plurality of sets of pn junction semiconductors are joined in series.   10. The variable capacitance substrate according to claim 1, wherein the semiconductor element has a bias voltage application electrode exposed through a through hole formed in the ground layer. 11.   A semiconductor element that generates a depletion layer in accordance with an applied bias voltage is formed in a substrate having a dielectric layer formed between a wiring conductor and a ground layer, and the bias voltage is changed to change the depletion layer. A substrate parasitic capacitance adjusting method characterized in that a parasitic capacitance parasitic to the wiring conductor can be adjusted by changing a dielectric constant by increasing / decreasing a generation amount.

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