JP2005175081A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having good silicide/silicon interface in which a crystal defect or roughness of the interface is improved and having stable characteristics, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device 100 includes a semiconductor layer 14 including at least a silicon, a gate insulating layer 26 formed on the semiconductor layer 14, a gate electrode 28 formed on the gate insulating layer 16, impurity layers 22, 24 formed on the semiconductor layer 14 and constituting a source/drain region, and silicide layers 32, 34 formed on the impurity layers 22, 24. Group IV elements except the silicon are included in the interface region IA1 between the impurity regions 22, 24 and the silicide layers 32, 34, and the group IV elements have the peak of a concentration distribution in the interface region IA1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a silicide structure and a method for manufacturing the same.

For the purpose of reducing the sheet resistance of the source / drain regions, it is known to provide a silicide layer on the surface of an impurity layer constituting the source / drain regions (see, for example, Japanese Patent Laid-Open No. 5-36632).
JP-A-5-36632

  The source / drain regions are formed by introducing n-type or p-type impurities into the silicon semiconductor layer. At the interface between the source / drain region and the silicide layer, crystal distortion caused by the difference in lattice constant between the silicon semiconductor layer and the silicide layer is significant. In such a semiconductor device, a sharp stress is generated at the interface between the source / drain region and the silicide layer (silicide / silicon interface), particularly during heat treatment, and therefore, there is a problem that crystal defects and roughness of the interface are likely to occur due to strain. is there. Such crystal defects at the interface and roughness of the interface cause an increase in junction leakage and contact resistance at the silicide / silicon interface. In particular, as the junction depth of the impurity layer constituting the source / drain region becomes shallower with the miniaturization of transistors, higher integration, or the adoption of SOI structure, junction leakage due to roughness or lattice defects at the silicide / silicon interface. In addition, an increase in contact resistance becomes a factor that degrades the characteristics of the semiconductor device.

  An object of the present invention is to provide a semiconductor device having a good silicide / silicon interface with improved crystal defects and roughness of the interface, having stable characteristics, and a method for manufacturing the same, which solves such problems.

The semiconductor device according to the present invention is
A semiconductor layer containing at least silicon;
A gate insulating layer formed on the semiconductor layer;
A gate electrode formed on the gate insulating layer;
An impurity layer forming a source / drain region formed in the semiconductor layer;
A silicide layer formed on the impurity layer;
Including
The interface region between the impurity layer and the silicide layer contains a Group 4 element other than silicon, and the Group 4 element has a concentration distribution peak in the interface region.

  According to this semiconductor device, the presence of a group 4 element other than silicon in the interface region (silicide / silicon interface region) between the impurity layer and the silicide layer reduces stress in the interface region, Generation of lattice defects and roughness can be suppressed.

  In the semiconductor device according to the present invention, the group 4 element other than silicon may be at least one of carbon and germanium.

  In the semiconductor device according to the present invention, the semiconductor layer may have an SOI (Silicon On Insulator) structure formed on the insulating layer.

  In the semiconductor device according to the present invention, the source / drain regions may have an elevated structure.

  In the semiconductor device according to the present invention, the semiconductor layer may include at least one of a Si layer, a SiGe layer, and a SiGeC layer.

The manufacturing method according to the present invention includes:
Forming a gate insulating layer over a semiconductor layer containing at least silicon;
Forming a gate electrode on the gate insulating layer;
Forming an impurity layer for source / drain regions in the semiconductor layer;
Forming a silicide layer on the impurity layer;
Forming a semiconductor layer containing a group 4 element other than silicon on the semiconductor layer before the step of forming the silicide layer;
By redistributing at least the group 4 element other than silicon by heat treatment, the group 4 element other than silicon is present in the interface region between the impurity layer and the silicide layer so as to have a peak of its concentration distribution. Process,
including.

  According to this manufacturing method, a group 4 element other than silicon can be present so as to have a concentration distribution peak in the interface region between the impurity layer and the silicide layer by a relatively simple process.

Here, “a step of forming a semiconductor layer containing a group 4 element other than silicon on the semiconductor layer”
Forming a semiconductor layer containing a group 4 element other than silicon directly on the semiconductor layer, and a semiconductor layer containing a group 4 element other than silicon via another semiconductor layer on the semiconductor layer. Including the case of forming.

  In the method of manufacturing a semiconductor device according to the present invention, the semiconductor layer containing a group 4 element other than silicon can be formed by epitaxial growth.

  In the method of manufacturing a semiconductor device according to the present invention, the semiconductor layer containing a group 4 element other than silicon can be formed by introducing a group 4 element other than silicon into the semiconductor layer by ion implantation.

  In the manufacturing method according to the present invention, the semiconductor layer may include at least one of a Si layer, a SiGe layer, and a SiGeC layer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1. 1. First embodiment 1.1. Semiconductor Device FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to the present embodiment.

  The semiconductor device 100 is configured using an SOI substrate. That is, the semiconductor device 100 includes a semiconductor substrate 10, an insulating layer 12 formed on the semiconductor substrate 10, and a silicon layer 14 formed on the insulating layer 12. The silicon layer 14 is single crystal silicon.

  In the silicon layer 14, a channel region 20 and a first impurity layer 22 and a second impurity layer 24 for source / drain regions located on both sides of the channel region 20 are formed. A gate insulating layer 26 is formed on the channel region 20. A gate electrode 28 is formed on the gate insulating layer 26. A sidewall insulating layer 29 is formed on the side surface of the gate electrode 28. A first silicide layer 32 and a second silicide layer 34 are formed on the exposed surfaces of the first impurity layer 22 and the second impurity layer 24, respectively.

  In the interface region IA1 between the silicon layer and the silicide layer, that is, the interface region IA1 between the first impurity layer 22 and the first silicide layer 32 and the interface region IA1 between the second impurity layer 24 and the second silicide layer 34, There are Group 4 elements other than silicon. Examples of the group 4 element include at least one of carbon and germanium. Then, as schematically shown in FIG. 2, the group 4 element is distributed in the interface region IA1 in a state where the peak of the concentration distribution exists. In FIG. 2, the horizontal axis indicates the depth from the surface of the silicide layers 32 and 34, and the vertical axis indicates the concentration of the group 4 element. FIG. 2 schematically shows the concentration distribution when germanium is used as the group 4 element.

  According to the semiconductor device 100 according to the present embodiment, a group 4 element other than silicon is present in the silicide / silicon interface region IA1 between the silicon layer 14 (impurity layers 22 and 24) and the silicide layers 32 and 34. , Has the following characteristics.

  For example, carbon and germanium are the same group 4b elements as silicon and have similar chemical properties. The lattice constant (atomic radius) has a relationship of carbon <silicon <germanium. The presence of carbon or germanium or both in the interface region IA1 allows carbon or germanium to enter the lattice positions or interstitial positions of the silicide and silicon layers in the silicide / silicon interface region, thereby causing crystal defects. It will be resolved. As a result, stress due to the difference in lattice constant between the silicon layer and the silicide layer can be reduced. That is, the group 4 elements such as carbon and germanium in the vicinity of the interface move and redistribute so as to relax the strain energy of the silicide / silicon interface during the heat treatment so that a concentration distribution peak exists in the interface region IA1. Distributed. As a result, roughness and lattice defects in the interface region IA1 are alleviated, and junction leakage can be suppressed.

  The distribution state of group 4 elements other than silicon depends on the atomic radius (lattice constant) of the group 4 element, the type of silicide layer, and the like. That is, Group 4 elements other than silicon redistribute so as to minimize the strain energy of the silicide / silicon interface during the formation of silicide, and therefore, when present at the same lattice position as silicon and at the interstitial position of silicon. May exist. In the case of carbon having an atomic radius smaller than that of silicon, a layer having a smaller lattice plane (layer having a larger lattice constant) is present at a lattice position and a layer having a larger lattice plane (a layer having a smaller lattice constant). Layer) at the interstitial position. On the other hand, in the case of germanium having an atomic radius larger than that of silicon, it can be present at a lattice position in a layer having a larger lattice plane (a layer having a smaller lattice constant). For example, in the example shown in FIG. 2, when the silicide layer 14 is titanium silicide, since titanium silicide has a larger lattice constant than silicon, germanium is more distributed in the interface region on the silicon layer side.

1.2. Manufacturing Method of Semiconductor Device An example of manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 1 and 3 to 7.

  (1) As shown in FIG. 3, a known SOI substrate is prepared. In the SOI substrate, an insulating layer 12 and a silicon layer 14 are stacked on a semiconductor substrate 10. The silicon layer 14 is single crystal silicon.

  (2) As shown in FIG. 4, a gate insulating layer 26 and a gate electrode 28 are formed by a known method. The insulating layer for the gate insulating layer 26 is formed by oxidizing the surface of the silicon layer 14 by, for example, a thermal oxidation method. The gate insulating layer 26 is not limited to a silicon thermal oxide film, and an insulator such as silicon oxynitride or silicon nitride, or a high dielectric such as tantalum oxide can be used. As the gate electrode 28, a metal such as polysilicon, tungsten, or tantalum, or a multi-layered conductive layer having a salicide structure can be used. The gate insulating layer 26 and the gate electrode 28 can be patterned by known lithography and etching using a hard mask 29A made of silicon oxide or the like.

  Next, a sidewall insulating layer 29 is formed. The sidewall insulating layer 29 can be formed by a known method. For example, the sidewall insulating layer 29 is formed by depositing the insulating layer on the entire surface by the CVD method and then performing anisotropic etching such as reactive ion etching, or when the gate electrode 28 is polysilicon. A method of forming a silicon oxide layer on the surface of the gate electrode 28 by oxidation can be used.

(3) As shown in FIG. 5, a SiGe layer 16 is formed on the exposed surface of the silicon layer 14 by epitaxial growth. The film thickness of the SiGe layer 16 is a so-called atomic layer and may be a very thin film having a degree of Ge atoms adhering to the surface or a few angstroms. For the epitaxial growth of the SiGe layer 16, a known chemical vapor deposition method can be used. For example, SiH ₄ and GeH ₄ are used as the reaction gas, argon or nitrogen is used as the carrier gas, the substrate temperature is set to 500 ° C. or more, and the reaction gas is thermally decomposed to form a film. The epitaxial growth method is not limited to this, and a hydrogen reduction method, a molecular beam epitaxial growth method, or the like can be used.

(4) As shown in FIG. 5, a silicon layer 18 is formed on the SiGe layer 16 by epitaxial growth. The film thickness of the silicon layer 18 can be normally 10 to 50 nm, considering that the silicon layer 18 becomes a silicon supply source when forming the silicide layer. A known chemical vapor deposition method can be used for epitaxial growth of the silicon layer 18. As an example, SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , SiH _x Cl _4-x (x = 1 to 4) are used as the reaction gas, argon or nitrogen is used as the carrier gas, and the substrate temperature is set to 800. The reaction gas can be thermally decomposed at a temperature higher than or equal to 0 ° C. to form a film. The epitaxial growth method is not limited to this, and a hydrogen reduction method, a molecular beam epitaxial growth method, or the like can be used.

  (5) As shown in FIG. 6, by using the gate electrode 28 and the sidewall insulating layer 29 as a mask, impurities of a specific conductivity type (n-type in the case of illustration) are ion-implanted through the silicon layer 18 and the SiGe layer 16 by ion implantation. Then, the silicon layer 14 is implanted to form impurity layers 22 and 24 for the source / drain regions. Thereafter, heat treatment is performed to activate the impurities. Although the temperature at this time is not specifically limited, For example, it can carry out at 800-1000 degreeC. This heat treatment can also be performed by a heat treatment when forming a silicide layer later. In that case, the heat treatment for activating the impurities in this step can be omitted.

  (6) Next, a silicide layer is formed. First, as shown in FIG. 7, a metal layer 30 for forming a silicide layer is formed on the entire surface of the substrate. The material of the metal layer 30 is not specifically limited, A well-known silicide material can be used and titanium, cobalt, nickel etc. can be illustrated. The metal layer 30 can be formed by a film forming method such as sputtering, CVD, or vapor deposition. The film thickness of the metal layer 30 is not particularly limited as long as it can supply a sufficient metal to form a predetermined silicide layer.

  (7) As shown in FIG. 1, the silicon layer 18 and the metal layer 30 shown in FIG. 7 are reacted by heating in an inert gas atmosphere to form silicide layers 32 and 34 on the impurity layers 22 and 24. Form.

  The silicide layers 32 and 34 can be formed by a known method. For example, by using rapid thermal annealing or the like, the silicide layers 32 and 34 can be formed by heating the substrate at a temperature at which only the Si and the metal react without causing the metal and the insulating film to react. Thereafter, the unreacted metal layer on the insulating film is removed by wet etching. Furthermore, by performing heat treatment at a high temperature that does not cause agglomeration in the inert gas, the low resistance and stable silicide layers 32 and 34 can be formed. The temperature of these two-step heat treatments depends on the type of metal and the fine pattern size. For example, it can be performed at 550 to 800 ° C. for titanium, 500 to 800 ° C. for cobalt, and 400 to 600 ° C. for nickel.

  By the heat treatment in the silicide process, germanium in the SiGe layer 16 shown in FIG. 7 is redistributed. That is, germanium moves and redistributes during the heat treatment so as to relieve strain energy at the silicide / silicon interface, and is distributed so that a peak of concentration distribution exists in the silicide / silicon interface region IA1 (see FIG. 1). . As a result, roughness and lattice defects in the interface region IA1 are alleviated, and stress due to the difference in lattice constant can be eliminated. If the germanium redistribution of the SiGe layer 16 is not sufficiently performed in the silicide process, further necessary heat treatment can be performed. The temperature of the heat treatment necessary for the redistribution of germanium is, for example, 400 to 800 ° C.

  As described above, according to the manufacturing method of the present embodiment, germanium is contained between the silicon layer 14 (impurity layers 22 and 24) and the silicon layer 18 for forming the silicide layers 32 and 34. By forming a layer, for example, the SiGe layer 16, and then performing a heat treatment (heat treatment in the step (7) in this example), germanium can be distributed so that a peak of concentration distribution exists in the interface region IA1. Thus, the semiconductor device 100 according to the present embodiment can be formed by a relatively simple method.

  In the example of the manufacturing method described above, the SiGe layer is used as a layer containing a group 4 element other than silicon. However, instead of this, a SiC layer or a SiGeC layer can be used. These layers can be formed by a known epitaxial growth method. When the SiC layer is used, carbon exists in the silicide / silicon interface region, and when the SiGeC layer is used, carbon and germanium exist in the silicide / silicon interface region.

In the example of the manufacturing method described above, epitaxial growth is used as a method for forming a layer containing a group 4 element other than silicon, but the method for forming such a layer is not limited to this. For example, instead of forming the SiGe layer 18 by epitaxial growth, germanium can be introduced into the silicon layer 18 by ion implantation to form a layer containing germanium (Si (Ge) layer). The ion implantation can be performed so that the concentration peak of germanium to be implanted is located in the vicinity of the interface between the silicide layers 32 and 34 and the silicon layer 14. The distribution in the depth direction of Ge formed by ion implantation can be controlled by the energy of ion implantation, the dose amount, and the like. The germanium ion implantation can be performed at a low acceleration and a concentration of 1 × 10 ¹⁵ cm ⁻² , for example. Also in this case, germanium can be distributed in the silicide / silicon interface region by the heat treatment in the step of forming the silicide layer (the step (7)) as in the above-described example. When the layer containing a group 4 element other than silicon is a SiC layer or a SiGeC layer, these layers can be similarly formed by ion implantation.

  In the example described above, the silicon layer 14 is used as the semiconductor layer, but a SiGe layer or a SiGeC layer can be used instead of the silicon layer. As the semiconductor layer, a heterostructure in which two or more of a silicon layer, a SiGe layer, and a SiGeC layer are stacked can be used.

2. Second Embodiment The present invention may be a semiconductor device 200 having a source / drain region having an elevated structure as shown in FIG. In the semiconductor device 200 shown in FIG. 8, the same reference numerals are given to substantially the same parts as those of the semiconductor device 100 shown in FIG. 1, and detailed description thereof is omitted.

  A semiconductor device 200 shown in FIG. 8 is different from the first embodiment in that the source / drain regions have an elevated structure. That is, the source / drain region is composed of impurity layers 22 and 24 formed in the silicon layer 14 and a semiconductor layer 17 formed on the silicon layer 14. The semiconductor layer 17 can be formed by known epitaxial growth, and the composition thereof is not particularly limited. The semiconductor layer 17 can be formed by, for example, a silicon layer, a SiGe layer, a SiC layer, a SiGeC layer, or the like. In this example, at least one of group 4 elements other than silicon, such as carbon and germanium, is distributed such that a concentration distribution peak exists in the interface region IA2 between the semiconductor layer 17 and the silicide layers 32 and 34.

  The semiconductor device 200 of the present embodiment can be manufactured by adding the process of forming the semiconductor layer 17 to the manufacturing method described in the first embodiment. That is, a step of forming the semiconductor layer 17 is added after the step (2) of the manufacturing method. When a SiGe layer, SiC layer, or SiGeC layer is used as the semiconductor layer 17, step (3) in the manufacturing method described in the first embodiment also serves as a step of forming the semiconductor layer 17. Can do.

  This embodiment also has the same features as those of the first embodiment and can achieve the same functions and effects.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be applied to a semiconductor device having a silicide layer. For example, in the above-described embodiment, an example using an SOI substrate has been described. However, the present invention can also be applied to a semiconductor device having a so-called bulk silicon layer.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the present invention. The figure which shows typically the concentration distribution of the germanium in a semiconductor layer. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the semiconductor device concerning the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate, 12 Insulating layer, 14 Silicon layer, 16 SiGe layer, 17 Semiconductor layer, 18 Silicon layer, 20 Channel region, 22, 24 Impurity layer, 26 Gate insulating layer, 28 Gate electrode, 29 Side wall insulating layer, 29A Hard mask, 32, 34 silicide layer, IA1, IA2 interface region, 100, 200 semiconductor device

Claims (11)

A semiconductor layer containing at least silicon;
A gate insulating layer formed on the semiconductor layer;
A gate electrode formed on the gate insulating layer;
An impurity layer forming a source / drain region formed in the semiconductor layer;
A silicide layer formed on the impurity layer;
Including
The semiconductor device includes a group 4 element other than silicon in an interface region between the impurity layer and the silicide layer, and the group 4 element has a peak of concentration distribution in the interface region. In claim 1,
The semiconductor device, wherein the group 4 element other than silicon is at least one of carbon and germanium. In claim 1 or 2,
The semiconductor device is a semiconductor device formed on an insulating layer. In any of claims 1 to 3,
The semiconductor device in which the source / drain regions have an elevated structure. In any of claims 1 to 4,
The semiconductor device, wherein the semiconductor layer includes at least one of a Si layer, a SiGe layer, and a SiGeC layer. Forming a gate insulating layer over a semiconductor layer containing at least silicon;
Forming a gate electrode on the gate insulating layer;
Forming an impurity layer for source / drain regions in the semiconductor layer;
Forming a silicide layer on the impurity layer;
Forming a semiconductor layer containing a group 4 element other than silicon on the semiconductor layer before the step of forming the silicide layer;
By redistributing at least the group 4 element other than silicon by heat treatment, the group 4 element other than silicon is present in the interface region between the impurity layer and the silicide layer so as to have a peak of its concentration distribution. Process,
A method for manufacturing a semiconductor device, comprising: In claim 6,
The semiconductor device manufacturing method, wherein the semiconductor layer containing a group 4 element other than silicon is formed by epitaxial growth. In claim 6,
The semiconductor layer containing a group 4 element other than silicon is formed by introducing a group 4 element other than silicon into the semiconductor layer by ion implantation. In any of claims 6 to 8,
The method for manufacturing a semiconductor device, wherein the semiconductor layer includes at least one of a Si layer, a SiGe layer, and a SiGeC layer. In any of claims 6 to 9,
The method for manufacturing a semiconductor device, wherein the semiconductor layer is formed on an insulating layer. In any of claims 6 to 10,
The method for manufacturing a semiconductor device, wherein the source / drain regions have an elevated structure.

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