JP2005175082A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a good hetero structure that a crystal defect or the roughness of an interface is improved and having stable characteristics, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device 100 includes a semiconductor layer, a gate insulating layer 26 formed on the semiconductor layer, and a gate electrode 28 formed on the gate insulating layer 26. The semiconductor layer has a hetero structure that a first layer (SiGe layer 14) containing at least Si and Ge, and a second layer (Si layers 13, 16) having a composition different from the first layer and containing at least an Si are laminated in such a manner that a carbon exists in the interface region between the first layer and the second layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a semiconductor layer has a heterostructure and a method for manufacturing the same.

For the purpose of further speeding up the operation of the semiconductor device, it is known to increase the carrier mobility by using a strained silicon layer in the channel region of the MOSFET. That is, by adopting a heterostructure consisting of a Si layer and a SiGe layer (or SiGeC layer) in the channel region, the Si layer is strained based on the difference in lattice constant between the Si layer and the SiGe layer (or SiGeC layer). Thus, by changing the energy band structure of the Si layer, electron mobility and hole mobility can be increased. As a technique using such a strained Si layer, for example, there is JP-A-2002-237590.
JP 2002-237590 A

  For example, in a semiconductor device having a heterostructure composed of a Si layer and a SiGe layer (or SiGeC layer), the crystal distortion caused by the difference in lattice constant between the Si layer and the SiGe layer (or SiGeC layer) is the interface region of the heterostructure. It is remarkable. Such a semiconductor device has a problem that steep stress is generated at the interface of the heterostructure, particularly during heat treatment, and thus crystal defects and roughness of the interface are likely to occur due to strain. Crystal defects and interface roughness in such a heterostructure cause, for example, leakage current.

  An object of the present invention is to provide a semiconductor device having a good heterostructure in which such problems are solved, crystal defects and interface roughness are improved, and stable characteristics, and a method for manufacturing the same.

A semiconductor device according to the present invention is a semiconductor device including a semiconductor layer, a gate insulating layer formed on the semiconductor layer, and a gate electrode formed on the gate insulating layer,
The semiconductor layer has a heterostructure in which a first layer containing at least Si or Ge and a second layer having a composition different from that of the first layer and containing at least Si or Ge are stacked,
Carbon exists in the interface region between the first layer and the second layer.

  According to this semiconductor device, since carbon exists in the interface region of the heterostructure, stress in the interface region is relieved, and generation of lattice defects and roughness in the interface region can be suppressed.

  In the semiconductor device of the present invention, the first layer and the second layer can have the following combinations.

  The first layer is any one of Si, Ge, SiGe, SiGeC, and SiC, and the second layer is any one of Si, Ge, SiGe, SiGeC, and SiC having a composition or composition ratio different from that of the first layer. Layer.

  In the semiconductor device of the present invention, the carbon may have a concentration distribution peak in an interface region between the first layer and the second layer.

  In the semiconductor device of the present invention, the semiconductor layer can be formed on an insulating layer, and an SOI substrate can be used.

  In the semiconductor device of the present invention, the interface region may be present in at least one of a channel region and a source / drain region or in the vicinity thereof. The presence of the interface region in such a region can reduce defects in the depletion layer region. In the semiconductor device of the present invention, the source / drain region may have an elevated structure, and the interface region may exist in the source / drain region.

The manufacturing method according to the present invention includes:
A method for manufacturing a semiconductor device, comprising: a semiconductor layer; a gate insulating layer formed on the semiconductor layer; and a gate electrode formed on the gate insulating layer,
In the formation of the semiconductor layer,
Forming a first layer containing at least Si or Ge;
Forming a second layer having a composition different from that of the first layer and containing at least Si or Ge;
Forming a third layer containing carbon on the first layer or the second layer between the step of forming the first layer and the step of forming the second layer;
Performing a heat treatment to cause a higher concentration of carbon in the interface region between the first layer and the second layer than in other regions;
including.

  According to this manufacturing method, it is possible to obtain the semiconductor device of the present invention in which a higher concentration of carbon is present in the interface region between the first layer and the second layer than in other regions by a relatively simple process. it can.

  In the production method of the present invention, the third layer containing carbon can be formed by, for example, the following method.

  The third layer can be formed by epitaxial growth. In this case, the third layer may be a SiC layer. The third layer can be formed by introducing carbon into the first layer or the second layer by ion implantation.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1. 1. First embodiment 1.1. Semiconductor Device FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to the present embodiment.

  The semiconductor device 100 is configured using an SOI (Silicon On Insulator) substrate, and the semiconductor layer has a heterostructure. That is, the semiconductor device 100 includes a semiconductor substrate 10, an insulating layer 12 formed on the semiconductor substrate 10, and a first Si layer 13 formed on the insulating layer 12. On the first Si layer 13, a SiGe layer 14 and a second Si layer 16 are formed in this order. In the heterostructure of this example, the second Si layer 16 and the SiGe layer 14 constitute an interface region IA3, and the SiGe layer 14 and the first Si layer 13 constitute a second interface region IA2.

  In the second Si layer 16, a channel region 20 and a first impurity layer 22 and a second impurity layer 24 for source / drain regions located on both sides of the channel region 20 are formed. The first and second impurity layers 22 and 24 are formed so that the lower ends thereof substantially reach the first interface region IA1. That is, the first interface region IA1 is located in contact with or near the channel region 20 and the impurity layers 22 and 24.

  Although not shown in the drawing, the impurity layers 22 and 24 for the source / drain regions may reach the SiGe layer 14 or the Si layer 13. Even in this case, the heterointerface IA1 in the channel region 20 overlaps the depletion layer region of the source / drain region.

  Carbon is present in the first interface region IA1 and the second interface region IA2. As schematically shown in FIG. 2, carbon is distributed in the first interface region IA <b> 1 and the second interface region IA <b> 2 in a state where the concentration distribution peak exists. In FIG. 2, the horizontal axis indicates the depth from the surface of the second Si layer 16, and the vertical axis indicates the carbon concentration.

  A gate insulating layer 26 is formed on the channel region 20. A gate electrode 28 is formed on the gate insulating layer 26. A sidewall insulating layer 29 is formed on the side surface of the gate electrode 28.

  The semiconductor device 100 according to the present embodiment has the following characteristics due to the presence of carbon in the heterostructure SiGe / Si interface region.

  Carbon is the same group 4b element as silicon and germanium, has similar chemical properties, and has the smallest atomic radius among these elements. The lattice constant has a relationship of carbon <silicon <germanium. By the presence of carbon in the interface regions IA1 and IA2, for example, carbon can enter point defects in the SiGe / Si interface region, and crystal defects are eliminated. As a result, stress concentration due to the difference in lattice constant at the interface between SiGe and Si can be reduced. In addition, since carbon has a higher diffusion rate than silicon and germanium, the movement of carbon to the interface regions IA1 and IA2 during heat treatment can relatively suppress the movement of germanium and cause redistribution of germanium. Absent. Therefore, the germanium does not cause roughening of the interface region due to the movement of the heterostructure interface regions IA1 and IA2. Further, the low temperature heat treatment does not cause a change in composition of each layer due to germanium moving to the Si layers 13 and 16.

  In particular, by suppressing the roughening of the interface and the generation of lattice defects in the interface region IA1 adjacent to the impurity layers 22 and 24 constituting the channel region 20 and the source / drain regions, defects in the depletion layer region can be reduced, and leakage Good characteristics with little current can be obtained.

  Further, for the reasons described above, lattice defects and roughness in the interface regions IA1 and IA2 can be reduced, and appropriate strain can be applied to the second Si layer 16 including the channel region 20, so that electron mobility and hole mobility can be provided. And high speed operation is possible.

1.2. Manufacturing Method of Semiconductor Device An example of manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 1 and 3 to 8.

  (1) As shown in FIG. 3, a known SOI substrate is prepared. In the SOI substrate, an insulating layer 12 and a first Si layer 13 are stacked on a semiconductor substrate 10. The first Si layer 13 is single crystal silicon.

(2) As shown in FIG. 4, a first SiC layer 15 is formed on the first Si layer 13 by epitaxial growth. The film thickness of the first SiC layer 15 is a so-called atomic layer and may be about several angstroms. For the epitaxial growth of the first SiC layer 15, a known chemical vapor deposition method can be used. For example, SiH ₄ and SiH ₃ CH ₃ are used as the reaction gas, argon or nitrogen is used as the carrier gas, the substrate temperature is set to 500 ° C. or more, and the reaction gas is thermally decomposed to form a film. The epitaxial growth method is not limited to this, and a hydrogen reduction method, a molecular beam epitaxial growth method, or the like can be used. Further, the carbon atoms may only adhere to the surface of the Si layer 13.

(3) As shown in FIG. 5, the SiGe layer 14 is formed on the first SiC layer 15 by epitaxial growth. The film thickness of the SiGe layer 14 is not particularly limited, but can be 10 to 100 nm in consideration of being able to give an appropriate strain to the second Si layer formed on the SiGe layer 14. For the epitaxial growth of the SiGe layer 14, a known chemical vapor deposition method can be used. For example, SiH ₄ and GeH ₄ are used as the reaction gas, argon or nitrogen is used as the carrier gas, the substrate temperature is set to 500 ° C. or more, and the reaction gas is thermally decomposed to form a film. The epitaxial growth method is not limited to this, and a hydrogen reduction method, a molecular beam epitaxial growth method, or the like can be used. When the SiGe layer 14 is formed by low-temperature epitaxial growth at 500 to 600 ° C., the SiGe layer has the same lattice constant as the underlying Si layer 13 and becomes a strained SiGe layer. Here, when thermal oxidation or high-temperature annealing is performed, the stress in the strained SiGe layer is relaxed due to slippage at the interface between the insulating layer 12 and the first Si layer 13. At the time of stress relaxation of the SiGe layer, since carbon is present at the interface between the SiGe layer 14 and the first Si layer 13, stress concentration on the SiGe / Si interface can be avoided, and the relaxed SiGe layer 14 free from crystal defects can be formed.

  (4) As shown in FIG. 6, a second SiC layer 17 is formed on the SiGe layer 14 by epitaxial growth. The film thickness of the second SiC layer 17 is a so-called atomic layer and may be about several angstroms. Since the epitaxial growth of the second SiC layer 17 is the same as that of the first SiC layer 15, detailed description thereof is omitted.

(5) As shown in FIG. 7, the second Si layer 16 is formed on the second SiC layer 17 by epitaxial growth. The film thickness of the second Si layer 16 is not particularly limited, but can be 1 to 10 nm in consideration of the spread of electrons for the channel region. A known chemical vapor deposition method can be used for the epitaxial growth of the second Si layer 16. For example, SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , SiH _x Cl _4-x (x = 1 to 4) are used as the reaction gas, argon or nitrogen is used as the carrier gas, and the substrate temperature is set to 500. The reaction gas can be thermally decomposed at a temperature higher than or equal to 0 ° C. to form a film. The epitaxial growth method is not limited to this, and a hydrogen reduction method, a molecular beam epitaxial growth method, or the like can be used.

  (6) Next, heat treatment is performed to move the carbon of the first and second SiC layers 15 and 17. The temperature at this time should just be carbon can move by thermal diffusion, for example, can be performed at 400-600 degreeC. By this heat treatment, carbon atoms move to this interface region so as to relax the strain energy at the interface of the heterostructure, and can enter the lattice position of the SiGe layer or the interstitial position of the Si layer at the interface. As a result, crystal defects in the interface region of the heterostructure are eliminated, and stress concentration due to a difference in lattice constant can be reduced. In addition, since carbon has a higher diffusion rate than silicon and germanium, germanium redistribution which causes a problem does not occur. Accordingly, the interface region is not roughened by the movement of germanium through the heterostructure interface. Further, the composition of the layers 14 and 16 due to the movement of germanium to the second Si layer 16 is not caused.

  Through this heat treatment step, as shown in FIG. 8, the laminated body having the first Si layer 13, the SiGe layer 14, and the second Si layer 16 and having carbon distributed in the interface regions IA1 and IA2 of the heterostructure is obtained. Can be obtained.

  (7) As shown in FIG. 1, a gate insulating layer 26 and a gate electrode 28 are formed by a known method. The insulating layer for the gate insulating layer 26 is formed, for example, by oxidizing the surface of the second Si layer 16 by a thermal oxidation method. The gate insulating layer 26 is not limited to a thermal oxide film, and an insulator such as silicon oxynitride or silicon nitride or a high dielectric such as tantalum oxide can be used. As the gate electrode 28, a metal such as polysilicon, tungsten, or tantalum, or a multi-layered conductive layer having a salicide structure can be used. Patterning of the gate insulating layer 26 and the gate electrode 28 can be performed by known lithography and etching.

  Next, as shown in FIG. 1, a sidewall insulating layer 29 is formed as necessary. The sidewall insulating layer 29 can be formed by a known method. For example, the sidewall insulating layer 29 is formed by depositing the insulating layer on the entire surface by CVD and then performing anisotropic etching such as reactive ion etching, or heat if the gate electrode 28 is polysilicon. A method of forming a silicon oxide layer on the surface of the gate electrode 28 by oxidation can be used.

  Further, as shown in FIG. 1, by using the gate electrode 28 and the sidewall insulating layer 29 as a mask, impurities of a specific conductivity type (n-type in the case of illustration) are implanted into the second Si layer 16 by ion implantation. Impurity layers 22 and 24 for the regions are formed. Thereafter, heat treatment is performed to activate the impurities.

  When this heat treatment is sufficiently high, for example, when it is performed at 600 ° C. or higher, the heat treatment (6) described above can be omitted. That is, the heat treatment in this step can simultaneously activate the impurities and diffuse the carbon in the interface regions IA1 and IA2.

  As described above, according to the manufacturing method of the present embodiment, a layer containing carbon, for example, SiC, between the first Si layer 13 and the SiGe layer 14 and between the SiGe layer 14 and the second Si layer 16 is used. By forming the layers 15 and 17, respectively, and then performing heat treatment, carbon can be distributed so that the concentration distribution peaks exist in the heterostructure interface regions IA1 and IA2. Thus, the semiconductor device 100 according to the present embodiment can be formed by a relatively simple method.

In the above-described example, epitaxial growth is used as a method of forming the first and second SiC layers 15 and 17 as the third layer containing carbon. However, the method of forming the SiC layer is not limited to this. For example, instead of forming the first SiC layer 15 and the second SiC layer 17 by epitaxial growth, carbon can be introduced into the surface regions of the first Si layer 13 and the SiGe layer 14 by ion implantation to form a layer containing carbon. Specifically, carbon can be ion-implanted into the surface region of the first Si layer 13 to form a Si (C) layer doped with carbon. Also, carbon can be ion-implanted into the SiGe layer 14 to form a SiGe (C) surface layer doped with carbon. The film thicknesses of these Si (C) layers and SiGe (C) layers can be controlled by the energy of ion implantation, the dose amount, and the like. The ion implantation of carbon can be performed at a low acceleration and a concentration of 1 × 10 ¹⁵ cm ⁻² , for example.

  Also in this case, carbon can be distributed in the interface region of the heterostructure by the heat treatment (the step (6) or the step (8)) as in the above-described example.

Furthermore, in the above-described example, the SiGe layer 14 is formed on the first Si layer 13, but a SiGeC layer can be used instead of the SiGe layer 14. In this case, the SiGeC layer can be formed by using a gas containing carbon as a reactive gas, for example, SiH ₃ CH ₃ or the like, in the epitaxial growth in the step (2). An SiC layer can be used instead of the second Si layer 16. As described above, even when any of the layers 14 and 16 contains carbon, the carbon existing at the lattice points hardly moves in these layers. Therefore, according to the method of the present embodiment, carbon can be localized in the interface regions IA1 and IA2 by forming the third layer and then performing heat treatment.

  In the above embodiment, carbon is localized in the interface regions IA1 and IA2 between the first and second Si layers 13 and 16 and the SiGe layer 14, but on the channel region 20 and the impurity layers 22 and 24 side. Carbon may be present only in the interface region IA1 located.

2. Second Embodiment 2.1. Semiconductor Device FIG. 9 is a cross-sectional view schematically showing a semiconductor device 200 according to the present embodiment.

  The semiconductor device 200 is configured using an SOI substrate, and the semiconductor layer has a heterostructure. That is, the semiconductor device 100 includes the semiconductor substrate 10, the insulating layer 12 formed on the semiconductor substrate 10, and the Si layer 13 formed on the insulating layer 12. A SiGe layer 14 is formed on the Si layer 13. In the heterostructure of this example, the interface region IA3 is configured by the SiGe layer 14 and the Si layer 13.

  In the Si layer 13, a channel region 20 and a first impurity layer 22 a and a second impurity layer 24 a for source / drain regions located on both sides of the channel region 20 are formed. The first and second impurity layers 22 a and 24 a are formed so that the lower ends thereof reach the insulating layer 12. Further, in the SiGe layer 14, a third impurity layer 22b and a fourth impurity layer 24b constituting so-called elevated source / drain regions are formed on the first impurity layer 22a and the second impurity layer 24a, respectively. That is, one impurity layer 22 is formed by the first impurity layer 22a and the third impurity layer 22b, and the other impurity layer 24 is formed by the second impurity layer 24a and the fourth impurity layer 24b. The interface region IA3 constituted by the SiGe layer 14 and the Si layer 13 exists in the impurity layers 22 and 24.

  A gate insulating layer 26 is formed on the channel region 20. A gate electrode 28 is formed on the gate insulating layer 26. A sidewall insulating layer 29 is formed on the side surface of the gate electrode 28.

  Carbon is present in the interface region IA3. As schematically shown in FIG. 10, carbon is distributed in the interface region IA3 in a state where the peak of the concentration distribution exists. In FIG. 10, the horizontal axis indicates the depth from the surface of the SiGe layer 14, and the vertical axis indicates the concentration of carbon.

  The semiconductor device 200 according to the present embodiment has the following characteristics due to the presence of carbon in the heterostructure SiGe / Si interface region.

  Carbon is the same group 4b element as silicon and germanium, has similar chemical properties, and has the smallest atomic radius among these elements. The lattice constant has a relationship of carbon <silicon <germanium. Due to the presence of carbon in the interface region IA3, for example, carbon can enter point defects in the SiGe / Si interface region, and crystal defects are eliminated. As a result, stress due to the difference in lattice constant between SiGe and Si can be alleviated. Further, since carbon has a higher diffusion rate than silicon and germanium, the movement of germanium is relatively suppressed and the redistribution of germanium does not occur when the carbon moves to the interface region IA3 during the heat treatment. Accordingly, the interface region does not become rough due to the movement of germanium through the heterostructure interface region IA3. Further, the composition of each layer is not changed by the movement of germanium to the Si layer 13.

  In particular, by suppressing the roughening of the interface and the generation of lattice defects in the interface region IA3 between the impurity layers 22a and 24a and the impurity layers 22b and 24b constituting the source / drain regions, good characteristics with less junction leakage can be obtained. Can be obtained.

2.2. Manufacturing Method of Semiconductor Device An example of manufacturing the semiconductor device 200 according to the second embodiment will be described with reference to FIGS. 9 and 11 to 15.

  (1) As shown in FIG. 11, a known SOI substrate is prepared. In the SOI substrate, an insulating layer 12 and an Si layer 13 are stacked on a semiconductor substrate 10. The Si layer 13 is single crystal silicon.

  Next, as shown in FIG. 11, a gate insulating layer 26 and a gate electrode 28 are formed by a known method using a hard mask 29A made of, for example, silicon oxide. As the materials of the gate insulating layer 26 and the gate electrode 28, the same materials as described in the first embodiment can be used. Patterning of the gate insulating layer 26 and the gate electrode 28 can be performed by known lithography and etching.

  (2) As shown in FIG. 12, an insulating layer 29a for the sidewall insulating layer is formed. The insulating layer 29a is obtained by a method of forming a silicon oxide layer on the surfaces of the gate electrode 28, the hard mask 29A, and the Si layer 13 by, for example, CVD or thermal oxidation.

  (3) As shown in FIG. 13, the sidewall insulating layer 29 is formed by anisotropically etching the insulating layer 29a shown in FIG. 12, and at least the insulating layer on the Si layer 13 is removed to remove the Si layer 13 To expose the surface.

(4) As shown in FIG. 14, a SiC layer 18 is formed on the exposed surface of the Si layer 13 by epitaxial growth. The film thickness of the SiC layer 18 is a so-called atomic layer and may be about several angstroms. Further, the carbon atoms may only adhere to the surface of the Si layer 13. A known chemical vapor deposition method can be used for epitaxial growth of the SiC layer 18. For example, SiH ₄ and SiH ₃ CH ₃ are used as the reaction gas, argon or nitrogen is used as the carrier gas, the substrate temperature is set to 500 ° C. or more, and the reaction gas is thermally decomposed to form a film. The epitaxial growth method is not limited to this, and a hydrogen reduction method, a molecular beam epitaxial growth method, or the like can be used.

Further, as shown in FIG. 14, the SiGe layer 14 is formed on the SiC layer 18 by epitaxial growth. The film thickness of the SiGe layer 14 is not particularly limited, but can be 10 to 100 nm in consideration of forming a sufficiently deep source / drain region. For the epitaxial growth of the SiGe layer 14, a known chemical vapor deposition method can be used. For example, SiH ₄ and GeH ₄ are used as the reaction gas, argon or nitrogen is used as the carrier gas, the substrate temperature is set to 500 ° C. or more, and the reaction gas is thermally decomposed to form a film. The epitaxial growth method is not limited to this, and a hydrogen reduction method, a molecular beam epitaxial growth method, or the like can be used.

  (5) As shown in FIG. 15, heat treatment is performed to move the carbon of SiC layer 18 shown in FIG. The temperature at this time should just be a thing which carbon can move by thermal diffusion, for example, can be performed at 400-800 degreeC. This heat treatment causes the carbon atoms to move and redistribute so as to stabilize the strain energy at the interface of the heterostructure. As a result, the crystal defects in the heterostructure interface region IA3 are eliminated, and stress due to the difference in lattice constant can be alleviated. In addition, since carbon has a higher diffusion rate than silicon and germanium, germanium redistribution which causes a problem does not occur. Accordingly, the interface region is not roughened by the movement of germanium through the heterostructure interface. Furthermore, the composition of the layers 13 and 14 due to the movement of germanium to the Si layer 13 is not caused.

  Through this heat treatment step, as shown in FIG. 15, it is possible to obtain a stacked body having the Si layer 13 and the SiGe layer 14 and having carbon distributed in the heterostructure interface region IA3.

  (6) As shown in FIG. 9, using the gate electrode 28 and the sidewall insulating layer 29 as a mask, impurities of a specific conductivity type (n-type in the case of illustration) are implanted into the SiGe layer 14 and the Si layer 13 by ion implantation. Thus, impurity layers 22a, 22b, 24a and 24b for the source / drain regions are formed. Thereafter, heat treatment is performed to activate the impurities.

  As described above, according to the manufacturing method according to the present embodiment, a layer containing carbon, for example, the SiC layer 18 is formed between the Si layer 13 and the SiGe layer 14, and then heat treatment is performed, so that the heterostructure The carbon can be distributed so that a concentration distribution peak exists in the interface region IA3. Thus, the semiconductor device 200 according to the present embodiment can be formed by a relatively simple method.

In the example described above, epitaxial growth is used as a method for forming the SiC layer 18 as the third layer containing carbon, but the method for forming the layer containing carbon is not limited to this. For example, instead of forming the SiC layer 18 by epitaxial growth, carbon can be introduced into the surface region of the Si layer 13 by ion implantation to form a layer containing carbon. Specifically, carbon can be ion-implanted into the surface region of the Si layer 13 to form a Si (C) layer doped with carbon. The ion implantation of carbon can be performed at a low acceleration and a concentration of 1 × 10 ¹⁵ cm ⁻² , for example.

  Also in this case, carbon can be distributed in the heterostructure interface region IA3 by the heat treatment (the step (5) or the step (6)) as in the above-described example.

  Furthermore, in the above-described example, the SiGe layer 14 is formed on the Si layer 13, but a SiGeC layer can be used instead of the SiGe layer 14. As a method for forming the SiGeC layer, the same method as described in the first embodiment can be used. An SiC layer can also be used in place of the Si layer 13. As described above, even when any of the layers 13 and 14 contains carbon, the carbon existing at the lattice points hardly moves in these layers. Therefore, according to the method of the present embodiment, carbon atoms are attached to the interface region IA3 by attaching carbon atoms to the interface region having a large strain or forming a third layer containing carbon and then performing heat treatment. Can exist.

  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments and can be applied to a semiconductor device having a heterostructure semiconductor layer. For example, in the above-described embodiment, an example using an SOI substrate has been described. However, the present invention can also be applied to a semiconductor device having a so-called bulk silicon layer.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment of the present invention. The figure which shows typically the density | concentration distribution of the carbon in a semiconductor layer. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 1st Embodiment. Sectional drawing which shows typically the semiconductor device concerning the 2nd Embodiment of this invention. The figure which shows typically the density | concentration distribution of the carbon in a semiconductor layer. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 2nd Embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device concerning 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate, 12 Insulating layer, 13 1st Si layer, Si layer, 14 SiGe layer, 16 2nd Si layer, 15, 17, 18 SiC layer, 20 channel region, 22, 24 Impurity layer, 26 Gate insulating layer, 28 Gate Electrode, 29 Side wall insulating layer, IA1, IA2, IA3 interface region, 100, 200 Semiconductor device

Claims (12)

A semiconductor device comprising: a semiconductor layer; a gate insulating layer formed on the semiconductor layer; and a gate electrode formed on the gate insulating layer,
The semiconductor layer includes a first layer made of a group IV element containing at least Si or Ge, and a second layer made of a group IV element containing a composition or composition ratio different from that of the first layer and containing at least Si or Ge. And has a laminated heterostructure,
A semiconductor device, wherein carbon is present in an interface region between the first layer and the second layer. In claim 1,
The first layer and the second layer are each a semiconductor device composed of any one of Si, Ge, SiGe, SiGeC, and SiC. In claim 1 or 2,
The carbon has a concentration distribution peak in an interface region between the first layer and the second layer. In any of claims 1 to 3,
The semiconductor device is a semiconductor device formed on an insulating layer. In any of claims 1 to 4,
The interface region is a semiconductor device that exists in at least one of a channel region and a source / drain region or in the vicinity thereof. In any of claims 1 to 4,
The semiconductor device, wherein the source / drain region has an elevated structure, and the interface region exists in the source / drain region. A method for manufacturing a semiconductor device, comprising: a semiconductor layer; a gate insulating layer formed on the semiconductor layer; and a gate electrode formed on the gate insulating layer,
In the formation of the semiconductor layer,
Forming a first layer containing at least Si or Ge;
Forming a second layer having a composition or composition ratio different from that of the first layer and containing at least Si or Ge;
Forming a third layer containing carbon on the first layer or the second layer between the step of forming the first layer and the step of forming the second layer;
Performing a heat treatment to cause a higher concentration of carbon in the interface region between the first layer and the second layer than in other regions;
A method for manufacturing a semiconductor device, comprising: In claim 7,
The method for manufacturing a semiconductor device, wherein the third layer is formed by epitaxial growth. In claim 7,
The method for manufacturing a semiconductor device, wherein the third layer is formed by introducing carbon by ion implantation. In any of claims 7 to 9,
The method for manufacturing a semiconductor device, wherein the semiconductor layer is formed on an insulating layer. In any of claims 7 to 10,
The method of manufacturing a semiconductor device, wherein the interface region exists in at least one of a channel region and a source / drain region or in the vicinity thereof. In any of claims 7 to 10,
A method of manufacturing a semiconductor device, wherein a source / drain region has an elevated structure, and the interface region exists in the source / drain region.

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