JP2005167135A - Method for forming conductive pattern, method for forming wiring, method for manufacturing semiconductor device, method for manufacturing circuit board, method for manufacturing electronic component, conductive pattern, wiring, semiconductor device, circuit board, electronic component, and electronic equipment - Google Patents

Method for forming conductive pattern, method for forming wiring, method for manufacturing semiconductor device, method for manufacturing circuit board, method for manufacturing electronic component, conductive pattern, wiring, semiconductor device, circuit board, electronic component, and electronic equipment Download PDF

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JP2005167135A
JP2005167135A JP2003407388A JP2003407388A JP2005167135A JP 2005167135 A JP2005167135 A JP 2005167135A JP 2003407388 A JP2003407388 A JP 2003407388A JP 2003407388 A JP2003407388 A JP 2003407388A JP 2005167135 A JP2005167135 A JP 2005167135A
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conductive
pattern
forming
conductive pattern
wiring
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JP4639586B2 (en
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Nobuaki Hashimoto
伸晃 橋元
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Seiko Epson Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/115Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/1155Selective modification
    • H01L2224/11552Selective modification using a laser or a focussed ion beam [FIB]
    • H01L2224/11554Stereolithography, i.e. solidification of a pattern defined by a laser trace in a photosensitive resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for inexpensively forming a conductive pattern with less facility investment. <P>SOLUTION: The surface of a core member 12 formed by a photo-fabrication technique is plated for its conduction. Using conductive resin (polymer material such as pyrrole exhibiting a metal conductivity or insulating resin such as acryl having conductive fine particles incorporated therein) as the material of the core member, an arbitrary shape of a three-dimensional pattern can be formed only by a core member forming step (photo-fabrication step). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、導電パターンの形成方法、配線の形成方法、半導体装置の製造方法、回路基板の製造方法、電子部品の製造方法、並びに、導電パターン、配線、半導体装置、回路基板、電子部品、電子機器に関する。   The present invention relates to a conductive pattern forming method, a wiring forming method, a semiconductor device manufacturing method, a circuit board manufacturing method, an electronic component manufacturing method, and a conductive pattern, wiring, semiconductor device, circuit board, electronic component, electronic Regarding equipment.

従来、中空配線等の3次元的なパターンは、犠牲層のエッチング等、MEMS技術若しくはその応用技術により形成されていた(例えば特許文献1〜3)。
特開平11−354717号公報 特開2000−269327号公報 特開2001−185821号公報
Conventionally, a three-dimensional pattern such as a hollow wiring has been formed by MEMS technology or its application technology such as etching of a sacrificial layer (for example, Patent Documents 1 to 3).
JP 11-354717 A JP 2000-269327 A JP 2001-185821 A

しかしながら、上述の方法はいずれもフォトリソグラフィ技術を使用するため、工程への設備投資が大きく、プロセスの流動時間も長い。また、MEMS技術によって形成した3次元パターン(例えば中空配線)は、衝撃等に弱く、信頼性の面でも課題があった。
本発明はこのような事情に鑑みてなされたもので、設備投資が少なく安価にパターンを形成することのできる導電パターンの形成方法、配線の形成方法、半導体装置の製造方法、回路基板の製造方法、電子部品の製造方法を提供することを目的とし、更に、衝撃等に対して高い信頼性が得られる導電パターン、配線、半導体装置、回路基板、電子部品、電子機器を提供することを目的とする。
However, since any of the above methods uses photolithography technology, the capital investment for the process is large and the flow time of the process is long. In addition, a three-dimensional pattern (for example, a hollow wiring) formed by the MEMS technique is vulnerable to an impact or the like, and has a problem in terms of reliability.
The present invention has been made in view of such circumstances, and a conductive pattern forming method, a wiring forming method, a semiconductor device manufacturing method, and a circuit board manufacturing method capable of forming a pattern inexpensively with little capital investment. An object of the present invention is to provide a method for manufacturing an electronic component, and further to provide a conductive pattern, a wiring, a semiconductor device, a circuit board, an electronic component, and an electronic device that can obtain high reliability against an impact or the like. To do.

上記の課題を解決するため、本発明の導電パターンの形成方法は、光造形技術により基板上にパターンの芯材を形成する工程と、メッキ技術により上記芯材の表面に導電材料を形成する工程とを備えたことを特徴とする。
本方法では、使用する装置が光造形機とメッキ装置のみで済む(即ち、設備投資が少なくて済む)ため、安価に製品を提供することができる。特に本方法では、光造形技術により任意の立体形状が得られるため、別途抵抗部やキャパシタ等の付加的な構造を追加することも容易であり、デバイスの設計自由度が非常に高い。また、本方法では、従来のフォトリソグラフィ技術で用いるようなマスクが不要であり、製造条件も安定していることから、少量多品種の製造に優れるといった利点もある。さらに、本方法によって形成された導電パターンは芯材が樹脂によって形成されるため、衝撃等に強く、信頼性の高いパターンとなる。逆に、このような樹脂の弾性力を積極的に利用することで、パターン自身に応力緩和機能や弾性変形機能(バネ構造を含む)を付与することもできる。
In order to solve the above problems, the conductive pattern forming method of the present invention includes a step of forming a core material of a pattern on a substrate by an optical modeling technique and a step of forming a conductive material on the surface of the core material by a plating technique. It is characterized by comprising.
In this method, since only the stereolithography machine and the plating apparatus are used (that is, the capital investment is small), the product can be provided at low cost. In particular, in this method, since an arbitrary three-dimensional shape can be obtained by the optical modeling technique, it is easy to add an additional structure such as a resistor or a capacitor, and the degree of freedom in device design is very high. In addition, this method does not require a mask as used in the conventional photolithography technique, and the manufacturing conditions are stable, so that there is an advantage that it is excellent in manufacturing a small variety of products. Furthermore, the conductive pattern formed by this method is resistant to impact and the like and has a high reliability because the core material is formed of resin. Conversely, by actively utilizing the elastic force of such a resin, a stress relaxation function and an elastic deformation function (including a spring structure) can be imparted to the pattern itself.

なお、本方法で得られる導電パターンでは、導電パスはパターンの表面部のみに形成されるため、従来のもの(導電パスがパターン全体で形成されるもの)に比べて抵抗が若干大きくなるが、この導電パターンを例えば高周波伝送等に利用する場合には、電気伝導はパターンの表面部のみで生じる(表皮効果)ため、特に問題にはならない。   In the conductive pattern obtained by this method, since the conductive path is formed only on the surface portion of the pattern, the resistance is slightly larger than the conventional one (the conductive path is formed by the entire pattern), When this conductive pattern is used, for example, for high-frequency transmission, electrical conduction occurs only on the surface portion of the pattern (skin effect), so there is no particular problem.

また、本発明の導電パターンの製造方法は、導電性の樹脂を用いて光造形技術により基板上に所定のパターンを形成することを特徴とする。
本方法では、別途樹脂の表面に導電材料を形成する必要がないため、より簡単に所望のパターンを得ることができる。また、こうして得られた導電パターンでは導電パスはパターン全体に形成されるため、パターン表層部にのみ導電パスが形成される上述の構成に比べて良好な電気的特性が得られる。なお、上述の導電性の樹脂としては、例えばピロール等の金属導電性を示す高分子材料を用いることができる。或いは、アクリル等の絶縁性の高分子材料に導電性微粒子を練り込んだものを用いてもよい。
Moreover, the manufacturing method of the conductive pattern of this invention forms a predetermined pattern on a board | substrate with an optical modeling technique using electroconductive resin.
In this method, it is not necessary to separately form a conductive material on the surface of the resin, so that a desired pattern can be obtained more easily. Further, in the conductive pattern thus obtained, the conductive path is formed over the entire pattern, so that better electrical characteristics can be obtained than in the above-described configuration in which the conductive path is formed only in the pattern surface layer portion. As the above-described conductive resin, for example, a polymer material exhibiting metal conductivity such as pyrrole can be used. Alternatively, a material obtained by kneading conductive fine particles in an insulating polymer material such as acrylic may be used.

また、本発明の導電パターンの形成方法は、導電層の上に該導電層と電気的に接続された導電パターンを形成する方法であって、光造形技術により、上記導電層上にパターン本体の形状をなす第1の芯部と、該第1の芯部と上記導電層とを接続するための第2の芯部とを一体に形成する工程と、メッキ技術により、上記第1の芯部と第2の芯部とを含む芯材の表面に導電材料を形成する工程とを備えたことを特徴とする。
本方法によれば、導電層上に層間絶縁膜を形成せずに直接導電パターンを形成できるため、導電層とパターン本体部との間に生じる寄生容量を十分小さくすることができる。このため、本構造を多層配線に適用した場合には、配線間に層間絶縁膜がない所謂中空配線と呼ばれる理想的な配線形態を実現することができる。通常、このような中空配線では十分な機械的強度は得られないが、本方法で形成されるパターンは芯材が樹脂で構成されるため、従来の無機材料のみからなる導電パターンと違って、パターン本体部と導電層との間に補強材(層間絶縁膜等)がなくても簡単に破損することはない。
The conductive pattern forming method of the present invention is a method of forming a conductive pattern electrically connected to the conductive layer on the conductive layer, and the pattern main body is formed on the conductive layer by stereolithography. A step of integrally forming a first core portion having a shape and a second core portion for connecting the first core portion and the conductive layer; and the first core portion by a plating technique. And a step of forming a conductive material on the surface of the core material including the second core portion.
According to this method, since the conductive pattern can be directly formed without forming the interlayer insulating film on the conductive layer, the parasitic capacitance generated between the conductive layer and the pattern main body can be sufficiently reduced. For this reason, when this structure is applied to a multilayer wiring, an ideal wiring form called a so-called hollow wiring having no interlayer insulating film between the wirings can be realized. Normally, sufficient mechanical strength cannot be obtained with such a hollow wiring, but the pattern formed by this method is composed of a resin core material, so unlike a conductive pattern made of only a conventional inorganic material, Even if there is no reinforcing material (interlayer insulating film or the like) between the pattern body and the conductive layer, it is not easily damaged.

また、本発明の導電パターンの形成方法は、導電層の上に該導電層と電気的に接続された導電パターンを形成する方法であって、導電性の樹脂を用いて光造形技術により、上記導電層上にパターン本体となる第1の導電部と、該第1の導電部と上記導電層とを接続するための接続プラグとなる第2の導電部とを一体に形成することを特徴とする。
本方法では、別途樹脂の表面に導電材料を形成する必要がないため、より簡単に中空配線等の3次元パターンを形成することができる。
Further, the conductive pattern forming method of the present invention is a method of forming a conductive pattern electrically connected to the conductive layer on the conductive layer, wherein the above-mentioned method is performed by stereolithography using a conductive resin. A first conductive part serving as a pattern body and a second conductive part serving as a connection plug for connecting the first conductive part and the conductive layer are integrally formed on the conductive layer. To do.
In this method, it is not necessary to separately form a conductive material on the surface of the resin, so that a three-dimensional pattern such as a hollow wiring can be more easily formed.

また、本発明の配線の形成方法,半導体装置の製造方法、回路基板の製造方法、電子部品の製造方法は、上述の方法により形成された導電パターンを用いてそれぞれ配線、半導体装置、回路基板、電子部品を形成又は製造することを特徴とする。
これにより、これらの部材や部品をより安価に提供することができる。
The wiring forming method, the semiconductor device manufacturing method, the circuit board manufacturing method, and the electronic component manufacturing method according to the present invention each include a wiring, a semiconductor device, a circuit board, An electronic component is formed or manufactured.
Thereby, these members and parts can be provided more inexpensively.

また、本発明の導電パターンは、3次元的な形状を有する樹脂製の芯材と、この芯材の表面を被覆する導電材料とを備えたことを特徴とする。
本発明では、導電パターンの芯材を樹脂によって構成しているため、衝撃等に対して信頼性の高いパターンが得られる。逆に、樹脂の弾性力を積極的に利用することで、該導電パターンに応力緩和機能や弾性変形機能を付与することも可能である。
In addition, the conductive pattern of the present invention includes a resin-made core material having a three-dimensional shape and a conductive material covering the surface of the core material.
In the present invention, since the core material of the conductive pattern is made of resin, a highly reliable pattern can be obtained with respect to impact or the like. On the contrary, it is possible to impart a stress relaxation function and an elastic deformation function to the conductive pattern by positively utilizing the elastic force of the resin.

また、本発明の導電パターンは、導電層に電気的に接続された導電パターンであって、パターン本体の形状をなす第1の芯部と、該第1の芯部と上記導電層とを接続するための第2の芯部とが一体に形成された樹脂製の芯材と、この芯材の表面を被覆する導電材料とを備えたことを特徴とする。
本構成では、導電パターンの芯材を樹脂によって構成しているため、十分な機械的強度が得られる。このため、導電層と導電パターンとの間を空洞(即ち、空気層)にして、これらの間の寄生容量を小さくすることができる。
The conductive pattern of the present invention is a conductive pattern electrically connected to the conductive layer, and connects the first core portion forming the pattern body, and the first core portion and the conductive layer. And a second core part formed integrally with a resin core material and a conductive material covering the surface of the core material.
In this configuration, since the core material of the conductive pattern is made of resin, sufficient mechanical strength can be obtained. For this reason, a space (that is, an air layer) is formed between the conductive layer and the conductive pattern, and the parasitic capacitance between them can be reduced.

また、本発明の配線、半導体装置、回路基板、電子部品、電子機器は、上述の導電パターンを備えたことを特徴とする。
これにより、機械的信頼性の高い部材や部品,機器を提供することができる。
Moreover, the wiring, semiconductor device, circuit board, electronic component, and electronic device of the present invention are characterized by including the above-described conductive pattern.
As a result, it is possible to provide members, parts, and equipment with high mechanical reliability.

以下、図面を参照しながら本発明の実施の形態について説明する。
本発明は、光造形技術によってパターンの芯材を形成し、この芯材の表面にメッキを施すことで導電化するものである。
図1は,本発明の電電パターンの形成方法の一例を示す工程図である。なお、以下の全ての図面においては、図面を見やすくするため、各構成要素の膜厚や寸法の比率などは適宜異ならせてある。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the present invention, a pattern core material is formed by stereolithography, and the surface of the core material is plated to make it conductive.
FIG. 1 is a process diagram showing an example of a method for forming an electric pattern of the present invention. In all the drawings below, the film thicknesses and dimensional ratios of the constituent elements are appropriately changed in order to make the drawings easy to see.

本例では、まず図1(a)に示すように、パターンの形成対象となる基板10を用意する。基板10の材料は、その目的に応じて種々のものを選択することができる。例えば光透過性が求められる場合にはガラス等の透光性材料が選択され、可撓性が求められる場合には樹脂材料等が選択される。また、半導体素子を形成する場合にはシリコンウェハ等の半導体基板が選択される。さらに、基板10は、複数の導電膜(配線層)と絶縁膜とが予め積層された多層配線基板や回路基板若しくはICチップ等であってもよい。本例では、基板10を、表面に電極又はランド(導電層)11を備えたICチップとし、このICチップ10の導電層11に再配置配線を形成する場合について説明する。   In this example, first, as shown in FIG. 1A, a substrate 10 to be a pattern formation target is prepared. Various materials can be selected for the substrate 10 according to the purpose. For example, a light-transmitting material such as glass is selected when light transmission is required, and a resin material or the like is selected when flexibility is required. When forming a semiconductor element, a semiconductor substrate such as a silicon wafer is selected. Further, the substrate 10 may be a multilayer wiring board, a circuit board, an IC chip or the like in which a plurality of conductive films (wiring layers) and an insulating film are laminated in advance. In this example, a case will be described in which the substrate 10 is an IC chip having electrodes or lands (conductive layers) 11 on the surface, and rearrangement wiring is formed on the conductive layer 11 of the IC chip 10.

このように基板10に対して、本発明では、図1(b)に示すように、光造形技術により3次元形状の樹脂製の芯材12を形成する。この芯材12は、配線本体(パターン本体)の形状をなす第1の芯部12aと、この第1の芯部12aと導電層11とを接続するための第2の芯部12bとを一体に備えている。また、本例では必要に応じて更に第1の芯部12aの端部に、端子電極又はランドの形状をなす第3の芯部12cを一体に設けることもできる。   As described above, in the present invention, as shown in FIG. 1B, a three-dimensional resin core 12 is formed on the substrate 10 by an optical modeling technique. The core material 12 is formed by integrating a first core portion 12a having a shape of a wiring main body (pattern main body) and a second core portion 12b for connecting the first core portion 12a and the conductive layer 11 together. In preparation. In this example, a third core portion 12c having a terminal electrode or land shape can be integrally provided at the end portion of the first core portion 12a as necessary.

このような芯材12は図2に示すような光造形装置によって形成することができる。図2において、光造形装置100は、レーザ光源101と、基板支持用のステージ102と、基板10に芯材の材料となる樹脂Rを吐出するためのマイクロディスペンサ103とを備えている。この光造形装置100は、レーザ照射によって樹脂層の所定の部位を選択的に硬化させることで、任意の形状の芯材を形成できるようになっている。
ここで、樹脂Rとしては光硬化性樹脂(感光性樹脂)及び熱硬化性樹脂のいずれを用いることもできる。本例では、例えばアクリル等の絶縁性の感光性樹脂(光硬化性樹脂)を用いる。レーザ光源101の出力波長や出力強度はこの樹脂Rの硬化特性(光反応特性、熱反応特性)に応じて最適に設定される。
Such a core material 12 can be formed by an optical modeling apparatus as shown in FIG. In FIG. 2, the optical modeling apparatus 100 includes a laser light source 101, a substrate supporting stage 102, and a microdispenser 103 for discharging a resin R as a core material onto the substrate 10. This stereolithography apparatus 100 can form a core material having an arbitrary shape by selectively curing a predetermined portion of the resin layer by laser irradiation.
Here, as the resin R, any of a photocurable resin (photosensitive resin) and a thermosetting resin can be used. In this example, an insulating photosensitive resin (photocurable resin) such as acrylic is used. The output wavelength and output intensity of the laser light source 101 are optimally set according to the curing characteristics (photoreaction characteristics and thermal reaction characteristics) of the resin R.

ステージ102は、基板10を支持した状態でX軸方向及びY軸方向に移動可能に設けられており、基板10はステージ102の移動により光源101から射出された光束に対して移動可能となっている。また、ステージ102はZ軸方向にも移動可能となっている。ここで、光源101とステージ102に支持された基板10との間には不図示の光学系が配置されている。基板10を支持したステージ102はZ軸方向に移動することにより、前記光学系の焦点に対する基板10の位置を調整可能となっている。そして、光源101より射出された光束は、ステージ102に支持されている基板10を照射するようになっている。   The stage 102 is provided so as to be movable in the X-axis direction and the Y-axis direction while supporting the substrate 10, and the substrate 10 is movable with respect to the light beam emitted from the light source 101 by the movement of the stage 102. Yes. The stage 102 can also move in the Z-axis direction. Here, an optical system (not shown) is disposed between the light source 101 and the substrate 10 supported by the stage 102. The stage 102 that supports the substrate 10 moves in the Z-axis direction so that the position of the substrate 10 with respect to the focal point of the optical system can be adjusted. The light beam emitted from the light source 101 irradiates the substrate 10 supported by the stage 102.

次に、図3を参照しながら具体的な芯材の形成手順について説明する。
まず、図3(a)に示すように、マイクロディスペンサ103によって基板上の所定の領域に樹脂層R1を形成し、この樹脂層R1に対して所定の光束径を有するレーザ光束を部分的に照射する。これにより、図3(b)に示すように、樹脂層R1はレーザの照射領域に対応して部分的に硬化され、この硬化された樹脂層によって第2の芯部12bが形成される。
Next, a specific procedure for forming the core material will be described with reference to FIG.
First, as shown in FIG. 3A, a resin layer R1 is formed in a predetermined region on the substrate by the microdispenser 103, and a laser beam having a predetermined beam diameter is partially irradiated to the resin layer R1. To do. Thereby, as shown in FIG. 3B, the resin layer R1 is partially cured corresponding to the laser irradiation region, and the second core portion 12b is formed by the cured resin layer.

次に、第2の芯部12bを形成したのと同様の手順により、樹脂層R1の上に第1の芯部12aを形成する。すなわち、マイクロディスペンサ103によって樹脂層R1(第2の芯部12bを含む)の上に樹脂層R2を形成し、レーザ照射によって、第2の芯部12bの形成領域を含む所定の領域の樹脂層R2を選択的に硬化する。この工程により、第1の樹脂層R1の上に、硬化樹脂からなる第1の芯部12aが第2の芯部12bと一体に形成される。
そして、このように下層側から第2の芯部12bと第1の芯部12とを順に形成した後、現像処理により未硬化部分の樹脂層を除去する。これにより、基板10上に3次元形状を有する芯材が形成される。なお、第1の芯部12aの上に第3の芯部12cを形成する場合には、図3(d)の工程の後に、第2の芯部12b及び第1の芯部12aを形成したのと同様の手順を繰り返せばよい。
Next, the first core portion 12a is formed on the resin layer R1 by the same procedure as that for forming the second core portion 12b. That is, the resin layer R2 is formed on the resin layer R1 (including the second core portion 12b) by the microdispenser 103, and the resin layer in a predetermined region including the region where the second core portion 12b is formed by laser irradiation. R2 is selectively cured. By this step, the first core portion 12a made of a cured resin is formed integrally with the second core portion 12b on the first resin layer R1.
And after forming the 2nd core part 12b and the 1st core part 12 in order from a lower layer side in this way, the resin layer of an unhardened part is removed by image development processing. As a result, a core material having a three-dimensional shape is formed on the substrate 10. In addition, when forming the 3rd core part 12c on the 1st core part 12a, the 2nd core part 12b and the 1st core part 12a were formed after the process of FIG.3 (d). The same procedure as above may be repeated.

図1に戻って芯材形成後の工程について説明する。
図3のようにして芯材12が形成されたら、今度はメッキ技術により、この芯材12の表面に導電材料を形成する。具体的には、液相法(ディップ法や液滴吐出法等)により芯材12の表面に塩化パラジウム等の触媒を形成し、無電解メッキにより導電薄膜(導電材料)13を堆積させる(図1(c))。
Returning to FIG. 1, the process after the core material is formed will be described.
When the core material 12 is formed as shown in FIG. 3, a conductive material is formed on the surface of the core material 12 by a plating technique. Specifically, a catalyst such as palladium chloride is formed on the surface of the core material 12 by a liquid phase method (dip method, droplet discharge method, etc.), and a conductive thin film (conductive material) 13 is deposited by electroless plating (FIG. 1 (c)).

以上により、導電層11の上に、配線本体(パターン本体)となる第1の導電部14aと、該第1の導電部14aと上記導電層11とを接続するための接続プラグとなる第2の導電部14bとを一体に備えた配線1が形成される。この配線1は、配線本体である第1の導電部14aの下層側に層間絶縁膜等が配置されない(即ち、配線本体の下が空気層となる)、所謂中空配線構造を有することから、理想的な電気的特性が得られるようになっている。通常、このような中空配線では十分な機械的強度は得られないが、本例の配線は配線芯が樹脂によって構成されるため、従来の無機材料のみからなる導電パターンと違って、パターン本体部と導電層との間に補強材(層間絶縁膜等)がなくても簡単に破損することはない。
このように形成された配線1には、図1(d)に示すように、配線端部に形成された端子電極又はランド13aの上に半田バンプ20が形成され、このバンプ20を介して外部素子と電気的に接続されることとなる。
As described above, on the conductive layer 11, the first conductive portion 14 a serving as a wiring main body (pattern main body), and the second plug serving as a connection plug for connecting the first conductive portion 14 a and the conductive layer 11. The wiring 1 integrally including the conductive portion 14b is formed. This wiring 1 has a so-called hollow wiring structure in which an interlayer insulating film or the like is not disposed on the lower layer side of the first conductive portion 14a which is a wiring body (that is, an air layer is formed under the wiring body), so that the wiring 1 is ideal. Electrical characteristics can be obtained. Normally, sufficient mechanical strength cannot be obtained with such a hollow wiring, but the wiring core of this example is made of a resin, so that the pattern body is different from the conventional conductive pattern made of only inorganic materials. Even if there is no reinforcing material (interlayer insulating film or the like) between the conductive layer and the conductive layer, it is not easily damaged.
In the wiring 1 formed in this way, as shown in FIG. 1D, solder bumps 20 are formed on the terminal electrodes or lands 13a formed at the ends of the wiring, and externally connected via the bumps 20. It is electrically connected to the element.

以上説明したように、本発明では、使用する装置が光造形機とメッキ装置のみで済む(即ち、設備投資が少なくて済む)ため、安価に製品を提供することができる。また、本方法では、従来のフォトリソグラフィ技術で用いるようなマスクが不要であり、製造条件も安定していることから、少量多品種の製造に優れるといった利点もある。
また、本方法によって形成された導電パターンは芯材が樹脂によって形成されるため、衝撃等に強く、信頼性の高いパターンとなる。逆に、このような樹脂の弾性力を積極的に利用することで、パターン自身に応力緩和機能や弾性変形機能(バネ構造を含む)を付与することもできる。このような樹脂の弾性力が有効に発揮される形態としては、以下のものが挙げられる。
As described above, according to the present invention, since only the optical modeling machine and the plating apparatus are used (that is, the capital investment is small), the product can be provided at low cost. In addition, this method does not require a mask as used in the conventional photolithography technique, and the manufacturing conditions are stable, so that there is an advantage that it is excellent in manufacturing a small variety of products.
Moreover, since the core material is formed of resin, the conductive pattern formed by this method is resistant to impact and the like and has a high reliability. Conversely, by actively utilizing the elastic force of such a resin, a stress relaxation function and an elastic deformation function (including a spring structure) can be imparted to the pattern itself. Examples of the form in which the elastic force of such a resin is effectively exhibited include the following.

図4は、本発明の導電パターンの形成方法を用いて製造した電子部品の一例であるプローブカード2の要部構造を示す断面図である。プローブカード2は、半導体装置や液晶装置等の電気特性検査を行なうための触針器具であり、端子電極(導電層)11を有するプローブ基板10と、この電極11の上に形成された検査針としてのプローブ17とを備えている。プローブ基板10には電極11の形成位置に貫通電極(図示略)が形成されており、この貫通電極及び電極11を介して、基板裏面側に配置された検査装置本体(テスター)からプローブ17に対して検査信号が供給されるようになっている。   FIG. 4 is a cross-sectional view showing the main structure of a probe card 2 which is an example of an electronic component manufactured using the method for forming a conductive pattern of the present invention. The probe card 2 is a stylus instrument for inspecting electrical characteristics of a semiconductor device, a liquid crystal device or the like, and includes a probe substrate 10 having a terminal electrode (conductive layer) 11 and an inspection needle formed on the electrode 11. As a probe 17. A through electrode (not shown) is formed on the probe substrate 10 at a position where the electrode 11 is formed, and the probe 17 is connected to the probe 17 from the inspection apparatus body (tester) arranged on the back side of the substrate via the through electrode and the electrode 11. On the other hand, an inspection signal is supplied.

このプローブ17は、プローブ本体(パターン本体)である第1の導電部17aと、この第1の導電部17aと電極11とを接続するための接続プラグとなる第2の導電部17bと、これら第1の導電部17aと第2の導電部17bとを繋ぐ第3の導電部17cとを備えており、例えば図1に示した配線1の形成方法と同様の手順によって形成されている。すなわち、まず基板10上に、光造形技術を用いて3次元的な形状を有する樹脂製の芯材15を形成する。この際、芯材15は、例えばプローブ本体17aの形状をなす第1の芯部15aと、この第1の芯部15aと電極11とを接続するための第2の芯部15bと、これらの芯部15a及び15bを繋ぐための第3の芯部15cとを、下層側のものから順に形成する。そして、この工程により一体に形成された第1の芯部15a,第2の芯部15b,第3の芯部15c(即ち、芯材15)にメッキ処理を施して、芯材15の表面を導電材料16によって被覆する。   The probe 17 includes a first conductive portion 17a which is a probe main body (pattern main body), a second conductive portion 17b which is a connection plug for connecting the first conductive portion 17a and the electrode 11, and these A third conductive portion 17c that connects the first conductive portion 17a and the second conductive portion 17b is provided. For example, the first conductive portion 17a and the second conductive portion 17b are formed by the same procedure as the method for forming the wiring 1 shown in FIG. That is, first, a resin core material 15 having a three-dimensional shape is formed on the substrate 10 using an optical modeling technique. At this time, the core material 15 includes, for example, a first core portion 15a having the shape of the probe main body 17a, a second core portion 15b for connecting the first core portion 15a and the electrode 11, and these A third core portion 15c for connecting the core portions 15a and 15b is formed in order from the lower layer side. Then, the first core portion 15a, the second core portion 15b, and the third core portion 15c (that is, the core material 15) integrally formed by this process are plated so that the surface of the core material 15 is Cover with conductive material 16.

本例のプローブ17は芯材が樹脂によって構成されているため、単に基板に検査針を埋め込んだだけの従来のプローブに比べて、弾力性に富んだ構造となっている。このため、検査針17aを半導体装置や液晶装置の端子部に接触させた場合に、この検査針17aと接続プラグ17bとの連結部である第2の導電層17cが弾性変形し、接触時の応力を緩和することができる(応力緩和機能)。このように本例によれば、被測定側の端子を傷つけることなく当該端子との間で良好な密着性が得られることから、高い精度の検査を行なうことが可能となる。また、極めて柔軟性の高い構造が得られることから、相手側端子との接触時に、その衝撃でプローブ17が破損する虞が少なくなる。
なお、樹脂の弾性力が有効に発揮される例としては、この他にも、例えばDMD等で用いられるような可動性のミラーデバイス等を挙げることができる。このような素子を本発明の方法によって形成することで、デバイスの高性能化及び低コスト化を図ることができる。
Since the core material of the probe 17 of this example is made of resin, the probe 17 has a structure rich in elasticity as compared with a conventional probe in which an inspection needle is simply embedded in a substrate. For this reason, when the inspection needle 17a is brought into contact with the terminal portion of the semiconductor device or the liquid crystal device, the second conductive layer 17c, which is a connecting portion between the inspection needle 17a and the connection plug 17b, is elastically deformed, Stress can be relaxed (stress relaxation function). As described above, according to this example, it is possible to obtain a high-accuracy inspection because good adhesion can be obtained between the terminals to be measured without damaging the terminals to be measured. In addition, since an extremely flexible structure can be obtained, there is less possibility that the probe 17 will be damaged by the impact at the time of contact with the counterpart terminal.
In addition, as an example in which the elastic force of the resin is effectively exhibited, for example, a movable mirror device used in DMD or the like can be cited. By forming such an element by the method of the present invention, high performance and low cost of the device can be achieved.

また、本発明の導電パターンの形成方法では、光造形技術により任意の立体形状が得られるため、例えば図5に示すように配線18の一部を渦巻状とすることで、インダクタ18(図中、符号17は配線3の芯材を示す)等の構造を付加することも容易となる。勿論、平板状の配線を重ねてキャパシタを形成したり、抵抗部を形成することもできる。このように本発明によれば、デバイスの設計自由度も格段に高くなり、デバイスの高機能化を図ることが可能となる。   Further, in the method for forming a conductive pattern of the present invention, an arbitrary three-dimensional shape can be obtained by the optical modeling technique. For example, by forming a part of the wiring 18 in a spiral shape as shown in FIG. It is also easy to add a structure such as (17 indicates a core material of the wiring 3). Of course, a capacitor can be formed by overlapping flat wirings, and a resistance portion can be formed. As described above, according to the present invention, the degree of freedom of device design is also greatly increased, and it is possible to improve the functionality of the device.

次に、本発明の導電パターンを有する配線又は半導体装置を備えた回路基板及び電子機器について説明する。
図6は本発明の回路基板の一実施形態の概略構成を示す斜視図である。図6に示すようにこの実施形態の回路基板5には、前述の再配置配線を備えたICチップを3次元実装してなる半導体装置4が搭載されている。回路基板5は、例えばガラスエポキシ基板等の有機系基板からなるもので、例えば銅等からなる配線パターン(図示せず)が所望の回路となるように形成され、さらにこれら配線パターンに電極パッド(図示せず)が接続されている。そして、この電気パッドに半導体装置4におけるインターポーザ基板のハンダボールが電気的に接続されることにより、半導体装置4は回路基板5上に実装されたものとなっている。なお、回路を構成する配線パターンを本発明の方法により形成することも可能である。
Next, a circuit board and an electronic device including a wiring or a semiconductor device having a conductive pattern according to the present invention will be described.
FIG. 6 is a perspective view showing a schematic configuration of an embodiment of the circuit board of the present invention. As shown in FIG. 6, on the circuit board 5 of this embodiment, a semiconductor device 4 in which an IC chip having the above-described rearrangement wiring is three-dimensionally mounted is mounted. The circuit board 5 is made of an organic substrate such as a glass epoxy board, for example, and a wiring pattern (not shown) made of, for example, copper or the like is formed so as to form a desired circuit, and electrode pads ( (Not shown) is connected. Then, the solder balls of the interposer substrate in the semiconductor device 4 are electrically connected to the electrical pads, so that the semiconductor device 4 is mounted on the circuit board 5. In addition, it is also possible to form the wiring pattern which comprises a circuit with the method of this invention.

図7は本発明の電子機器の一実施形態としての、携帯電話の概略構成を示す斜視図である。図7に示すようにこの携帯電話6は、前記のICチップ又は前記回路基板5を、その筐体内部に備えている。
なお、電子機器としては、前記の携帯電話に限られることなく、種々の電子機器に適用することができる。例えば、ノート型コンピュータ、液晶プロジェクタ、マルチメディア対応のパーソナルコンピュータ(PC)及びエンジニアリング・ワークステーション(EWS)、ページャ、ワードプロセッサ、テレビ、ビューファインダ型又はモニタ直視型のビデオテープレコーダ、電子手帳、電子卓上計算機、カーナビゲーション装置、POS端末、タッチパネルを備えた装置等の電子機器に適用することができる。
FIG. 7 is a perspective view showing a schematic configuration of a mobile phone as an embodiment of the electronic apparatus of the present invention. As shown in FIG. 7, the cellular phone 6 includes the IC chip or the circuit board 5 inside the casing.
Note that the electronic device is not limited to the mobile phone described above, and can be applied to various electronic devices. For example, notebook computers, liquid crystal projectors, multimedia-compatible personal computers (PCs) and engineering workstations (EWS), pagers, word processors, TVs, viewfinder type or monitor direct view type video tape recorders, electronic notebooks, electronic desks The present invention can be applied to electronic devices such as a computer, a car navigation device, a POS terminal, and a device having a touch panel.

以上、添付図面を参照しながら本発明に係る好適な実施の形態について説明したが、本発明は係る例に限定されない。
例えば本実施形態では、本発明の導電パターンの形成方法を電極や配線の形成方法、或いは、電子部品の形成方法に適用した例について説明した。しかし、本発明を半導体装置や回路基板等の、導電パターンを有する種々のデバイスの製造方法に適用可能であることは言うまでもなく、これにより、従来のMEMS技術を用いて形成した3次元構造よりも信頼性の高い構造物を安価に形成することが可能となる。この場合、平面形状のパターンを形成することも可能であるが、3次元形状のパターンを形成する方が本発明の効果をより効果的に発揮することができる。
なお、本方法で得られる導電パターンでは、導電パスはパターンの表面部のみに形成されるため、従来のもの(導電パスがパターン全体で形成されるもの)に比べて抵抗が若干大きくなるが、この導電パターンを例えば高周波伝送等に利用する場合には、電気伝導はパターンの表面部のみで生じる(表皮効果)ため、特に問題にはならない。
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples.
For example, in the present embodiment, an example in which the method for forming a conductive pattern of the present invention is applied to a method for forming an electrode or wiring or a method for forming an electronic component has been described. However, it goes without saying that the present invention can be applied to a method for manufacturing various devices having a conductive pattern, such as a semiconductor device or a circuit board, thereby making it more suitable than a three-dimensional structure formed using conventional MEMS technology. A highly reliable structure can be formed at low cost. In this case, a planar pattern can be formed, but the effect of the present invention can be more effectively exhibited by forming a three-dimensional pattern.
In the conductive pattern obtained by this method, since the conductive path is formed only on the surface portion of the pattern, the resistance is slightly larger than the conventional one (the conductive path is formed by the entire pattern), When this conductive pattern is used, for example, for high-frequency transmission, electrical conduction occurs only on the surface portion of the pattern (skin effect), so there is no particular problem.

また、上記実施形態では、導電パターンを絶縁性の芯材の表面にメッキ処理を施すことにより形成したが、芯材自体が導電性を示すものであれば、このようなメッキ処理は不要となる。例えば芯材を、ピロール等の金属導電性を示す高分子材料によって形成したり、アクリル等の絶縁性の高分子材料に導電性微粒子を練り込んだものによって形成したりすることにより、芯材の形成工程のみで導電パターンを形成することが可能となる。また、こうして得られた導電パターンでは導電パスはパターン全体に形成されるため、パターン表層部にのみ導電パスが形成される上述の構成に比べて良好な電気的特性が得られる。   In the above embodiment, the conductive pattern is formed by plating the surface of the insulating core material. However, if the core material itself exhibits conductivity, such a plating process is not necessary. . For example, the core material is formed of a polymer material exhibiting metal conductivity such as pyrrole or formed by kneading conductive fine particles in an insulating polymer material such as acrylic. The conductive pattern can be formed only by the forming process. Further, in the conductive pattern thus obtained, the conductive path is formed over the entire pattern, so that better electrical characteristics can be obtained than in the above-described configuration in which the conductive path is formed only in the pattern surface layer portion.

本発明の導電パターンの形成方法の一例としての配線の形成方法を示す工程図。FIG. 5 is a process diagram showing a wiring forming method as an example of a conductive pattern forming method of the present invention. 同、導電パターンの形成方法に好適に用いられる光造形装置の概略構成を示す模式図。The schematic diagram which shows schematic structure of the optical modeling apparatus used suitably for the formation method of an electroconductive pattern similarly. 同、導電パターンの芯材の形成工程の一例を示す工程図。Process drawing which shows an example of the formation process of the core material of a conductive pattern equally. 本発明の電子部品の一例を示す部分断面図。The fragmentary sectional view which shows an example of the electronic component of this invention. 本発明の配線構造の一例を示す平面図及び断面図。The top view and sectional drawing which show an example of the wiring structure of this invention. 本発明の回路基板の一例を示す斜視図。The perspective view which shows an example of the circuit board of this invention. 本発明の電子機器の一例を示す斜視図。FIG. 14 is a perspective view illustrating an example of an electronic device of the invention.

符号の説明Explanation of symbols

1・・・配線(導電パターン)、2・・・電子部品、3・・・配線(導電パターン)、5・・・回路基板、6・・・電子機器、10・・・基板、11・・・導電層、12・・・芯材、12a,15a・・・第1の芯部、12b,15b・・・第2の芯部、12c,15c・・・第3の芯部、13,16・・・導電材料、14a,17a・・・第1の導電部、14b,17b・・・第2の導電部、14c,17c・・・第3の導電部、17・・・プローブ(導電パターン)、18・・・インダクタ(導電パターン)、R,R1,R2・・・樹脂

DESCRIPTION OF SYMBOLS 1 ... Wiring (conductive pattern), 2 ... Electronic component, 3 ... Wiring (conductive pattern), 5 ... Circuit board, 6 ... Electronic device, 10 ... Board, 11 ... -Conductive layer, 12 ... core material, 12a, 15a ... first core portion, 12b, 15b ... second core portion, 12c, 15c ... third core portion, 13, 16 ... Conductive material, 14a, 17a ... 1st conductive part, 14b, 17b ... 2nd conductive part, 14c, 17c ... 3rd conductive part, 17 ... Probe (conductive pattern) ), 18 ... inductor (conductive pattern), R, R1, R2 ... resin

Claims (15)

光造形技術により基板上にパターンの芯材を形成する工程と、
メッキ技術により上記芯材の表面に導電材料を形成する工程とを備えたことを特徴とする、導電パターンの形成方法。
Forming the core material of the pattern on the substrate by stereolithography technology;
And a step of forming a conductive material on the surface of the core material by a plating technique.
導電性の樹脂を用いて光造形技術により基板上に所定のパターンを形成することを特徴とする、導電パターンの形成方法。   A method for forming a conductive pattern, wherein a predetermined pattern is formed on a substrate by an optical modeling technique using a conductive resin. 導電層の上に該導電層と電気的に接続された導電パターンを形成する方法であって、
光造形技術により、上記導電層上にパターン本体の形状をなす第1の芯部と、該第1の芯部と上記導電層とを接続するための第2の芯部とを一体に形成する工程と、
メッキ技術により、上記第1の芯部と第2の芯部とを含む芯材の表面に導電材料を形成する工程とを備えたことを特徴とする、導電パターンの形成方法。
A method of forming a conductive pattern electrically connected to the conductive layer on the conductive layer,
A first core part that forms the shape of the pattern main body and a second core part for connecting the first core part and the conductive layer are integrally formed on the conductive layer by an optical modeling technique. Process,
A method for forming a conductive pattern, comprising: a step of forming a conductive material on a surface of a core material including the first core portion and the second core portion by a plating technique.
導電層の上に該導電層と電気的に接続された導電パターンを形成する方法であって、
導電性の樹脂を用いて光造形技術により、上記導電層上にパターン本体となる第1の導電部と、該第1の導電部と上記導電層とを接続するための接続プラグとなる第2の導電部とを一体に形成することを特徴とする、導電パターンの形成方法。
A method of forming a conductive pattern electrically connected to the conductive layer on the conductive layer,
A first conductive part that becomes a pattern body on the conductive layer, and a second plug that becomes a connection plug for connecting the first conductive part and the conductive layer by an optical modeling technique using a conductive resin. A conductive pattern forming method, wherein the conductive portion is integrally formed.
請求項1〜4のいずれかの項に記載の方法により形成された導電パターンを用いて配線を形成することを特徴とする、配線の形成方法。   A method of forming a wiring, comprising forming a wiring by using the conductive pattern formed by the method according to claim 1. 請求項1〜4のいずれかの項に記載の方法により形成された導電パターンを用いて半導体装置を製造することを特徴とする、半導体装置の製造方法。   A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device using the conductive pattern formed by the method according to claim 1. 請求項1〜4のいずれかの項に記載の方法により形成された導電パターンを用いて回路基板を製造することを特徴とする、回路基板の製造方法。   A circuit board is manufactured using the conductive pattern formed by the method of any one of Claims 1-4, The manufacturing method of a circuit board characterized by the above-mentioned. 請求項1〜4のいずれかの項に記載の方法により形成された導電パターンを用いて電子部品を製造することを特徴とする、電子部品の製造方法。   The manufacturing method of an electronic component characterized by manufacturing an electronic component using the conductive pattern formed by the method of any one of Claims 1-4. 3次元的な形状を有する樹脂製の芯材と、この芯材の表面を被覆する導電材料とを備えたことを特徴とする、導電パターン。   A conductive pattern comprising a resin-made core material having a three-dimensional shape and a conductive material covering the surface of the core material. 導電層に電気的に接続された導電パターンであって、
パターン本体の形状をなす第1の芯部と、該第1の芯部と上記導電層とを接続するための第2の芯部とが一体に形成された樹脂製の芯材と、
この芯材の表面を被覆する導電材料とを備えたことを特徴とする、導電パターン。
A conductive pattern electrically connected to the conductive layer,
A resin core material in which a first core portion forming the shape of a pattern body and a second core portion for connecting the first core portion and the conductive layer are integrally formed;
A conductive pattern comprising a conductive material covering the surface of the core material.
請求項9又は10記載の導電パターンを備えたことを特徴とする、配線。   A wiring comprising the conductive pattern according to claim 9. 請求項9又は10記載の導電パターンを備えたことを特徴とする、半導体装置。   A semiconductor device comprising the conductive pattern according to claim 9. 請求項9又は10記載の導電パターンを備えたことを特徴とする、回路基板。   A circuit board comprising the conductive pattern according to claim 9. 請求項9又は10記載の導電パターンを備えたことを特徴とする、電子部品。   An electronic component comprising the conductive pattern according to claim 9. 請求項9又は10記載の導電パターンを備えたことを特徴とする、電子機器。   An electronic apparatus comprising the conductive pattern according to claim 9.
JP2003407388A 2003-12-05 2003-12-05 Conductive pattern forming method, wiring forming method, semiconductor device manufacturing method, circuit board manufacturing method, and electronic component manufacturing method Expired - Fee Related JP4639586B2 (en)

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