JP2005167009A - Manufacturing method of electronic beam exposure mask - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of a mask for electronic beam exposure, with which cost can remarkably be reduced and a merit such as remarkable shortening of an appointed date of delivery can be obtained. <P>SOLUTION: A master mask M where prescribed mask patterns A to H are formed in a plurality of mask pattern forming regions is arranged in the mask stage of an electronic beam proximity exposure device. Mask blanks 40 are disposed in work stages of the electronic beam proximity exposure device. A plurality of mask patterns of the master mask are transferred on resist layers of the mask blanks adjacently to a planar direction. The mask blanks after transfer are installed on the work stages of an electronic beam drawing device. A connection pattern C between a plurality of mask patterns transferred by electronic beam drawing is drawn. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing an electron beam exposure mask, and in particular, a novel mask for a semiconductor integrated circuit by combining a plurality of mask patterns of a circuit that is expected to be used for general use, which is registered as IP (Intellectual Property). The present invention relates to a method for manufacturing an electron beam exposure mask suitable for forming a pattern.

  In recent years, sharing of circuit portions has progressed in semiconductor circuits and the like that are increasing in complexity. In the design field of semiconductor circuits and the like, IP (Intellectual Property) often refers to a circuit unit having a certain scale such as RAM, ROM, and DSP. Smaller general-purpose circuits are cells (microcells, Standard cells) and smaller circuits are called libraries. All of these general-purpose circuit units may be considered as broad IP. The term IP used in the present invention means this broad IP.

  That is, a circuit unit commonly used in a semiconductor circuit or the like is registered as an IP, and in designing a new semiconductor circuit or the like, the design is completed simply by arranging these IPs (referred to as layout design). ing.

  These IPs tend to be shared and used by organizations such as corporations and universities. By adopting such a form, the effort to redesign the circuit part commonly used among each user is greatly reduced, and the advantages such as drastic reduction of design cost and drastic reduction of delivery time Is obtained.

An electron beam exposure mask composed of the mask pattern thus formed is suitable for various electron beam exposures such as a low energy electron beam proximity projection lithography (LEEPL) method (see Patent Document 1). Can be used for
US Pat. No. 5,831,272

  However, when a pattern is drawn in the production of a conventional photomask, even if it is an IP pattern, the mask drawing machine needs to generate and draw the pattern each time, and thus has a large capacity. Data management costs increase, and pattern drawing takes a long time.

  In addition, with the recent miniaturization of design rules for semiconductor circuits and the like, more serious problems have occurred. In other words, various phase shift masks such as halftone and Levenson type have begun to be used, but when one IP is developed and registered in halftone type and another IP is developed and registered in Levenson type, these IPs are the same. It is extremely difficult to manufacture on a photomask substrate. As a result, there are significant restrictions on the use of IP.

  Photomasks having an optical proximity correction (OPC) pattern have also begun to be used for fine patterns, but this pattern varies depending on the wavelength of the light exposure apparatus. That is, there are various types of light sources for the light exposure apparatus such as g-line, I-line, KrF laser, ArF laser, and F2 laser. In addition, it takes a long time (for example, 3 to 7 days) to produce data for OPC.

  Thus, with the progress of miniaturization, in the light exposure using a photomask, the improvement in the design efficiency of the soot that is enhanced by utilizing IP may cause the opposite effect. Also, in the manufacture of photomasks, not only can the benefits of using IP be obtained, but there is also a need to draw a complicated and enormous number of patterns such as OPC patterns and phase shift masks.

  The present invention has been made in view of such circumstances, and does not limit the use of IP at the time of design, and does not unnecessarily increase the types of IP. Is also applied to provide a method of manufacturing a mask for electron beam exposure that can provide advantages such as a significant reduction in cost and a significant reduction in delivery time when a mask pattern is formed.

  In order to achieve the above object, according to the present invention, a master mask in which a predetermined mask pattern is formed in a plurality of mask pattern formation regions is arranged on a mask stage of an electron beam proximity exposure apparatus, and mask blanks are arranged in an electron beam proximity exposure apparatus. And providing a mask blank for electron beam exposure, wherein a plurality of mask patterns of the master mask are transferred to a resist layer of the mask blank substantially adjacent to each other in a plane direction.

  According to the present invention, a desired mask pattern is selected and transferred to a mask blank resist layer. As a result, a desired device design pattern is formed on the mask blank, and the phase shift and OPC are not necessary for these patterns. As a result, it is possible to obtain merits such as drastic reduction in mask manufacturing cost and drastic reduction in delivery time.

  That is, the mask manufactured using the electron beam in the present invention is for transferring a pattern of a semiconductor circuit or the like onto the wafer using the electron beam. With the progress of miniaturization in recent years, the pattern dimension is required to be about 1/2 of the wavelength of light used by the light exposure apparatus, and pattern formation is difficult due to the light diffraction effect. In order to improve this even a little, a phase shift mask or a photomask with an OPC pattern is used. On the other hand, when an electron beam is used as in the present invention, the wavelength of the electron beam is as short as 0.27 angstrom even at 2 KeV, and the diffraction effect can be completely ignored. That is, the present invention provides a mask that does not require a phase shift or an OPC pattern, and clears technical problems that restrict IP utilization.

  Further, according to the present invention, a master mask having a predetermined mask pattern formed in a plurality of mask pattern forming regions is arranged on a mask stage of an electron beam proximity exposure apparatus, and mask blanks are arranged on a work stage of the electron beam proximity exposure apparatus. , A plurality of mask patterns of the master mask are transferred to the resist layer of the mask blanks substantially adjacent to each other in a plane direction, the mask blanks after the transfer are arranged on a work stage of an electron beam drawing apparatus, Provided is a method for manufacturing an electron beam exposure mask, wherein a connection pattern between a plurality of transferred mask patterns is drawn.

  According to the present invention, a desired mask pattern is selected from a plurality of mask patterns that have been converted to IP in the master mask, transferred to the resist layer of the mask blank, and another desired mask adjacent to the transferred pattern. The pattern is transferred, and this process is repeated to transfer all the mask patterns necessary for the desired semiconductor integrated circuit. Then, this mask blank is placed in an electron beam drawing apparatus, and a connection pattern between a plurality of mask patterns transferred by electron beam drawing is drawn. As a result, a desired semiconductor integrated circuit design pattern is formed on the mask blank.

  In other words, in the present invention, mask pattern transfer is performed using an electron beam having an extremely short wavelength, so that it is not necessary to cope with phase shift or OPC, data preparation is unnecessary, or data of only a connection part and a new circuit part. Since it can be limited to creation, the process from the design of the semiconductor integrated circuit to the mask manufacturing can be performed in a very short time. As a result, merits such as a significant reduction in the manufacturing cost of the semiconductor integrated circuit and a significant shortening of the delivery time can be obtained.

  In the present invention, the plurality of mask patterns of the master mask preferably include a plurality of the same mask patterns. As described above, in the aspect having a plurality of the same mask patterns, when one mask pattern is contaminated, another mask pattern can be used immediately instead of this, and the necessary total exposure amount can be increased. Multiple exposures that reduce the influence of a defective mask pattern by exposing with a half exposure amount are possible, and various merits can be obtained.

  In the present invention, the plurality of mask patterns of the master mask may include a mask pattern having a complementary relationship. By using a complementary mask pattern, a so-called donut pattern can be rapidly exposed onto the wafer.

  As described above, according to the present invention, a desired mask pattern is selected and transferred to the resist layer of the mask blank. If necessary, a connection pattern between mask patterns or a new design pattern is drawn by electron beam drawing. As a result, design patterns of desired devices are formed on the mask blanks, and these patterns do not require phase shift or OPC, and data preparation is unnecessary or can be performed in a very short time. . As a result, it is possible to obtain merits such as drastic reduction in design from mask to design and mask manufacturing cost, and drastic reduction in delivery time.

  A preferred embodiment of a method for manufacturing an electron beam exposure mask according to the present invention will be described below with reference to the accompanying drawings. Here, an example will be described in which a step of drawing a connection pattern between a plurality of transferred mask patterns is included. FIG. 1 is a process flow diagram showing a manufacturing method of an electron beam exposure mask and the like, and FIG. 2 is an explanatory diagram showing an arrangement state of a plurality of mask patterns in a master mask M and a mask pattern transfer state in a mask blank 40. It is.

  A method for manufacturing an electron beam exposure mask will be described with reference to FIG. First, a method for manufacturing the master mask M for electron beam exposure shown in FIGS. 1A and 1B will be described. As shown in FIG. 2, the master mask M is a mask in which a plurality of IP mask patterns A to H are arranged in each mask pattern formation region. The mask patterns A to H may include a plurality of identical mask patterns, or may include a mask pattern having a complementary relationship. However, it is preferable that the mask patterns A to H include all patterns necessary as circuit patterns of an integrated circuit such as a semiconductor circuit.

  Usually, the size of an IP mask pattern is within 1 mm square. When an 8-inch wafer master mask is used, about 10,000 1 mm square mask patterns can be arranged.

  The master mask M is manufactured by an electron beam lithography apparatus 2 (which may be either an electron beam mask lithography apparatus or an electron beam wafer direct lithography apparatus) 2. The electron beam mask drawing apparatus is sold by Hitachi, JEOL, New Flare Technology, etc. An electron beam wafer direct writing apparatus is sold by, for example, Advantest.

  Next, among the mask patterns A to H of the master mask M, a plurality of mask patterns necessary for a desired integrated circuit are selected, and the plurality of mask patterns are substantially adjacent to the resist layer of the mask blank 40 in the plane direction. Transfer (see FIG. 1C). In the example shown in FIG. 2, among the mask patterns A to H of the master mask M, four patterns A, D, E, and H are selected and transferred onto the mask blank 40 adjacent to each other.

  Hereinafter, the transfer process shown in FIG. 1C will be described together with the configuration of the electron beam proximity exposure apparatus 10. FIG. 3 is a diagram showing a basic configuration of the electron beam proximity exposure apparatus 10. The electron beam proximity exposure apparatus 10 is a LEEPL (low energy electron beam proximity projection lithography) type exposure apparatus.

  The electron beam proximity exposure apparatus 10 mainly includes an electron beam source 14 that generates an electron beam 15, an electron gun 12 that includes a lens 16 that makes the electron beam 15 a parallel beam, and a shaping aperture 18, main deflectors 22 and 24, and sub-deflection. The scanner 26 includes a scanning unit 20 that scans an electron beam parallel to the optical axis, and a mask 30. In this transfer process, the master mask M is used as the mask 30.

  The mask 30 is arranged so as to be close to a mask blank 40 having a resist layer 42 formed on the surface (so that a gap between the mask 30 and the mask blank 40 is 50 μm, for example). In this state, when the electron beam 15 is irradiated perpendicularly to the mask 30, the electron beam 15 that has passed through the mask pattern of the mask 30 is irradiated to the resist layer 42 on the mask blank 40.

  Further, the scanning means 20 controls the deflection of the electron beam so that the electron beam 15 scans the entire surface of the mask 30 as shown in FIG. Thereby, the mask pattern of the mask 30 is transferred to the resist layer 42 on the mask blank 40 at the same magnification.

  The electron beam proximity exposure apparatus 10 is provided in a vacuum chamber 50 as shown in FIG. In the vacuum chamber 50, the mask stage 80 that supports the mask 30 and the mask 30 supported by the mask stage 80 are moved in two horizontal orthogonal directions (X direction and Y direction) and rotated in a horizontal plane. A mask moving mechanism 83 is provided.

  When the mask pattern is within the deflection region of the electron beam 15, the mask pattern is selected by deflecting the electron beam 15, and the mask pattern is transferred at the same magnification by performing beam scanning only on the selected mask pattern. . When the mask pattern is outside the deflection area of the electron beam 15, the mask moving mechanism 83 moves the mask pattern into the deflection area of the electron beam 15, selects it by deflection, and performs the same size transfer by beam scanning. To do. By repeating these, a plurality of types of mask patterns of the master mask M can be transferred to one mask blank 40.

  Further, in the vacuum chamber 50, an electrostatic chuck 60 for attracting the mask blanks 40 and the mask blanks 40 attracted to the electrostatic chucks 60 in the horizontal orthogonal biaxial directions (X direction and Y direction). A wafer stage 70 is provided for moving and rotating in a horizontal plane. The wafer stage 70 moves the mask blanks 40 by a predetermined amount every time the same-size transfer of the mask pattern is completed. Thereby, a plurality of mask patterns can be transferred to one mask blank 40.

  When the master mask M is distorted at the time of this transfer, the transferred pattern is distorted. Therefore, the sub-deflectors 26 and 28 control the incident angle of the electron beam at the time of transfer, thereby reducing the mask distortion. Make corrections. The control of the incident angle of the electron beam is performed so that the mask distortion is corrected by an instruction of a digital arithmetic circuit (not shown) based on correction data corresponding to the master mask M data (mask distortion) measured in advance. The incident angle of the beam to the mask pattern is controlled (tilt correction).

  As shown in FIG. 6, if the incident angle of the electron beam 15 on the mask 30 is Ψ and the interval between the mask 30 and the mask blank 40 is G, the shift amount δ of the transfer position of the mask pattern by the incident angle Ψ. Is represented by δ = G · tan Ψ. In FIG. 6, the mask pattern is transferred to a position shifted from the initial position by the shift amount δ. Therefore, the transfer position can be changed by changing the incident angle Ψ according to the scanning position of the electron beam.

  The mask distortion is corrected by, for example, enlarging the mask pattern or reducing the mask pattern and transferring it so that the electron beam tilts so that the mask pattern is transferred without mask distortion. This is done by performing correction.

  While controlling as described above, the mask pattern formed on the mask 30 by the electron beam is transferred to the mask blank 40, and this transfer is repeated to transfer all the mask patterns necessary for the desired device.

  Next, as shown in FIG. 1 (d), the mask blanks 40 after transfer are arranged on the work stage of the electron beam drawing apparatus 4, and a connection pattern C between a plurality of mask patterns transferred by electron beam drawing, Draw C ... The electron beam drawing apparatus 4 used here is used for electron beam drawing of a mask and electron beam drawing of a device, and is sold. The details of this drawing are shown in FIG.

  In this way, all the mask patterns necessary for the desired device are transferred, and the connection patterns C, C... Between the plurality of mask patterns are drawn, so that the design pattern of the desired device is formed on the mask blank. The Rukoto. In addition, it is not necessary to cope with phase shift or OPC, and data preparation is unnecessary or can be performed in a very short time. As a result, it is possible to obtain merits such as drastic reduction in mask manufacturing cost and drastic reduction in delivery time.

  Next, a process of forming the mask blank 40 by transfer and electron beam drawing on the electron beam exposure mask will be described. Here, a process of forming a stencil mask 112 shown in FIG. 7 as an electron beam exposure mask will be described. This process proceeds in the order from FIG. 7 (a) to (g).

  In FIG. 7A, the stencil mask 112 includes silicon 114, and a thin film is formed in the order of the silicon oxide layer 116 and the silicon film 118 on the entire lower surface of the silicon 114. Note that when the silicon film 118 is diamond or SiC, the silicon oxide layer 116 may be omitted. The thickness of each of the silicon 114, the silicon oxide layer 116, and the silicon film 118 is not particularly limited. For example, the silicon 114 has a thickness of about 525 μm, and the silicon oxide layer 116 and the silicon film 118 have a thickness of 0.3 to 1. Those in the range of 0.0 μm can be suitably used.

  FIG. 7B shows a state in which a resist 120 is formed on the back surface (upper surface) of the stencil mask 112, and this resist 120 is patterned into a window shape for back etching processing.

  FIG. 7C shows a state in which the silicon 114 and the silicon oxide layer 116 are removed in a window shape by the back etching process. .. Are formed by the removed silicon 114 and silicon oxide layer 116, and the membranes 126, 126... Are exposed from the transmission holes 125, 125. Here, as the back etching treatment, for example, a wet etching solution, that is, a heated alkaline solution such as potassium hydroxide or hydrazine is used. In addition to the wet etching method, a dry etching method may be used.

  In FIG. 7D and subsequent figures, the stencil mask 112 is shown in an upside down state. FIG. 7D shows a state in which a predetermined pattern portion is exposed after the resist 122 is applied and formed on the silicon film 118 on the surface (upper surface) of the stencil mask 112. A master mask M is used for this exposure. By this exposure, a pattern is formed on the resist 122 as shown in FIG.

  FIG. 7F shows a state in which a portion of the membrane 126 (silicon film 118) exposed on the surface side (upper surface side) of the stencil mask 112 is removed by dry etching, and mask patterns 127, 127... Are formed. .

  FIG. 7G shows a state where the resist 122 has been peeled off, and is the final form of the stencil mask 112 according to the present invention.

  Transmission holes 125, 125... Are formed in the mask pattern formation region of the stencil mask 112, and membranes 126, 126,... With the mask pattern 127 formed on the upper surface of the stencil mask 112. A part of the silicon 114 left in the back etching process is left as a beam 124, and supports the membranes 126, 126. The above is one example of the process of forming the stencil mask 112 as the electron beam exposure mask (mask blank 40).

  FIG. 1E shows a state in which a plurality of mask blanks 40, 40. As shown in FIG. 1 (f), the mask blanks 40, 40... Are mounted on the mask stages 80 (see FIG. 5) of a plurality of electron beam proximity exposure apparatuses 10, 10,. As a result, as shown in FIG. 1 (g), a plurality of wafers W, W... Can be exposed with high efficiency, the manufacturing cost of integrated circuit elements such as semiconductor circuits can be greatly reduced, and the delivery time can be greatly reduced. Etc. are obtained.

  The preferred embodiments of the method for manufacturing an electron beam exposure mask according to the present invention have been described below, but the present invention is not limited to the above-described embodiments, and various aspects can be adopted. For example, the arrangement state of the plurality of mask patterns in the master mask M and the transfer state of the mask pattern in the mask blank 40 can take various forms other than the form shown in FIG.

  In the present invention, a connection pattern between a plurality of mask patterns transferred by the electron beam drawing apparatus 4 is drawn, but a method of forming a connection pattern on a part of the plurality of mask patterns in the master mask M is also provided. Can be adopted. According to such a method, although it is inferior in terms of versatility of the mask pattern, the process of drawing a connection pattern between a plurality of mask patterns transferred by electron beam drawing, which is the latter process, can be omitted. Significant shortening can be achieved.

Process flow diagram showing manufacturing method of electron beam exposure mask Explanatory drawing which shows the arrangement state of the several mask pattern in a master mask, and the transfer state of the mask pattern in mask blanks The figure which shows the basic composition of the electron beam proximity exposure apparatus Diagram used to explain scanning of mask by electron beam Overall configuration of electron beam proximity exposure system The figure which shows a mode that the transfer position of an electron beam is shifted by a sub deflector. Sectional drawing which shows the process of forming a stencil mask

Explanation of symbols

  DESCRIPTION OF SYMBOLS 2 ... EB mask writer, 4 ... Electron beam drawing apparatus, 10 ... Electron beam proximity exposure apparatus, 12 ... Electron gun, 15 ... Electron beam, 20 ... Scanning means, 22, 24 ... Main deflector, 26, 28 ... Sub deflection 40 ... Mask blanks, 44 ... Wafer pallet, 70 ... Wafer stage, 80 ... Mask stage, M ... Master mask, W ... Wafer

Claims (4)

A master mask in which a predetermined mask pattern is formed in a plurality of mask pattern formation regions is arranged on a mask stage of an electron beam proximity exposure apparatus,
Place the mask blank on the work stage of the electron beam proximity exposure system,
A method for manufacturing an electron beam exposure mask, comprising: transferring a plurality of mask patterns of the master mask substantially adjacent to each other in a plane direction onto a resist layer of the mask blanks. A master mask in which a predetermined mask pattern is formed in a plurality of mask pattern formation regions is arranged on a mask stage of an electron beam proximity exposure apparatus,
Place the mask blank on the work stage of the electron beam proximity exposure system,
A plurality of mask patterns of the master mask are transferred to the resist layer of the mask blank substantially adjacent to each other in a plane direction,
A method of manufacturing an electron beam exposure mask, wherein the mask blanks after transfer are arranged on a work stage of an electron beam lithography apparatus, and a connection pattern between the plurality of transferred mask patterns is drawn by electron beam lithography. .   3. The method for manufacturing an electron beam exposure mask according to claim 1, wherein the plurality of mask patterns of the master mask include a plurality of the same mask patterns.   4. The method of manufacturing an electron beam exposure mask according to claim 1, wherein the plurality of mask patterns of the master mask include complementary mask patterns. 5.

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