JP2005165257A - Display device and driving method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make good display possible by improving the controllability of display operations by a video signal. <P>SOLUTION: Writing operations are changed between the first and second writing operations based on the gradations to be displayed. The first writing operation includes setting a voltage signal input terminal E at a first potential, opening a switch Sw 2, and closing switches Sw 5a and Sw 5b to pass current as the video signal to a driving control element Tr. The second writing operation includes setting the voltage signal input terminal E at a second potential, opening the switch Sw 2, and closing the switches Sw 5a and Sw 5b to pass current as a reset signal to the driving control element Tr, then opening the switch Sw 5b and thereafter setting the voltage signal input terminal E at the potential corresponding to the video signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a display device and a driving method thereof, and more particularly, to a display device that controls optical characteristics of a display element by a current passed through the display device and a driving method thereof.

  In a display device such as an organic EL (electroluminescence) display device in which the optical characteristics of a display element are controlled by a drive current applied thereto, image quality defects such as luminance unevenness occur when the drive current varies. Therefore, when the active matrix driving method is adopted in such a display device, it is required that the characteristics of the driving transistor for driving the display element are substantially the same between the pixels. However, in this display device, since the transistor is usually formed on an insulator such as a glass substrate, variations in transistor characteristics are likely to occur.

  For this problem, the circuits shown in FIGS. 7 and 8 are proposed in Patent Documents 1 and 2 below. Hereinafter, characteristic correction of the driving transistor using these circuits will be described.

  In the organic EL display device 1 using the circuit of FIG. 7 (threshold cancellation type), when any of the pixels 2 is brought into the display state, first, the output control switch Sw2 is opened using the scanning signal line 7 (OFF) In addition, the correction switch Sw3 is closed (ON) using the scanning signal line 15 to supply charges to the capacitors C1 and C2 until no current flows between the source and drain of the driving transistor Tr. In this state, since the drain and gate of the driving transistor Tr are connected, the potential of the node A becomes the threshold value Vth of the driving transistor Tr. During this time, a scanning signal is supplied from a scanning signal line driver (not shown) to the scanning signal line 6 to close the selection switch Sw1, and a reset signal Vrst is supplied from the video signal line driver (not shown) to the video signal line 9. .

  After completing the above operation, the correction switch Sw3 is opened, and the video signal Vsig is supplied from the video signal line driver to the video signal line 9. As a result, the gate potential of the driving transistor Tr varies from the threshold value Vth by an amount equal to the variable amount from Vrst to Vsig. Then, the selection switch Sw1 is opened and the output control switch Sw2 is closed. As a result, a drive current corresponding to the fluctuation amount is supplied from the power supply wiring 11 to the organic EL element 20 via the drive transistor Tr and the output control switch Sw2.

  Thus, according to the circuit of FIG. 7, the influence of the threshold value Vth on the drive current can be eliminated. Therefore, even if the threshold value of the driving transistor Tr varies between the pixels 2, the influence of such variations on the driving current supplied to the organic EL element 20 can be minimized.

  However, the drive current is affected not only by the threshold value of the drive transistor Tr but also by its mobility and size. Therefore, according to the circuit of FIG. 7, it is difficult to improve the light emission uniformity until the display unevenness is not visually recognized.

  On the other hand, in the organic EL display device 1 using the circuit of FIG. 8 (current copy type), when any one of the pixels 2 is brought into the display state, first, the output control switch Sw2 is opened, the selection switch Sw1 and the correction switch are corrected. / Close the write switch Sw4. Next, in this state, a current Isig corresponding to the video signal is caused to flow between the source and drain of the driving transistor Tr using a constant current circuit (not shown). By this operation, the voltage between both electrodes of the capacitor C2 becomes the gate-source voltage necessary for flowing the current Isig through the channel of the driving transistor Tr.

  Thereafter, the selection switch Sw1 and the correction / writing switch Sw4 are opened, and the output control switch Sw2 is closed. The potential of the node B is set such that a driving current substantially equal to the current Isig flows between the source and drain of the driving transistor Tr by the previous operation.

  As described above, according to the circuit of FIG. 8, a current having a magnitude almost equal to the current Isig supplied as the video signal in the writing period is applied between the source and drain of the driving transistor Tr in the holding period following the writing period. It can flow. Therefore, not only the threshold value Vth of the driving transistor Tr but also the influence of mobility and dimensions on the driving current can be eliminated.

However, in the circuit of FIG. 8, the following problems occur when the wiring capacity of the video signal wiring increases as the pixel size increases or the writing period becomes shorter as the configuration becomes thinner. That is, when the current Isig is small, insufficient writing occurs. In other words, it becomes difficult to write a desired video signal.
US Pat. No. 6,229,506 B1 US Pat. No. 6,373,454B1

  An object of the present invention is to improve the controllability of a display operation using a video signal and to enable good display.

  According to a first aspect of the present invention, there is provided a display device including a plurality of pixels arranged in a matrix, each of the plurality of pixels including a voltage signal input terminal to which a voltage signal is supplied, and a first power source. A drive control element including a first terminal connected to the terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between them; and between the voltage signal input terminal and the control terminal A first capacitor connected to the first capacitor; a current signal input terminal to which a current signal is supplied; a first switch connected between the current signal input terminal and the control terminal; the current signal input terminal; A second switch connected between two terminals, an output control switch having an input terminal connected to the second terminal, and a display connected between a second power supply terminal and the output terminal of the output control switch Comprising the elements, The apparatus changes the writing operation between the first and second writing operations based on the gradation to be displayed, and the first writing operation sets the voltage signal input terminal to the first potential and performs the output control. And opening a switch and closing the first and second switches to pass a current as a video signal between the first and second terminals, and the second writing operation includes setting the voltage signal input terminal to the second Set the potential and open the output control switch and close the first and second switches to pass a current as a reset signal between the first and second terminals, then open the first switch, A display device including setting the voltage signal input terminal to a potential corresponding to the video signal is provided.

  According to a second aspect of the present invention, a plurality of pixels arranged in a matrix are provided, each of the plurality of pixels having a first terminal connected to a first power supply terminal, a control terminal, and a voltage therebetween. A drive control element including a second terminal for outputting a current corresponding to the above, a display element connected between the second terminal and the second power supply terminal, and the control terminal and the voltage signal input terminal. A driving method of a display device including a capacitor connected between the first writing and the second writing operation, wherein the writing operation is changed between a first writing operation and a second writing operation based on a gray level to be displayed. The operation is performed by setting the voltage signal input terminal to the first potential, disconnecting the display element from the second terminal, and connecting the control terminal to the outside of the pixel. A video signal between the terminals The second writing operation sets the voltage signal input terminal to a second potential, disconnects the display element from the second terminal, and connects the control terminal to the outside of the pixel. In this state, a current as a reset signal is passed between the first and second terminals, and then the connection between the control terminal and the outside of the pixel is disconnected, and then the voltage signal input terminal corresponds to the video signal. A method is provided that includes setting to a predetermined potential.

  According to the present invention, the controllability of the display operation by the video signal can be improved, and a good display is possible.

  Hereinafter, some aspects of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the same or similar component, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a plan view schematically showing a display device according to a first aspect of the present invention. The display device 1 is an organic EL display device, for example, and includes a plurality of pixels 2. These pixels 2 are arranged in a matrix on the substrate 3.

  A scanning signal line driver 4 and a video signal line driver 5 are further provided on the substrate 3. The video signal line driver 5 constitutes at least a part of a current signal supply circuit. The video signal line driver 5 constitutes at least a part of the voltage signal supply circuit.

  On the substrate 3, scanning signal lines 6 to 8 connected to the scanning signal line driver 4 are provided so as to extend in the row direction of the pixels 2. The scanning signal lines 6 to 8 are supplied with scanning signals from the scanning signal line driver 4 as voltage signals.

  Further, on the substrate 3, a voltage signal line 9 connected to the video signal line driver 5 and supplied with a voltage signal therefrom, and a current signal connected to the video signal line driver 5 and supplied with a current signal therefrom. A line 10 is provided so as to extend in the column direction of the pixels 2.

  Further, power wiring 11 is provided on the substrate 3.

  The pixel 2 includes a drive control element Tr, a selection switch Sw1, an output control switch Sw2, correction signal supply control switches Sw5a and Sw5b, capacitors C1 and C2, and a display element 20. These switches Sw1, Sw2, Sw5a, and Sw5b are, for example, thin film transistors (TFTs), and the capacitors C1 and C2 are, for example, thin film capacitors. Here, the drive control element Tr is assumed to be composed of TFTs.

  The display element 20 includes an anode and a cathode facing each other, and an active layer whose optical characteristics change according to a current flowing between them. Here, as an example, the display element 20 is an organic EL element including a light emitting layer as an active layer. Here, as an example, the anode is provided as a lower electrode, and is connected to the drive control element Tr via the output control switch Sw2. On the other hand, the cathode is provided, for example, as an upper electrode disposed opposite to the lower electrode through the active layer.

  The drive control element Tr is, for example, a p-channel TFT, and its gate is connected to one electrode of the capacitor C1. When the drive control element Tr is a p-channel TFT, its source is connected to the power supply wiring 11, and its drain is connected to the lower electrode of the organic EL element 20 via the output control switch Sw2.

  The selection switch Sw1 has an input terminal connected to the video signal line 9, and an output terminal connected to the gate of the drive control element Tr via the capacitor C1. The switching operation of the selection switch Sw <b> 1 is controlled by a scanning signal supplied from the scanning signal line 6. The selection switch Sw1 is, for example, a p-channel TFT. In this case, the gate is connected to the scanning signal line 6, the source is connected to the video signal line 9, and the drain is connected to the other electrode of the capacitor C1.

  The output control switch Sw <b> 2 is connected between the drive control element Tr and the organic EL element 20. The switching operation of the output control switch Sw2 is controlled by a scanning signal supplied from the scanning signal line 7. The output control switch Sw2 is, for example, a p-channel TFT. In this case, the gate is connected to the scanning signal line 7, and the source and drain are connected to the drive control element Tr and the organic EL element 20, respectively.

  The correction signal supply control switch Sw5a is connected between the drain of the drive control element Tr and the current signal line 10. Note that the node C on the current signal line 10 serves as a current signal supply terminal. The switching operation of the switch Sw5a is controlled by a scanning signal supplied from the scanning signal line 8. The correction signal supply control switch Sw5a is, for example, a p-channel TFT. In this case, the gate is connected to the scanning signal line 8, and the source and drain are connected to the drain of the drive control element Tr and the current signal line 10, respectively.

  The correction signal supply control switch Sw5b is connected between the drain and gate of the drive control element Tr. The switching operation of the switch Sw5b is controlled by a scanning signal supplied from the scanning signal line 8. The correction signal supply control switch Sw5b is, for example, a p-channel TFT. In this case, the gate is connected to the scanning signal line 8, and the source and drain are connected to the drain and gate of the drive control element Tr, respectively.

  The correction signal supply control switches Sw5a and Sw5b constitute a correction signal supply control unit. The correction signal supply control unit has a structure other than that shown in FIG. 1 as long as the connection / disconnection of the drain of the drive control element Tr, the gate of the drive control element Tr, and the current signal line 10 can be switched. Also good.

  For example, in FIG. 1, the switching operations of the correction signal supply control switches Sw5a and Sw5b are controlled by one scanning signal line 8, but may be controlled by two scanning signal lines.

  In FIG. 1, the correction signal supply control switch Sw5a is connected between the drain of the drive control element Tr and the current signal line 10, but the correction signal supply control switch Sw5a is connected to the drain of the drive control element Tr. It may be connected between the drain of the drive control element Tr and the current signal line 10 between the gate of the drive control element Tr.

  Further, in FIG. 1, the correction signal supply control switch Sw5b is connected between the drain and gate of the drive control element Tr. However, the correction signal supply control switch Sw5b is connected to the current signal line 10 and the drive control element Tr. You may connect between gates.

  The capacitor C1 is connected between the selection switch Sw1 and the gate of the drive control element Tr. The capacitor C2 is connected between the source of the drive control element Tr and the gate of the drive control element Tr. Note that the node E connected to the source of the selection switch Sw1 serves as a voltage signal input terminal.

  The capacitances of the capacitors C1 and C2 do not have to be equal to each other, but are assumed to be equal to each other for simplicity. In addition, the capacitor C2 is, for example, a constant potential terminal insulated from the gate of the drive control element Tr and the source of the drive control element Tr instead of being connected between the source of the drive control element Tr and the gate of the drive control element Tr. You may connect between. That is, if one terminal of the capacitor C2 is connected to the gate of the drive control element Tr and can hold the gate-source voltage of the drive control element Tr corresponding to the video signal, the gate of the drive control element Tr is provided. -There is no need to connect between sources.

  The display device 1 further includes a voltage / current source 25 connected to the video signal line driver 5. The voltage / current source 25 has a built-in voltage source capable of changing the output voltage and a current source capable of changing the output current.

FIG. 2 is an equivalent circuit diagram of a video signal line driver and a voltage / current source that can be used in the display device of FIG.
In the circuit of FIG. 2, the voltage / current source 25 includes a current source CS, a voltage source VS, a switch SwC1, and a switch SwV1. The switch SwC1 is connected between the current source CS and the output terminal of the voltage / current source 25. The switch SwV1 is connected between the voltage source VS and the output terminal of the voltage / current source 25.

  The voltage source VS and the current source CS can be formed in one IC (integrated circuit) 16. The IC 16 can further include a switch SwC1 and a switch SwV1. The voltage / current source 25 can be composed of, for example, the plurality of ICs 16.

  The video signal line driver 5 includes a constant potential line 14, a switch SwV0, a switch SwV2, and a switch SwC2. The constant potential line 14 is set to a constant potential, for example, 0V. The switch SwV0 is connected between the constant potential line 14 and the voltage signal line 9. The switch SwV2 is connected between the output terminal of the voltage / current source 25 and the voltage signal line 9. The switch SwC2 is connected between the output terminal of the voltage / current source 25 and the current signal line 10.

  FIG. 3 is a timing chart schematically showing an example of a method for driving the display device shown in FIG. In this driving method, the first writing period P3C and the second writing period P3V constitute one horizontal period, and the first writing period P3C, the second writing period P3V, and the holding period P4 constitute one vertical period.

  In the method of FIG. 3, the output current Iout of the current source CS and the output voltage Vout of the voltage source VS are different between displaying a brighter gradation and displaying a darker gradation. In FIG. 3, as an example, it is assumed that brighter gradations are displayed by the pixels 2 in the m-th and m + 2 rows, and darker gradations are displayed by the pixels 2 in the m + 1-th row.

  In the case of displaying a gradation that is brighter, for example, corresponding to a driving current larger than 100 nA, the display device 1 is driven as follows, for example.

  For example, in the period for selecting the pixel 2 in the m-th row, that is, the m-th row selection period, first, the switch Sw2 is opened. The first write operation and the second write operation are sequentially performed within a period during which the switch Sw2 is opened.

  In the first writing period P3C in which the first writing operation is performed, first, the switches SwV0, SwC1, and SwC2 are closed, and the switches SwV1 and SwV2 are opened. That is, the voltage source VS and the video signal line driver 5 are disconnected, the constant potential line 14 and the voltage signal line 9 are connected, and the current source CS and the current signal line 10 are connected. In this state, the switches Sw1, Sw5a, and Sw5b are closed, and the output current Iout of the current source CS is set to a current signal Isig corresponding to the video signal, for example, 500 nA. Thereby, the gate-source voltage of the drive control element Tr is set to a value when the current Isig flows between the source and the drain. The first writing period P3C is ended by opening the switches Sw5a and Sw5b.

  As described above, in the first writing period P3C, the connection between the voltage source VS and the video signal line driver 5 is disconnected. Therefore, the potential Vout of the output terminal of the voltage source VS may be any value, but is set to a potential output in the second writing period in order to suppress undesired potential fluctuation later. It is desirable. For example, the potential Vout of the output terminal of the voltage source VS is set to 0V.

  In the second writing period P3V following the first writing period P3C, the gate-source voltage of the drive control element Tr set in the first writing period P3C is held. That is, the switch Sw5b is kept open. Here, as an example, in the second writing period P3V, the switches SwV0, SwC1, and SwC2 are further opened, and the switches Sw1, SwV1, and SwV2 are closed. Here, as an example, the potential Vout of the output terminal of the voltage source VS is set to a predetermined potential, for example, 0V. The second writing period P3V is ended by opening the switch Sw1. Here, the predetermined potential refers to a potential equivalent to the potential set by the constant potential line 14 during the first writing period P3C.

  In the holding period P4 following the second writing period P3V, the switch Sw2 is closed. As a result, a current having a magnitude substantially equal to the current Isig flows through the display element 20. Note that the switches SwV0, SwC1, and SwC2 are closed and the switches SwV1 and SwV2 are opened to perform writing to the next pixel row.

  As described above, in the write operation for displaying a brighter gradation, the current signal Isig is supplied as a video signal between the source and the drain of the drive control element Tr. Thereby, the potential of the node D is set to a value corresponding to the video signal. Since the current Isig is sufficiently large, the potential of the node D faithfully reflects the characteristics of the drive control element Tr. That is, according to this aspect, when displaying a brighter gradation, it is possible to completely eliminate the influence of not only the threshold value Vth of the drive control element Tr but also mobility and dimensions on the drive current.

  In the method of FIG. 3, in the case of displaying a gradation corresponding to a darker drive current of, for example, 100 nA or less, the display device 1 is driven by, for example, the following method.

  For example, in the period for selecting the pixel 2 in the (m + 1) th row, that is, in the (m + 1) th row selection period, first, the switch Sw2 is opened as described for the mth row selection period. The first write operation and the second write operation are sequentially performed within a period during which the switch Sw2 is opened.

  In the first write period P3C in which the first write operation is performed, the switches SwV0, SwC1, and SwC2 are first closed and the switches SwV1 and SwV2 are opened, as described for the m-th row selection period. That is, the voltage source VS and the video signal line driver 5 are disconnected, the constant potential line 14 and the voltage signal line 9 are connected, and the current source CS and the current signal line 10 are connected. In this state, the switches Sw1, Sw5a, and Sw5b are closed.

  However, here, in this state, the output current Iout of the current source CS is not a current Isig corresponding to the video signal but a predetermined reset current Irst, for example, 100 nA. Thus, the gate-source voltage of the drive control element Tr is set to a value Vcrct when the current Irst flows between the source and drain. The first writing period P3C is ended by opening the switches Sw5a and Sw5b.

  In the second writing period P3V, the gate-source voltage of the drive control element Tr set in the first writing period P3C is held as described for the m-th row selection period. That is, the switch Sw5b is kept open. In the second writing period P3V, the switches SwV0, SwC1, and SwC2 are further opened, and the switches SwV1 and SwV2 are closed.

  However, here, in this state, the voltage signal Vout output from the voltage source VS is set to a voltage signal Vsig ', for example, 4 V, substantially corresponding to the video signal. The voltage signal Vsig 'is set within a range of 0V to 6V, for example. As a result, the node E which is a voltage signal input terminal is set to the potential Vsig '. The second writing period P3V is ended by opening the switch Sw1.

  As described above, at the end of the first writing period P3C, the potential of the node D is set to the value Vcrct when the current Irst flows between the source and drain of the drive control element Tr. For this reason, when the potential of the node E is changed from 0 V to Vsig ′, for example, in the second writing period P3V, the potential of the node D changes from Vcrct to Vcrct + Vsig ″. This value is determined by the gate potential and the capacitance ratio of the capacitors C1 and C2. Accordingly, when it is designed that a certain gray scale is displayed when the potential of the node D is Vsig, the voltage signal Vsig ′ for displaying the gray scale is expressed by the equation: Vsig = Vsig ″ + Vcrct (Av The Vcrct (Av) is a value expected for the potential Vcrct, for example, an average value for all pixels of Vcrct.

  The potential Vcrct is a value that is influenced not only by the threshold value of the drive control element Tr but also by its mobility and size. If the current Irst is sufficiently large, the potential Vcrct faithfully reflects the characteristics of the drive control element Tr. Therefore, the characteristics of the drive control element Tr are corrected when the second writing period P3V ends.

  In the holding period P4, the switch Sw2 is closed as described for the m-th row selection period. As a result, a current having a magnitude substantially corresponding to the potential Vcrct + Vsig ′ flows through the display element 20. Note that the switches SwV0, SwC1, and SwC2 are closed and the switches SwV1 and SwV2 are opened to perform writing to the next pixel row.

  As described above, in the writing operation for displaying a darker gradation, first, a sufficiently large reset current Irst is caused to flow between the source and the drain of the drive control element Tr, whereby correction corresponding to the reset current Irst is applied to the node D. A signal Vcrct is supplied. This corrects variations in the characteristics of the drive control element Tr, that is, the threshold value Vth, mobility, dimensions, and the like. Next, the voltage signal Vsig ′ substantially corresponding to the video signal is supplied to the node E, and the potential of the node D is set to Vcrct + Vsig ′.

  When the drive current is equal to the reset current Irst, the correction signal Vcrct completely eliminates the influence of the characteristics of the drive control element Tr, that is, the threshold value Vth, mobility, and dimensions on the drive current. On the other hand, when the drive current is different from the reset current Irst, the correction signal Vcrct does not completely eliminate the influence of the characteristics of the drive control element Tr on the drive current. That is, in the latter case, the correction signal Vcrct includes an error corresponding to the difference between the potential of the node E in the second writing period P3V and the potential of the node E in the first writing period P3C. However, if this potential difference is sufficiently small, the error of the correction signal Vcrct is also small. Therefore, according to this aspect, even when a darker gradation is displayed, the influence of the characteristics of the drive control element Tr, that is, the threshold value Vth, mobility, size, and the like, on the drive current can be almost completely eliminated. it can.

  Further, the writing operation for displaying a brighter gradation and the writing operation for displaying a darker gradation are different only in the outputs of the current source CS and the voltage source VS. That is, in the above method, it is not necessary to change the switching operation of each switch according to the gradation to be displayed. Therefore, a long time is not required for the writing operation to each pixel row.

  Furthermore, in the circuit of FIG. 2, the output from the voltage source VS and the output from the current source CS are selected inside the voltage / current source 25. Therefore, the number of the output terminals of the voltage / current source 25 or the input terminals of the video signal line driver may be one for each pixel column. Even when both a voltage signal and a current signal are used for signal writing, an increase in the outer shape of the module can be suppressed and the reliability of the mechanical strength can be maintained without increasing the number of connection points with an external circuit.

Next, the second aspect of the present invention will be described.
FIG. 4 is a plan view schematically showing a display device according to the second aspect of the present invention. The display device 1 illustrated in FIG. 4 is, for example, an organic EL display device. The display device 1 has the same structure as the display device 1 of FIG. 1 except that the following configuration is adopted.

  That is, in the display device 1, the current signal line 10 is omitted. In the display device 1, instead, the voltage signal line 9 is used as a voltage / current signal line to which both a voltage signal and a current signal are supplied. In the display device 1, a constant potential line 26 is provided.

  In each pixel 2, the drain of the switch Sw1 is connected to the voltage / current signal line 9, and a correction signal supply control switch Sw5e connected between the source of the switch Sw1 and the constant potential line 26 is provided. Here, as an example, a p-channel transistor is used as the switch Sw5e. Here, as an example, the source of the switch Sw5e is connected to the constant potential line 26, but the source of the switch Sw5e may be connected to the power supply wiring 11. In this case, the constant potential line 26 can be omitted.

  A scanning signal line 17 connected to the scanning signal line driver 4 is provided on the substrate 3. The gate of the switch Sw5e is connected to the scanning signal line 17.

  Further, in the display device 1, the video signal line driver 5 shown in FIG. 2 is omitted. Instead, the output terminal of the voltage / current source 25 is connected to the voltage / current signal line 9, and the voltage / current source 25 is used as a video signal line driver.

  In this embodiment, when displaying a gray scale corresponding to a brighter drive current, for example, greater than 100 nA, the display device 1 is driven by, for example, the following method.

  In a period for selecting the pixel 2 to display a brighter gradation, for example, the m-th line selection period, first, the switch Sw2 is opened as described with reference to FIG. The first write operation and the second write operation are sequentially performed within a period during which the switch Sw2 is opened.

  In the first writing period P3C in which the first writing operation is performed, as described with reference to FIG. 3, first, the switch SwC1 is closed and the switch SwV1 is opened. That is, the connection between the voltage source VS and the voltage / current signal line 9 is disconnected, and the current source CS and the voltage / current signal line 9 are connected. In this state, the switches Sw5a, Sw5b, and Sw5e are closed. Note that the switch Sw1 is left open.

  In this state, the output current Iout of the current source CS is set to the current signal Isig corresponding to the video signal. Thereby, the gate-source voltage of the drive control element Tr is set to a value when the current Isig flows between the source and the drain. The first writing period P3C is ended by opening the switches Sw5a and Sw5b.

  In the second writing period P3V following the first writing period P3C, the switch Sw5e is opened. The switch Sw5e may be opened at this stage, or may be opened simultaneously with the opening of the switch Sw5b.

  In the second writing period P3V, next, the switch SwC1 is opened, and the switches Sw1 and SwV1 are closed. Here, the potential Vout of the output terminal of the voltage source VS is substantially equal to the potential V0 of the constant potential line 26. Thereafter, the switch Sw1 is opened. Thereby, the second writing period P3V ends.

  In the holding period P4 following the second writing period P3V, the switch Sw2 is closed. As a result, a current having a magnitude substantially equal to the current Isig flows through the display element 20. Note that the switch SwC1 is closed and the switch SwV1 is opened in order to perform writing to the next pixel row.

  In this aspect, in a period in which a pixel to display a darker gradation, for example, the pixel 2 in the (m + 1) th row is selected, first, the switch Sw2 is opened as described with reference to FIG. The first write operation and the second write operation are sequentially performed within a period during which the switch Sw2 is opened.

  In the first write period P3C in which the first write operation is performed, the switch SwC1 is closed and the switch SwV1 is opened as described for the m-th row selection period. That is, the connection between the voltage source VS and the voltage / current signal line 9 is disconnected, and the current source CS and the voltage / current signal line 9 are connected. In this state, the switches Sw5a, Sw5b, and Sw5e are closed. Further, the switch Sw1 is left open.

  However, here, in this state, the output current Iout of the current source CS is not a current Isig corresponding to the video signal, but a predetermined reset current Irst, for example, a current of 100 nA. Thus, the gate-source voltage of the drive control element Tr is set to a value Vcrct when the current Irst flows between the source and drain. The first writing period P3C is ended by opening the switches Sw5a and Sw5b.

  In the second writing period P3V, the switch Sw5e is opened as described for the m-th row selection period. The switch Sw5e may be opened at this stage, or may be opened simultaneously with the opening of the switch Sw5b.

  In the second writing period P3V, next, the switch SwC1 is opened and the switches Sw1 and SwV1 are closed, as described for the m-th row selection period.

  However, here, in this state, the voltage signal Vout output from the voltage source VS is set to the voltage signal Vsig ′ substantially corresponding to the video signal. As a result, the node E is set to the potential Vsig '. The second writing period P3V is ended by opening the switch Sw1.

  As described in the first mode, when the first writing period P3C ends, the potential of the node D is set to the value Vcrct when the current Irst flows between the source and drain of the drive control element Tr. Yes. Therefore, in the second write period P3V, when the potential of the node E is changed from V0 to Vsig ′, the potential of the node D is changed from Vcrct to Vcrct + Vsig ″ −V0. Therefore, the potential of the node D is Vsig. In this case, when it is designed that a certain gradation is displayed, the voltage signal Vsig ′ for displaying the gradation substantially satisfies the relationship represented by the equation: Vsig = Vsig ″ + Vcrct (Av) −V0. It may be determined as follows.

  In the holding period P4, the switch Sw2 is closed as described for the m-th row selection period. A current having a magnitude substantially corresponding to the potential Vcrct + Vsig ″ −V0 flows through the display element 20. Note that the switch SwC1 is closed and the switch SwV1 is opened in order to perform writing to the next pixel row.

  As described above, the driving method according to this aspect is substantially the same as the first aspect except that the power supply wiring 26 is used instead of the constant potential line 14. Therefore, also in this aspect, the same effect as described in the first aspect can be obtained.

  Further, as described above, in this aspect, the constant potential line 26 is used instead of the constant potential line 14 used in the first aspect. Accordingly, it is necessary to provide the switch Sw5e for each pixel 2, but the current signal line 10 and the video signal line driver 5 shown in FIG. 2 can be omitted.

Next, the third aspect of the present invention will be described.
FIG. 5 is a plan view schematically showing a display device according to the third aspect of the present invention. The display device 1 illustrated in FIG. 5 is, for example, an organic EL display device. This display device 1 has the same structure as the display device 1 of FIG. 4 except that the scanning signal line 17 is omitted and the gate of the switch Sw5e is connected to the scanning signal line 8.

  In the display device 1 of FIG. 5, the switching operation of the switch Sw5e cannot be controlled independently from the switching operation of the switches Sw5a and Sw5b, but can be driven by the same method as described in the second mode. . Therefore, also in this aspect, the same effect as described in the second aspect can be obtained.

  In addition, in this embodiment, the scanning signal line 17 is omitted. That is, according to this aspect, the number of wirings can be reduced as compared with the second aspect.

Next, the fourth aspect of the present invention will be described.
FIG. 6 is a plan view schematically showing a display device according to the fourth aspect of the present invention. A display device 1 illustrated in FIG. 6 is, for example, an organic EL display device. The display device 1 has the same structure as the display device 1 of FIG. 5 except that the following configuration is adopted.

  That is, in the display device 1 of FIG. 6, the correction signal supply control switches Sw5f and Sw5g and the scanning signal line 18 are provided. The correction signal supply control switch Sw5f is connected between one terminal (here, drain) of the correction signal supply control switch Sw5b and the gate of the drive control element Tr. Switching of the correction signal supply control switch Sw5f is controlled by a scanning signal supplied from the scanning signal line 18. The correction signal supply control switch Sw5g is connected between the output terminal of the correction signal supply control switch Sw5e and the electrode on the switch Sw5e side of the capacitor C1. Switching of the correction signal supply control switch Sw5g is controlled by a scanning signal supplied from the scanning signal line 17.

  In the display device 1, the substrate 3, the scanning signal lines 6 to 8 and 18, the voltage / current signal line 9, the power supply line 11, the constant potential line 26, and the switches Sw1, Sw2, Sw5a, Sw5b, Sw5e. , Sw5f and Sw5g, the drive control element Tr, and the capacitors C1 and C2 constitute an active matrix substrate. The active matrix substrate can further include a scanning signal line driver 4 and the like. The active matrix substrate can further include one electrode of the display element.

  The display device 1 of FIG. 6 can be driven by the same method as described in the third aspect. Therefore, also in this aspect, the same effect as described in the third aspect can be obtained.

  By the way, the switches Sw5a and Sw5b may have the same structure and may be formed at the same time. In this case, in principle, the thresholds of the switches Sw5a and Sw5b are the same. However, in practice, the threshold values of the switches Sw5a and Sw5b may vary.

  If the thresholds of the switches Sw5a and Sw5b are different, the switching is not performed at the same time. For example, when the switch Sw5a is opened before the switch Sw5b is opened, the potential of the node D varies between the time when the switch Sw5b is opened and the time when the switch Sw5a is opened. That is, it may be difficult to sufficiently correct the characteristics of the drive control element Tr.

  In this aspect, the switching of the switch Sw5f can be controlled independently of the switching of the switch Sw5b. Therefore, in the first writing period P3C, the switch Sw5f can be opened prior to opening the switch Sw5b. Therefore, undesired fluctuations in the potential of the node D can be prevented. Therefore, the characteristics of the drive control element Tr can be reliably corrected. This effect can also be obtained when the switches Sw5b and Sw5g are not provided.

  In this embodiment, the switches Sw5f and Sw5b are connected in series between the gate and drain of the drive control element Tr. The switches Sw5g and Sw5e are connected in series between the capacitor C1 and the constant potential line 26. Therefore, it is possible to suppress the charge accumulated in the capacitor C1 from leaking during the holding period P4. That is, it is possible to suppress the gate potential of the drive control element Tr from changing in the holding period P4.

  Further benefits and variations are readily apparent to those skilled in the art. Therefore, the invention in its broader aspects should not be limited to the specific descriptions and representative embodiments described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the generic concept of the invention as defined by the appended claims and their equivalents.

1 is a plan view schematically showing a display device according to a first aspect of the present invention. FIG. 2 is an equivalent circuit diagram of a video signal line driver and a voltage / current source usable in the display device of FIG. 1. 2 is a timing chart schematically showing an example of a method for driving the display device shown in FIG. 1. The top view which shows roughly the display apparatus which concerns on the 2nd aspect of this invention. The top view which shows roughly the display apparatus which concerns on the 3rd aspect of this invention. The top view which shows roughly the display apparatus which concerns on the 4th aspect of this invention. 1 is an equivalent circuit diagram of an organic EL display device using a threshold cancellation type circuit. FIG. 3 is an equivalent circuit diagram of an organic EL display device using a current copy type circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 2 ... Pixel, 3 ... Substrate, 4 ... Scanning signal line driver, 5 ... Video signal line driver, 6 ... Scanning signal line, 7 ... Scanning signal line, 8 ... Scanning signal line, 9 ... Voltage signal line Or voltage current signal line, 10 ... current signal line, 11 ... power supply wiring, 14 ... constant potential line, 15 ... scanning signal line, 16 ... IC, 17 ... scanning signal line, 20 ... display element, 25 ... voltage / current source, 26 ... constant potential line, A ... node, B ... node, C ... node or current signal input terminal, C1 ... capacitor, C2 ... capacitor, CS ... current source, D ... node, E ... node or voltage signal input terminal, Sw1 Switch for selection, Sw2 ... Switch for output control, Sw3 ... Switch for correction, Sw4 ... Switch for correction / writing, Sw5a ... Switch for correction signal supply control, Sw5b ... Switch for correction signal supply control, Sw5e ... Correction signal Supply control switch, Sw5f ... Correction signal supply control switch, Sw5g ... Correction signal supply control switch, SwC1 ... Switch, SwC2 ... Switch, SwV0 ... Switch, SwV1 ... Switch, SwV2 ... Switch, Tr ... Drive control element, VS ... voltage source.

Claims (8)

A display device comprising a plurality of pixels arranged in a matrix, wherein each of the plurality of pixels is
A voltage signal input terminal to which a voltage signal is supplied; and
A drive control element including a first terminal connected to the first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage therebetween;
A first capacitor connected between the voltage signal input terminal and the control terminal;
A current signal input terminal to which a current signal is supplied; and
A first switch connected between the current signal input terminal and the control terminal;
A second switch connected between the current signal input terminal and the second terminal;
An output control switch having an input terminal connected to the second terminal;
A display element connected between a second power supply terminal and an output terminal of the output control switch;
The display device changes the writing operation between the first and second writing operations based on the gradation to be displayed,
In the first writing operation, the voltage signal input terminal is set to a first potential, the output control switch is opened, the first and second switches are closed, and a video signal is generated between the first and second terminals. Including flowing a current of
In the second write operation, the voltage signal input terminal is set to a second potential, the output control switch is opened, the first and second switches are closed, and a reset signal is provided between the first and second terminals. And then opening the first switch and then setting the voltage signal input terminal to a potential corresponding to the video signal. A plurality of scanning signal lines arranged corresponding to the row of pixels;
A plurality of voltage signal lines arranged corresponding to the columns of pixels and supplying the voltage signal to the voltage signal input terminals, respectively.
A plurality of current signal lines arranged corresponding to the columns of pixels and supplying the current signals to the current signal input terminals, respectively.
Each of the plurality of pixels further includes a selection switch that is connected between the voltage signal line and the voltage signal input terminal and whose switching operation is controlled by a scanning signal supplied from the scanning signal line. Item 4. The display device according to Item 1. A plurality of scanning signal lines arranged corresponding to the row of pixels;
A plurality of voltage / current signal lines arranged corresponding to the columns of pixels and supplying the voltage signals to the voltage signal input terminals and supplying the current signals to the current signal input terminals, respectively.
Each of the plurality of pixels further includes a selection switch connected between the voltage / current signal line and the voltage signal input terminal and whose switching operation is controlled by a scanning signal supplied from the scanning signal line. The display device according to claim 1.   4. The display device according to claim 3, wherein each of the plurality of pixels further includes a third switch connected between the voltage signal input terminal and a constant voltage source.   The display device according to claim 1, wherein the first switch is connected to the current signal input terminal via the second switch.   2. The display device according to claim 1, wherein each of the plurality of pixels further includes a second capacitor having one electrode connected to the control terminal and the other electrode connected to a constant voltage source.   The display device according to claim 1, wherein the display element is an organic EL element. A plurality of pixels arranged in a matrix, and each of the plurality of pixels outputs a first terminal connected to the first power supply terminal, a control terminal, and a current corresponding to a voltage between them; A drive control element including a terminal, a display element connected between the second terminal and the second power supply terminal, and a capacitor connected between the control terminal and the voltage signal input terminal. A display device driving method comprising:
Changing the write operation between the first and second write operations based on the grayscale to be displayed;
In the first writing operation, the voltage signal input terminal is set to a first potential, the connection between the display element and the second terminal is disconnected, and the control terminal is connected to the outside of the pixel. Flowing a current as a video signal between the first and second terminals,
In the second writing operation, the voltage signal input terminal is set to a second potential, the connection between the display element and the second terminal is disconnected, and the control terminal is connected to the outside of the pixel. Passing a current as a reset signal between the first and second terminals, then disconnecting the control terminal from the outside of the pixel, and then setting the voltage signal input terminal to a potential corresponding to the video signal; Including methods.

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