JP2005157487A - Automatic arranging and wiring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute the proper arrangement and wiring of power lines even for specific cells such as a micro-cell or soft macros, and to prevent standard cells strongly connected to each other from being arranged in circuit blocks different from each other. <P>SOLUTION: This automatic arranging and wiring method comprises a step S1 for arranging specific cells such as macro cells in a specific region in the arrangement region of a semiconductor integrated circuit, a step S2 for arranging and wiring the first power line for supplying a power to the specific cells, a step S3 for dividing any region other than the specific region in the arrangement region into n pieces of divided regions so that the current consumption of the specific cells and the first power line can be well-balanced, a step S4 for dividing any circuit other than the circuit by the specific cells in a logic circuit constituted of the semiconductor integrated circuit into the n pieces of circuit blocks according to the logical connection and steps S5 to S10 for arranging the n pieces of circuit blocks in the n pieces of divided regions according to the logical connection of the logic circuit and current supply quantity to be supplied to the respective divided regions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention reads out at least one macro cell, a soft macro-developed cell group or a special cell such as a cell group having a problem of skew, and a plurality of standard cells from the storage device by a computer including the storage device, The present invention relates to an automatic placement and routing method for creating a layout of a semiconductor integrated circuit by placing and routing special cells, the standard cells, and power supply lines.

  In semiconductor integrated circuits, the metal wiring composing the wiring layer is becoming increasingly thinner and the wiring pitch is reduced as the semiconductor process becomes finer and the wiring layer becomes multi-layered. As the number of elements increases, it is an important issue to consider these parasitic elements when designing the layout.

  In particular, in the layout design of individual power supply lines that supply power supply voltage to individual circuit blocks of a semiconductor integrated circuit, it is considered that voltage fluctuations occur in the power supply lines due to current consumption of the circuit blocks and parasitic elements of the power supply lines. There is a need to. In a semiconductor integrated circuit having a high operating frequency, measures against a voltage drop caused by wiring resistance and a delay caused by the voltage drop are important issues.

  Therefore, conventionally, in order to reduce the voltage drop of the power line, for each standard cell, the actual current consumption is calculated based on the specific current consumption data, load impedance data and circuit activation rate data, Current consumption for each circuit block obtained by dividing the entire logic circuit by a certain unit (total current consumption of a plurality of standard cells constituting the circuit block) and each circuit obtained by dividing the current consumption of the entire logic circuit by the number of circuit blocks There has been proposed a method of dividing each circuit block so that the difference from the average current consumption of the block is small (see, for example, Patent Document 1). Also, here, a standard cell having a relatively large current consumption in the circuit block is arranged near the power supply line, and a standard cell belonging to one circuit block is replaced with a standard cell belonging to another circuit block. It has a process.

By adopting these methods, the entire circuit is divided (grouped) to equalize the current consumption of each circuit block, and standard cells are arranged in each circuit block. It is possible to equalize and suppress variations in circuit delay. As a result, design margins such as circuit operation speed and power supply line width can be reduced to the minimum necessary, so that high speed and high integration of the semiconductor integrated circuit can be achieved.
JP-A-11-238802

  However, since the above method processes the placement and routing in consideration of the power line and current consumption, the standard cell that should be classified in the same circuit block can be replaced with a cell in another circuit block. Sex occurs. Further, no consideration is given to macro cells such as PLLs and memories and soft macros, which need to be supplied with power and whose division area is limited.

  An object of the present invention is to perform proper power line arrangement and wiring for special cells such as macro cells and soft macros, and to prevent standard cells that are strongly connected to each other from being arranged in different circuit blocks. It is to provide an automatic placement and routing method.

According to a first aspect of the present invention, there is provided an automatic placement and routing method comprising: a computer equipped with a storage device; and a special cell such as at least one macro cell, a soft macro expanded cell group or a cell group in which skew is a problem, In an automatic placement and routing method for reading a plurality of standard cells and arranging and wiring the special cells and the standard cells and power supply lines to create a layout of the semiconductor integrated circuit, the special cells are placed in a specific region in the placement region of the semiconductor integrated circuit. A second step of arranging and wiring a first power line for supplying power to the special cell in the arrangement region, a current consumption of the special cell, and the first power line. In order to achieve a balance, areas other than the specific area in the arrangement area are divided to form n divided areas, and power lines are arranged. A third step of wiring, and a fourth step of forming n circuit blocks by dividing a circuit excluding the circuit by the special cell in the logic circuit composed of the semiconductor integrated circuit according to a logical connection. A fifth step of arranging the n circuit blocks in the n divided regions according to a logical connection of the logic circuits and a current supply amount supplied to the n divided regions. And an automatic placement and routing method.
The invention according to claim 2 is the automatic placement and routing method according to claim 1, wherein the formation of the n divided regions in the third step and the formation of the n circuit blocks in the fourth step are performed. , According to the current consumption of the standard cells and the n circuit blocks constituting the n circuit blocks, and the wiring length and wiring width of the power supply lines arranged and wired in the n divided regions. The automatic placement and routing method is as follows.
The invention according to claim 3 is the automatic placement and routing method according to claim 1 or 2, wherein the fifth step uses the n divided regions as gene loci and the n circuit blocks as genes. The tightness of the relationship between the n circuit blocks and between the n circuit blocks and the special cells, the amount of power supplied to the n circuit blocks, and the current consumption in the n circuit blocks The automatic placement and routing method is characterized in that the optimal allocation of the n circuit blocks to the n divided regions is performed by a genetic algorithm using the relationship with the quantity as a constraint.
According to a fourth aspect of the present invention, in the automatic placement and routing method according to the third aspect, the genetic algorithm creates a plurality of combinations of allocation of the n circuit blocks for the n divided regions, and each combination An automatic placement and routing method characterized by evaluating each circuit block according to the constraint condition, and selecting an optimal combination that substantially satisfies the constraint condition by repeating selection, multiplication, and evolution according to the evaluation result; did.

  According to the present invention, a special cell such as a macro cell, a soft macro expanded cell group, or a cell group in which skew is a problem is first arranged in a specific area of the arrangement area, and a power line for the special cell is necessary and sufficient. The other circuit blocks and the power lines that supply power to them are placed and routed so that they are balanced with these special cells, and the special cells and their power lines are affected by others. And can be arranged as required. In addition, since the circuit blocks to be divided into n pieces are divided according to the logical connection, cells that should be classified in the same circuit block are not classified into different circuit blocks. Furthermore, when allocating n circuit blocks to n divided regions, an optimal allocation can be performed quickly by using a genetic algorithm so as to satisfy a predetermined constraint condition.

  In an embodiment of the present invention, a computer equipped with a storage device, and a special cell such as a cell group in which at least one macro cell, a soft macro expanded cell group or a skew is a problem from the storage device, and a plurality of standard cells, and Circuit connection information, design constraints, and other data necessary for automatic placement and routing are read out, and the layout of the semiconductor integrated circuit is created by placing and routing the special cells, the standard cells, and the power supply lines. The outline is as follows.

(1) A special cell (one or two or more) is arranged in a predetermined specific area in the arrangement area of the semiconductor integrated circuit, and a power line for supplying power to the special cell is arranged and wired as required.
(2) Next, the current consumption of all the cells and each circuit block (consisting of classified cell groups) and the wiring lengths and wiring widths of the power supply lines to be arranged and wired are digitized and evaluated based on a certain standard.
(3) Next, on the semiconductor integrated circuit, the special cell arranged in (1) and the area other than the specific area where the power line of the special cell is arranged are temporarily divided into n divided areas. A new power supply line is laid out so that the current consumption value is balanced with the wiring length and width of the power supply line, that is, the special cell side is not affected by others.

  (4) Next, in consideration of logical connection and the like, that is, the circuit portion excluding the special cell in the logic circuit is divided into n pieces so that cells having a close logical relationship are included in the same circuit block. . In these (3) and (4), n circuit blocks other than special cells are evaluated according to the procedure (2) (current consumption of cells and circuits, wiring length and wiring width of power supply lines), and Depending on the evaluation result, the wiring width of the power supply line is changed or the branch is changed, and the divided areas and the number n and the contents and the number n of the circuit blocks are changed.

  (5) Next, n circuit blocks are allocated and arranged in n divided areas. At this time, priority is given to the weight of connection with a special cell already arranged. That is, a circuit block that is strongly associated with a special cell is arranged in a divided area near the special cell. Note that the current consumption of n circuit blocks to some extent and the power supply capability of existing wiring are also taken into consideration. Again, the allocation of n circuit blocks to the n divided areas is repeated until a balance is obtained in the evaluation of the procedure (2). In the above description, the arrangement and wiring of the signal lines are out of the scope of the present invention, and thus the description thereof is omitted.

  As described above, after the special cell and the power supply line for supplying power to the special cell are first arranged and wired, the n divided areas where the power supply line is arranged and wired so as to balance the entire semiconductor integrated circuit are logically connected. Since n circuit blocks obtained by dividing the circuit are arranged, the special cell is not affected by the arrangement and wiring of the subsequent circuit block, and the n circuit blocks have the same circuit in which the logical relationship is close. Since it is divided so that it is included in a block, cells that should be classified in the same circuit block are not classified as different circuit blocks, and circuit blocks that are closely related to special cells Since it is arranged close to the cell, optimal placement and routing can be realized, and the power consumption of the entire circuit can be prevented from being locally biased while ensuring the delay time within the required specifications. Hereinafter, specific examples will be described in detail.

  FIG. 1 is a flowchart of a placement and routing process according to the first embodiment, and FIG. 2 is a diagram showing a region (floor) of a semiconductor integrated circuit as a placement and routing target. First, a special cell is placed in the specific area 2 previously assigned to the special cell (step S1), and then a power supply line is placed and wired to the special cell (step S2). Then, in the region on the semiconductor integrated circuit, the region other than the special region 2 of the special cell is divided into n (seven in FIG. 2 for simplicity) to obtain divided regions 1, 3 to 8, and power supply lines Are arranged (step S3). Next, the circuit portion of the logic circuit excluding the circuit by the special cell is divided into n circuit blocks (step S4). The above processing steps S1 to S4 correspond to the above (1), (3), and (4). In steps S3 and S4, as described above, n circuit blocks are evaluated by the current consumption of cells and circuits, the wiring length and wiring width of the power supply line, and the wiring width of the power supply line is changed according to the evaluation result. Alternatively, the branch is changed, and the divided areas and the number n and the contents and the number n of the circuit blocks are changed.

  The next steps S6 to S10 are processes corresponding to the above (5) in which n circuit blocks are allocated and arranged in n divided areas. The allocation of the n circuit blocks is based on the weight of the connection between the circuit blocks (including the connection between the special cell and other circuit blocks), and the current supplied to each circuit block is consumed by each block. Evaluate the constraints such as whether or not the current is satisfied, and arrange them. When such allocation is simply calculated in detail, a calculation explosion occurs when the number of n increases, so the following means are adopted.

  That is, the problem of which circuit block is allocated and arranged in which divided area is regarded as a modification of the traveling salesman problem, and a realistic solution is obtained using a genetic algorithm. In this case, it is considered as a city (gene) that circulates the circuit block. As an evaluation function, a connection weight between circuit blocks, a power supply capability, and a current consumption amount are set. First, weighting between circuit blocks is set in advance. The distance between circuit blocks may be measured or normalized. As an evaluation function for connection between circuit blocks, for example, a function of f (x) = [weighting / distance] is defined. Similarly, an evaluation function is set such that it is positive if the current consumption of the circuit block with respect to the power supply capability of the power supply line falls within a certain range, and negative if it exceeds. Thereafter, when a simulation is performed in which each circuit block (city) is regarded as one bit of a gene and a minimum value is obtained, an optimal allocation arrangement is obtained.

  Hereinafter, the genetic algorithm is applied with reference to FIGS. 3 and 4 to describe how n circuit blocks are arranged in n divided regions. The divided region corresponds to a gene locus, and the circuit block corresponds to a gene. First, as shown in FIG. 3A, which will be described later, the circuit blocks A, PLL, PLL-c, and B to F are sequentially assigned to the divided area 1, the specific area 2, and the divided areas 3 to 8. A combination P2 in which the combination P1, circuit block D, PLL, F, A, E, B, PLL-c, and C are assigned in order is set as an initial combination (parent gene group) (step S5 in FIG. 1). Here, for the sake of simplicity, the number of combinations is two.

  However, the circuit block PLL is a special cell such as a macro cell and is fixed to the specific area 2. The circuit block PLL-c is a circuit block closely related to the circuit block PLL. In the combination P1, the circuit block PLL-c is arranged in the divided region 3 near the circuit block PLL. It is arranged.

  Next, each circuit block allocated to the predetermined divided area 1, the specific area 2, and the divided areas 3 to 8 is evaluated (except for the circuit block PLL) as described above (step S6 in FIG. 1). This evaluation is performed under the first to third constraints as shown in FIG.

  In the first constraint, as an example, the circuit blocks A-B and A-C will be described. The number of wirings between A and B is X1 (for example, 10), and between A and C is X2 (for example, 5). The number of signal lines is X, and the distance between circuit blocks (actual measurement between the central points or Manhattan distance) is Y. “f = X × (1 / Y) "is used as the evaluation function. The evaluation f increases as the number of wirings between circuit blocks increases and the distance decreases. In the second constraint, an evaluation is made based on whether or not the amount of power supplied to the circuit block (determined by the width and number of power supply lines, etc.) is greater than the amount of power consumed by the circuit block. When “quantity”, the evaluation is increased (plus). In the third constraint condition, a ratio “power consumption / power supply amount” between the amount of power supplied to the circuit block and the power consumption of the block is obtained, and the smaller this is, the higher evaluation is given. If there is a variation of more than%, the evaluation value is the lowest value.

  As described above, a plurality of combinations (P1, P2, etc.) are evaluated, and it is determined whether the average of the evaluation of each circuit block of each combination is sufficiently increased or converged to the optimal solution. (Step S7 in FIG. 1), if there is a combination corresponding to it, the process ends as YES, but if NO, the process proceeds to the next step S8.

  In this step S8 (淘汰), 淘汰 is performed by deleting the lower p% of the evaluation values for the plurality of combinations created in step S5. Then, in the next step S9 (proliferation), the number of parents of the top p% of the evaluation value is doubled to increase the number of combinations. Next, a new combination (child) is created from the excellent combination (parent) obtained as a result of the above by crossover or mutation in step S10 (evolution).

  Here, a method of creating two combinations (children) Q1 and Q2 by one-point crossover from the combinations (parents) P1 and P2 will be described with reference to FIG. In addition, it demonstrates here with a gene. FIG. 5 is a flowchart thereof. First, the first half of parent P1 is copied to the first half of child Q1, and the first half of parent P2 is copied to the first half of child Q2 (step S21). Thus, “A, PLL, PLL-c, B” is copied to the first half of the child Q1, and “D, PLL, F, A” is copied to the first half of the child Q2.

  Next, a gene in the second half of parent P1 and not used in the first half of child Q2 is copied to the second half of child Q2, and is used in the second half of parent P2 and in the first half of child Q1. A gene that has not been copied is copied to the second half of the child Q1 (step S22). As a result, “E, *, *, C” is copied to the second half of the child Q1, and “C, *, E, *” is copied to the second half of the child Q2. * Is a divided area that is used in the first half and is not copied.

  Next, genes that are not stored in the child Q1 are searched for from the smaller locus of the parent P2 and stored in order, and genes that are not stored in the child Q2 are searched for from the smaller locus of the parent P1 and stored in order. (Step S23). Thereby, D is stored in the locus 6 of the child Q1, F is stored in the locus 7, PLL-c is stored in the locus 6 of the child Q2, and B is stored in the locus 8. As described above, children Q1 and Q2 in which the latter half of the parent P1 and P2 are changed are created.

  In the case of mutation, a child Q3 is created by alternately exchanging some genes of the parent P1. In the example of FIG. 3B, the child P3 is created by exchanging the genes PLL-c and D of the parent P1.

  After creating a plurality of new combinations by crossover or mutation in step S10 as described above, the process returns to step S6 again to evaluate each circuit block for each combination, and the determination is made in step S7. By processing a plurality of generations with one round of steps S6 to S10 as one generation, the average value of the evaluation of all circuit blocks is sufficiently increased in step S7, or one combination converged to the optimal solution is obtained relatively quickly. Can do.

It is a flowchart of Example 1 of the automatic placement and routing method of the present invention. It is explanatory drawing of the division | segmentation of the arrangement | positioning area | region of a semiconductor integrated circuit. It is explanatory drawing of crossover and mutation of a genetic algorithm. It is explanatory drawing of the constraint conditions for evaluation in a genetic algorithm. It is a flowchart of crossover in a genetic algorithm.

Explanation of symbols

1, 3-8: Divided region (locus)
2: Specific region (locus)
A to F: circuit block (gene)
PLL: Special cell (gene)
PLL-c: Circuit block (gene) closely related to the special cell PLL
P1, P2: Combination of circuit blocks (parent gene group)
Q1-Q3: Combination of circuit blocks (child gene group)

Claims (4)

A computer having a storage device reads out from the storage device at least one macro cell, a soft macro expanded cell group, or a special cell such as a cell group having a skew problem and a plurality of standard cells, and the special cell and the standard In an automatic placement and routing method for creating a layout of a semiconductor integrated circuit by arranging and wiring cells and power supply lines,
A first step of disposing the special cell in a specific region in the disposition region of the semiconductor integrated circuit;
A second step of arranging and wiring a first power supply line for supplying power to the special cell in the arrangement region;
In order to balance the current consumption of the special cell and the first power supply line, an area other than the specific area in the arrangement area is divided to form n divided areas, and the power supply lines are arranged and wired. A third step,
A fourth step of dividing a circuit excluding the circuit by the special cell in the logic circuit composed of the semiconductor integrated circuit to form n circuit blocks by dividing according to a logical connection;
A fifth step of arranging the n circuit blocks in the n divided regions according to a logical connection of the logic circuits and a current supply amount supplied to the n divided regions;
An automatic placement and routing method comprising: In the automatic placement and routing method according to claim 1,
The formation of the n divided regions in the third step and the formation of the n circuit blocks in the fourth step are performed by the standard cell and the n circuit blocks constituting the n circuit blocks. The automatic placement and routing method is performed according to the current consumption and the wiring length and the wiring width of the power supply lines arranged and wired in the n divided regions. In the automatic placement and routing method according to claim 1 or 2,
In the fifth step, the n divided regions are used as loci, the n circuit blocks are used as genes, and the relationship between the n circuit blocks and between the n circuit blocks and the special cell. The n circuit blocks for the n divided regions are constrained by the relationship between the tightness of power and the amount of power supplied to the n circuit blocks and the amount of current consumed by the n circuit blocks. An automatic placement and routing method characterized in that the optimal allocation of a signal is performed by a genetic algorithm. In the automatic placement and routing method according to claim 3,
The genetic algorithm creates a plurality of combinations of the allocation of the n circuit blocks for the n divided regions, evaluates each circuit block in each combination according to the constraint condition, and determines according to the evaluation result, An automatic placement and routing method characterized by selecting one optimal combination that substantially satisfies the constraint conditions by repeating multiplication and evolution.

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