JP2005153366A - Pulse width modulation signal generation device and image forming device with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse width modulation signal generation device and an image forming device with the same, that reduce image mackles by synchronizing the start of image data writing with a main scan synchronization signal by a delay circuit having a prescribed number of delay stages and outputting an image signal faithful to the density of the image data by correcting the number of delay stages per basic clock varying in accordance with an operation environment. <P>SOLUTION: The pulse width modulation signal generation device has a plurality of delay elements sequentially delaying and outputting a main scan synchronization signal inputted and image data subsequently inputted, detects the number of stages of remaining delay elements until the main scan synchronization signal is outputted for each basic clock driving the pulse width modulation signal generation device when the main scan synchronization signal is delayed, propagated and outputted by the delay means, synchronizes the number states detected in a basic clock preceding a basic clock where zero is detected for the number of remaining stages with the main scan synchronization signal by delaying from the basic block as the number of delay adjustment stages. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a pulse width modulation signal generation apparatus, and more particularly to a pulse width modulation signal generation apparatus that generates a signal for driving a semiconductor laser for image formation and an image forming apparatus including the same.

  In an image forming apparatus, as an exposure apparatus that exposes an image on a photoconductor, a laser beam emitted from a semiconductor laser oscillator is reflected by a polygon mirror that has a plurality of reflecting surfaces and rotates at high speed, and the axial direction of the photoconductor There is a semiconductor laser device that performs exposure by scanning according to an image signal. In this case, the beam detector attached to a position slightly deviated from the scanning start position detects the laser beam moving to the scanning start position, and the detection timing of the detection signal (referred to as main scanning synchronization signal or BD signal). Based on the above, the scanning start timing on the photosensitive member is taken.

  For example, when a cylindrical photosensitive member rotates about its axis, the laser beam scans the surface of the photosensitive member from one end to the other end along the axis. This is so-called main scanning, and one main scanning or the amount of scanning is sometimes referred to as a scan line. The start of main scanning, that is, the writing start for each scan line is normally controlled in synchronization with a clock signal. Specifically, for example, the control for starting writing for each scan line at the rising edge of the clock signal that appears next from the end edge of the BD signal after the laser beam passes through the beam detector, or predetermined from the start edge of the BD signal Conventionally, control for starting writing at the rising edge of the clock signal delayed by the number of clocks has been performed.

  In such write control, since the BD signal is not synchronized with the clock signal, the start of writing for each scan line varies by one cycle of the clock signal at the maximum. This variation appears in the finally formed image, and so-called image blurring such as a jagged line is generated, which is a factor that greatly deteriorates the image quality.

  Further, during the main scan, exposure corresponding to all the pixels for each scan line is performed according to the density of each pixel. Therefore, a drive pulse having a pulse width corresponding to the density of each pixel is generated, and one drive line is scanned by repeatedly turning these drive pulses on and off. As a conventional technique for generating a pulse width corresponding to the density of each pixel, for example, there is a method of generating a drive pulse having a desired width by generating a triangular wave and changing this cycle. However, if the operating environment such as the power supply voltage and temperature changes as the image formation speed increases and the resolution increases, it becomes difficult to generate a drive pulse with an accurate width according to the pixel density. There was also a problem that the reproducibility deteriorated.

  In order to solve the above problem, Patent Document 1 discloses an image forming apparatus that performs gradation representation of an image by pulse width modulation, based on a predetermined basic clock, an offset delay amount and a delay from an input image signal. Means for generating an amount, a unit delay amount, and a reference signal, and two types of first delay pulses having a predetermined pulse width delayed based on the offset delay amount, the delay amount, the unit delay amount, and the reference signal. And a means for generating a second signal having a pulse width corresponding to the phase difference between the two types of first signals, and performing pulse width modulation according to the second signal. Is disclosed.

Further, in Patent Document 2, in order to cope with the above-described problem of fluctuations in the drive pulse width, dots that selectively generate a plurality of dot clocks having different periods as dot clocks that define the recording time per pixel. The input image signal is converted so that the duty ratio with respect to the dot clock cycle of the modulation pulse width obtained for the input image signal based on the dot clock cycle and the dot clock cycle has a fixed relationship with the input image signal. Disclosed is a semiconductor laser driving device having a lookup table and a drive pulse signal generating means for generating a laser drive pulse signal having a pulse width corresponding to a signal converted by the lookup table with reference to the dot clock. Yes.
JP-A-6-278321 Japanese Patent Laid-Open No. 5-48181

  However, since the image forming apparatus according to Patent Document 1 generates a drive clock having a predetermined pulse width based on the basic clock, a drive pulse having a width corresponding to the pixel density can be generated, but writing starts for each scan line. It does not disclose solving the problems of the prior art regarding the position. In addition, since a drive pulse is generated by combining delays generated by a delay circuit in which delay elements are connected in series, it is conceivable that the delay time varies and the width of the drive pulse varies depending on the power supply voltage, temperature, and the like.

  The semiconductor laser driving device according to Patent Document 2 generates a driving pulse having a pulse width corresponding to the pixel density using a lookup table. In order to keep the duty ratio constant, the influence of fluctuations in the power supply voltage and temperature is reduced. However, regarding the write start position for each scan line, it is not disclosed to solve the problems of the prior art. Also, two circuits that generate different pulse widths are required, and in particular, the second pulse width generation circuit generates a pulse width according to the data converted by the lookup table. For this reason, the second pulse width generation circuit that generates the actual pulse based on the pulse width data is influenced by the power supply voltage, temperature change, etc. The pulse width is likely to fluctuate.

  The present invention has been made in view of such a situation, and a delay circuit having a predetermined number of delay stages detects the number of delay stages for each basic clock, and the result is added to the image data. By synchronizing the start of writing with the main scanning synchronization signal, image blurring is reduced, and the number of delay stages for each basic clock, which varies depending on the operating environment, is corrected so that the image signal faithful to the density of the image data It is an object of the present invention to provide a pulse width modulation signal generation apparatus that performs output and an image forming apparatus including the same.

  In order to achieve the above object, in the present invention, an image signal for performing image formation based on pixel data including pixel density information while repeatedly scanning based on a main scanning synchronization signal is used as the main scanning synchronization signal. In the pulse width modulation signal generation device that outputs in synchronization with each other, the pulse width modulation signal generation device comprises a plurality of delay elements that sequentially delay and output the input main scanning synchronization signal and the pixel data input thereafter. When the main scanning synchronization signal is delayed and propagated by the delay means and output, the remaining until the main scanning synchronization signal is output for each basic clock that drives the pulse width modulation signal generator The number of stages of the delay element is detected, and the number of stages detected by the basic clock immediately before the basic clock in which the remaining number of stages is detected as 0 is set as the number of delay adjustment stages. By delaying for an image signal is always configured to be synchronized with the main scanning synchronization signal is outputted after a predetermined time from the main scanning synchronizing signal for each scan.

  The pulse width modulation signal generation device of the present invention further includes dot clock generation means for generating a dot clock that divides a basic clock to define a processing time for each pixel, and pixel data according to the contents thereof. The conversion means for converting the rising position and the falling position of the pulse, represented by the number of delay stages of the delay means per dot clock cycle, and the rising position and the falling position of the pixel data converted by the conversion means, respectively. Delay adjustment means for adding the number of delay adjustment stages to the rising position where the number of delay adjustment stages is added is delayed by the basic clock equivalent to the quotient divided by the number of delay stages per basic clock, and then divided The falling position with the delay adjustment stage number added to the delay element corresponding to the remainder is added to the delay per basic clock. From the basic clock delays corresponding to the quotient obtained by dividing by the number of stages, by input to the delay elements corresponding to the division the remainder is configured to output an image signal from the delay means.

  Further, the pulse width modulation signal generating apparatus of the present invention causes the calibration signal to be input to the delay means when the main scanning synchronization signal and the pixel data are not input to the delay means, and while the calibration signal is delayed and propagated through the delay means, In this configuration, the number of delay stages per period of the basic clock is detected, and the number of delay stages per period of the dot clock is corrected according to the detection result.

  Further, the pulse width modulation signal generating apparatus of the present invention has a main scanning synchronization signal for each basic clock that drives the pulse width modulation signal generating apparatus when the main scanning synchronization signal is delayed and output by the delay means. The number of remaining delay elements until output is detected, the number of stages detected by the basic clock two times before the basic clock where the remaining number of stages is detected as 0, and the number of stages detected by the previous basic clock. And the number of delay stages per dot clock cycle is corrected according to the detection result.

  In the pulse width modulation signal generation device of the present invention, pixel data moves forward, centrally, or backward in parallel with the rising and falling positions of pixel data within one period of the dot clock together with density information. It is the structure containing the gathering information to be made.

  An image forming apparatus according to the present invention includes the pulse width modulation signal generating device according to any one of the claims to form an image.

  According to the pulse width modulation signal generating apparatus based on the present invention, the main scanning synchronization signal (BD signal) and the image signal are input to the same delay means composed of a plurality of delay elements, and the actual number of delay stages with respect to the basic clock is detected. In order to adjust the pixel data, the image signal driven by the basic clock can always be synchronized with the main scanning synchronization signal with a simple structure even if the main scanning synchronization signal and the basic clock are not synchronized. Is possible.

  In addition, according to the pulse width modulation signal generating apparatus based on the present invention, the dot clock is converted into the number of delay stages of the delay means, and the pixel data is processed with the number of delay stages based on the dot clock. Therefore, even if the dot clock is changed, there is no need to change the circuit, and conversion from pixel data to an image signal can be realized with a simple circuit.

  Furthermore, according to the pulse width modulation signal generation device based on the present invention, the number of delay stages per dot clock is calibrated almost regularly on the basis of the basic clock even if the operating environment such as temperature and voltage fluctuates. For this reason, the main scanning synchronization signal and the image signal are periodically synchronized to form an image without blurring.

  Alternatively, according to the pulse width modulation signal generating device based on the present invention, even if the operating environment such as temperature and voltage fluctuates, the number of delay stages per dot clock is calibrated for each scan based on the basic clock. The main scanning synchronization signal and the image signal are always kept synchronized, and image formation without blurring is possible.

  According to the pulse width modulation signal generating apparatus based on the present invention, since the pixel data includes the shift information together with the density information, it can be used for processing such as image smoothing.

  Since the image forming apparatus according to the present invention includes the above-described pulse width modulation signal generation device, the effect of the pulse width modulation signal generation device according to the present invention can be utilized.

  Hereinafter, the details of the present invention will be described with reference to the accompanying drawings. First, the image forming apparatus according to the present embodiment will be described in detail with reference to FIG. FIG. 1 is a schematic front view showing a configuration of an image forming apparatus to which the present invention is applied. The image forming apparatus 1 is configured as a printer. The image forming apparatus 1 stores an operation unit 2 including a display unit 2a and an operation input unit 2b, and a sheet P as a recording medium, and is configured to be capable of being pulled out toward the front in the figure. A paper cassette 3, a paper feed mechanism 4 that feeds paper P one by one from the paper feed cassette 3, an image forming unit 5 that forms an image, and a photoconductor 5 a included in the image forming unit 5 are provided. A laser exposure device 11 for exposure, a pulse width modulation signal generation device 7 for generating an image signal input to the laser exposure device 11, a fixing unit 8 for fixing an image on paper, and a discharge for depositing discharged paper A paper tray 9 and a control unit 10 that controls the entire image forming apparatus 1 are schematically configured. In the drawing, the alternate long and short dash line represents the conveyance path of the paper P.

  FIG. 2 is a top perspective view of the laser exposure apparatus 11 according to the present invention. In FIG. 2, reference numeral 11 is a laser exposure apparatus. As main components, 12 is a casing, 13 is a semiconductor laser light source that emits a laser beam, 14 is a polygon mirror that rotates at high speed and reflects the laser beam in the main scanning direction, 15 is an fθ lens, 16 Is a beam detector that detects the presence or absence of a laser beam, 17 is a condenser lens that converts the laser beam into parallel light together with the fθ lens 15, and 19 is provided to change the optical path of the laser beam that has passed through the condenser lens 17 to a right angle. A total reflection mirror 18 is a slit (exit port) formed in the housing 12 so as to guide the optical path of the laser beam from the total reflection mirror 19 to the irradiation surface of the scanning medium such as a photosensitive member.

  In the laser exposure apparatus 11, the polygon mirror 14 rotates at high speed in the clockwise direction when viewed from above. Therefore, the laser beam emitted from the semiconductor laser light source 13 is reflected in the direction of the fθ lens 15 by the rotating polygon mirror 14. Further, since the side surface of the polygon mirror 14 is constituted by a reflecting surface that forms a polygon (in FIG. 1, for example, a hexagon), the laser beam is detected by the beam detector 16 along with the clockwise rotation of the polygon mirror 14, Thereafter, main scanning is performed line by line while moving the total reflection mirror 19 from the right end to the left end in the figure.

  The image forming apparatus 1 shown in FIG. 1 is connected to an information processing apparatus (not shown), and print data is transmitted from the information processing apparatus. In this case, if the image forming apparatus 1 is a printer that can process the PDL language (page description language), the control unit 10 or a printer controller (not shown) performs processing for developing the pixel data constituting the image. If the image forming apparatus 1 is a printer that cannot process the PDL language, the print data transmitted from the information processing apparatus is composed of pixel data.

  Such pixel data is sent to the pulse width modulation signal generation device 7 via the control unit 10. The pulse width modulation signal generation device 7 generates a pulse having a width according to each pixel data, that is, according to the gradation (density) of each pixel, and drives the semiconductor laser light source 13 shown in FIG. The signal is sent to the laser exposure apparatus 11 as a signal. While the semiconductor laser light source 13 is scanning, the laser exposure device 11 modulates (turns on) the semiconductor laser light source 13 for a time corresponding to the pulse width of the image signal, and exposes one pixel (dot) to the photoconductor 5a. Form on top. The beam detector 16 emits a laser beam to generate a beam detector signal (BD signal or main scanning synchronization signal) for taking a scanning start timing for each line, and the BD signal is subjected to pulse width modulation. It is supplied to the signal generator 7.

  3A and 3B are diagrams for explaining the configuration of pixel data when image processing is performed on the print data and output as pixel data. FIG. 3A is a left-aligned pixel data of each density, and FIG. Is an example of pixel data of each density arranged in the center, and (c) is an example of pixel data of each density right-justified. In order to reduce the jaggedness peculiar to a digital image appearing in a printed image, the image forming apparatus 1 according to the present invention performs a so-called smoothing process on the image by an image processing unit (not shown). In the smoothing process, in order to reduce the jaggedness of the image, the position of the pixel within the maximum processing time of one pixel is divided into three positions, left-justified, centered, and right-justified, and pixels are formed continuously. Sometimes, each pixel forming a straight line or a curve is connected continuously and smoothly. Although not described in detail because it is not directly related to the present invention, the pixel data output from the image processing unit is configured as follows.

  FIG. 3 shows an example of pixel data. In the description of the embodiment according to the present invention, the pixel data output from the image processing unit is assumed to be composed of 6 bits, the shift data for determining the pixel position occupies the upper 2 bits, and the lower 4 bits are the density. The density in 16 gradations from 0 (white) to 15 (black) is shown. FIG. 3A shows pixel data left-justified for smoothing, and the density n is an arbitrary density from 0 to 15. FIG. 3B similarly shows pixel data arranged in the center. FIG. 3C shows pixel data right-justified.

  Next, the present invention will be described in detail by dividing it into a first embodiment and a second embodiment. In both the first and second embodiments, the image data is subjected to image processing and is input as individual pixel data to the pulse width modulation signal generation device 7, but the maximum exposure time of one pixel on one scan line Corresponds to one period of a so-called dot clock. In both the first and second embodiments, the basic clock for controlling the entire pulse width modulation signal generation device 7 is 250 MHz, and the dot clock uses 50 MHz obtained by dividing the basic clock. That is, in calculation, the maximum exposure time width of one pixel is 20 ns.

First embodiment

  FIG. 4 is a block diagram for outlining the pulse width modulation signal generating apparatus 7 according to the first embodiment of the present invention. As described above, the image processing unit 21 is not normally included in the pulse width modulation signal generation device 7 but is included in the control unit 10 of the image forming apparatus 1 or a printer controller (not shown). For the sake of explanation, a broken line is shown.

  Each 6-bit pixel data output from the image processing unit 21 is supplied to an LUT unit (look-up table) 22 configured by software or hardware. The LUT unit 22 converts the density of each pixel data into a density according to the characteristics of the image forming apparatus 1, particularly the development characteristics during image formation, and the rising edge and falling edge of the pulse according to the density. The position is converted into a unit of the number of delay stages per dot clock based on the number of delay stages of the delay chain circuit 26 described later. Thereafter, the edge conversion unit 23 compares adjacent pixels on one scan line, and when pixels that are originally continuous have the same falling edge position and rising edge position, such pixels are connected continuously. I do.

  Thereafter, the skew adjustment unit 24 corrects the shake of the write start position when the BD signal for each scan line described as a problem of the prior art is used as a reference, and performs the process of aligning the start positions for all the scan lines. Do. The rising edge position and the falling edge position corrected in this way and converted into units of delay stages are subtracted and input to the delay chain circuit 26 to generate an image signal having a pulse width, as will be described later.

  The delay chain circuit 26 outputs to the laser drive voltage generation circuit 30 an image signal having a pulse width corresponding to the pixel data gathering information and density in accordance with the input. The image signal is converted into a pulse having voltage capability and current capability for causing the semiconductor laser to emit light by the laser drive voltage generation circuit 30 and supplied to the laser exposure apparatus 11 (FIGS. 1 and 2), and exposure according to pixel data is performed. Done. Note that the laser drive voltage generation circuit 30 and the laser exposure apparatus 11 are usually not included in the pulse width modulation signal generation apparatus 7 and are therefore shown by broken lines. Of course, it is also possible to include the laser drive voltage generation circuit 30 in the pulse width modulation signal generation device 7.

  In the pulse width modulation signal generation device 7, as shown in FIG. 4, all operations after the edge conversion unit 23 are performed based on the basic clock. On the other hand, the BD signal is not linked to the basic clock, and is input to the delay chain circuit 26 with a different shift for each scan line. However, if the image signal generated in synchronization with the basic clock is not synchronized with the BD signal, the problem arises that the start position varies for each scan line, as described in the prior art.

  The switching circuit 27 selects the BD signal supplied for each scan line before starting scanning, and inputs it to the delay chain circuit 26. Based on the BD signal, a correction value for synchronizing the image signal with the BD signal for each scan line, that is, a skew is detected as the number of delay stages of the delay chain circuit 26 and is output to the skew detector 28. The output skew is fed back to the skew adjusting unit 24 and added from the leading pixel data, so that the image signal is delayed.

  When pixel data is not processed between the print job and the next print job or between the page being printed and the next page, calibration is performed from the image processing unit 21 or the outside via the switching circuit 27. A signal is input to the delay chain circuit 26. Based on the calibration signal, the number of delay stages per basic clock cycle of the delay chain circuit operating under a certain operating environment is detected by the skew detector 28 as a calibration value. This calibration value is fed back to the LUT unit 22, and the number of delay stages per dot clock used by the LUT unit 22 is changed at the timing described above. That is, even if the delay speed of the delay chain circuit 26, that is, the number of delay stages per basic clock, varies depending on the operating environment, it is possible to perform calibration with feedback at the above timing.

  Next, the operation of the LUT unit 22 will be described with reference to FIG. FIG. 5 is a diagram illustrating a method in which pixel data composed of shift data and density data is converted into a rising edge position and a falling edge position in units of delay stages. In this example, as described with reference to FIG. 3, the density is expressed by 16 gradations of 0 (white) to 15 (black). The larger the interval from the rising edge position to the falling edge position (in the figure, the ↑ edge position and the ↓ edge position, respectively), the greater the density value.

  Based on the calibration signal described above, the calibration value per basic clock is fed back to the LUT unit 22, but since the LUT unit 22 processes in units of dot clocks, the number of delay stages per basic clock is replaced with the number of delay stages per dot clock. . For example, in this embodiment, the total number of delay stages of the delay chain circuit 26 is 128. When there is no change in the operating environment, for example, a delay of 0.1 ns per stage is used. Therefore, the number of delay stages per basic clock generated at 250 MHz is 40. Since the frequency of the dot clock is 50 MHz, the number of delay stages per dot clock is 200. That is, the maximum density 15 is 200 when the exposure is performed for one dot clock, and the maximum density 15 is 200 in terms of the number of delay stages. The minimum density 0 is 0 when replaced with the delay stage number unit.

  Based on the above idea, conversion of the left-justified pixel data shown in FIG. Originally, the LUT unit 22 also corrects the density data according to the characteristics of the image forming apparatus 1, but for the sake of simplicity of explanation, it is assumed here that the value of the density data is linearly converted. When the total delay stage number 200 per dot clock is assigned to the maximum density 15, as shown in the figure, the density n is left-justified, so that the rising edge position is 0 and the falling edge position is 200 × n / The number of delay stages can be expressed by 15 (rounded off after the decimal point). Note that the falling edge position of density 15 is originally 200, but when the subsequent pixel rises to 0, the fall and the rise occur almost simultaneously, and noise and pixel breaks may occur. Therefore, when the falling edge position is 200, the maximum value that can be handled by the LUT unit 22 configured by software or hardware is assigned. In this example, the maximum value is set to 4095.

  Next, conversion of pixel data in the central arrangement shown in FIG. 5B will be described. The basic idea is to convert so that the rising edge position is located at the center of the maximum density width, that is, the front half 100 of the total delay stage number 200, and the falling edge position is located at the center of the rear half 100. . When the falling edge position is 200, 4095 is set as described above. The rising edge position of the density n can be expressed as 100-100 × n / 15 (rounded off after the decimal point), and the falling edge position can be expressed as 100 + 100 × n / 15 (rounded down after the decimal point).

  Further, conversion of right-justified pixel data shown in FIG. 5C will be described. The basic idea is that the left-justified base point is reversed left and right. The rising edge position of the density n is 200−200 × n / 15 (rounded off after the decimal point), and the falling edge position is 200 in all densities, that is, 4095 for the above-described reason. Note that data with reference numerals d1 to d3 indicate examples of data used in the following description.

  Next, the operation of the edge conversion unit 23 will be described with reference to FIG. FIG. 6 is a diagram illustrating how the pixel data output from the LUT unit 22 is corrected by the edge conversion unit 23. FIG. 6A is a diagram illustrating an example in which the falling position and the rising position are generated as data even when adjacent pixel data is originally continuous. As shown in gap1 and gap2 in this figure, the falling edge position of the pixel of interest is 200 (the flag that indicates that 200 is replaced with 4095 in the LUT part), and the rising edge position of the next pixel data Is zero, the two pixel data are inherently continuous. However, if falling and rising occur simultaneously at the same position as in gap1 and gap2, there is a possibility that the output will be interrupted in the delay chain circuit 26 at the subsequent stage.

  Therefore, the edge conversion unit 23 performs conversion according to the following procedure so that no break occurs in the delay chain circuit 26. That is, when the falling edge position of the previous pixel is the end (position 4095) and the rising edge position of the target pixel is the tip (position 0), the rising edge position of the target pixel is replaced with 8191. Other than this, when the rising edge position of the previous pixel is 4095, the rising edge position of the target pixel is replaced with 200. When the trailing edge position of the rear pixel is the leading end (position 0) and the trailing edge position of the target pixel is 4095, the trailing edge position of the target pixel is replaced with 8191. In other cases, when the trailing edge position of the rear pixel is 4095, the leading edge position of the target pixel is replaced with 200.

  6B is a diagram illustrating edge positions when the pixel data d1, d2, and d3 illustrated in FIG. 5 are input to the edge conversion unit 23 as the pixel 1, the pixel 2, and the pixel 3. As illustrated in FIG. FIG. 6C is a diagram illustrating pixel data after the edge conversion unit 23 performs edge conversion (replacement) on the pixel data in FIG. 6B according to the above-described edge conversion procedure.

  Next, the skew adjustment unit 24 will be described. How the skew value for skew adjustment is generated will be described later. In the skew adjustment unit 24, the skew value detected by the skew detection unit 28 is fed back and is uniformly added to the rising edge position and the falling edge position of each pixel data by an arithmetic circuit (not shown). However, when those positions are 8191, they are not added. FIG. 6D is a diagram illustrating an example in which the skew adjustment unit 24 adds the above-described skew value to the pixel data illustrated in FIG. 6C output from the edge conversion unit 23. In this example, 10 skew values are added in units of delay stages, and corrected pixel data is shown.

  Thereafter, the pixel data is input to the delay chain circuit 26 via the pulse generation unit 25, and an image signal corresponding to the pixel data is output to the laser drive voltage generation circuit 30. Prior to the input of pixel data, the skew value is detected by the skew detector 28 at the start timing for each scan line. FIG. 7 is a timing chart for explaining the operation of the pulse generator 25 and the delay chain circuit 26.

  From the top of the figure, 50 MHz dot clock, 250 MHz basic clock, the rising edge positions of the pixel data of pixel 1, pixel 2, and pixel 3 shown in FIG. 6D, and their rising edge positions by two subtracting circuits The subtraction processing status of each, the falling edge position of each, and the subtraction processing status of those falling edge positions by two subtraction circuits. In this example, the maximum skew value fed back and added corresponds to the number of delay stages per period of the basic clock, and is 40. That is, when the maximum skew value 40 is added to the pixel data having the maximum exposure time, that is, the pixel data of the delay stage number unit 200 by the skew adjusting unit 24, the rising edge position of the pixel is 40, and the falling edge position is Becomes 240. Since the delay stage number 40 per basic clock period is sequentially subtracted from the maximum value 240, at least seven basic clock periods are required to complete the subtraction. In addition, since a new subtraction is performed on the next pixel every dot clock cycle, that is, every five basic clock cycles, two subtracters are required for each subtraction of the rising edge position and the falling edge position. It becomes. In FIG. 7, subtracters A and B and subtracters C and D are shown, which are alternately used for each pixel data in each set.

  In FIG. 7, the rising edge position 144 of the pixel 1 is input to the subtractor A, and the falling edge position 210 is input to the subtractor C. Then, the subtracter A performs subtraction for every 40 delay stages corresponding to one basic clock cycle until the subtraction result becomes less than 40. As a result, the rising edge position 144 = basic clock 3 + 24 is obtained. Similarly, the subtracter C performs subtraction for every 40 delay stages corresponding to one basic clock cycle until the subtraction result becomes less than 40. As a result, a falling edge position 210 = basic clock 5 + 10 is obtained.

  Next, the rising edge position 197 of the pixel 2 is input to the subtractor B, and the falling edge position 8191 is input to the subtractor D. Subtraction similar to that for pixel 1 is performed, and the rising edge position 197 = basic clock 4 + 37 and the falling edge position do not occur because the calculation result does not become less than 40. Thereafter, the rising edge position 8191 of the pixel 3 is input to the subtractor A, and the falling edge position 23 is input to the subtractor C. Then, the same subtraction is performed, and the rising edge position is not generated because the calculation result is not less than 40, and the falling edge position = basic clock 0 + 23. Each subtracter continues to subtract until a new edge position is input. For example, after the subtraction result becomes 24 in the subtracter A, the subtraction continues and becomes −16. However, when the result is negative, 8192-16 = 8176 is calculated. The timing is measured by the number of basic clocks of these calculation results, and the remaining numerical value is input to the flip-flop at the corresponding stage of the delay chain circuit 26 described later.

  Next, the operation of the delay chain circuit 26 will be described with reference to FIG. FIG. 8 is a logic circuit diagram of the delay chain circuit 26. In the upper part of the figure, 128 D-type flip-flops (hereinafter referred to as flip-flops) 100_0 to 100_127 are connected as shown in the figure. Let a specific flip-flop be 100_n. Data and a basic clock are input to the flip-flops 100_0 to 100_127 from terminals shown in the drawing, respectively. Further, when a signal is input to a clear terminal (not shown), the flip-flops 100_0 to 100_127 are cleared. The flip lip 100_127 side is referred to as upstream, and the flip lip 100_0 side is referred to as downstream.

  In the middle of the figure, 128 EX-NOR circuits 200_0 to 200_127 are connected as shown in the figure. A specific EX-NOR circuit is set to 200_n. The EX-NOR circuit 200_n has one input terminal connected to the output terminal of the flip-flop 100_n, and the other input terminal connected to the upstream (right adjacent to the drawing) output terminal of the EX-NOR circuit 200_n + 1. ing. The EX-NOR circuit 200_127 side is referred to as upstream, and the EX-NOR circuit 200_0 side is referred to as downstream.

  In the lower part of the figure, 128 D-type flip-flops (hereinafter referred to as flip-flops) 300_0 to 300_127 are connected as shown in the figure. A specific flip-flop is assumed to be 300_n. Data and a basic clock are input to the flip-flops 300_0 to 300_127 from terminals shown in the drawing, respectively. Further, when a signal is input to a clear terminal (not shown), the flip-flops 300_0 to 300_127 are cleared. The flip lip 300_127 side is referred to as upstream, and the flip lip 300_0 side is referred to as downstream.

  An input buffer 202 is provided on the upstream side of the EX-NOR circuit, and an output terminal thereof is connected to the other input terminal of the EX-NOR circuit 200_127. The output from the switching circuit 27 described with reference to FIG. 4 is input to the input buffer 202. That is, an input fixed at a LOW (hereinafter, L) level, or either a BD signal or a calibration signal is input. An output buffer 201 is provided on the downstream side of the EX-NOR circuit, and its input terminal is connected to the output terminal of the EX-NOR circuit 200_0. In addition, when scanning is performed based on pixel data from the output terminal of the output buffer 201, an image signal for causing the laser semiconductor to emit light is the laser drive voltage generation circuit 30 described with reference to FIG. Is output.

  The 128 flip-flops 100_0 to 100_127 receive the pixel data from the pulse generation unit 25, pass the pixel data to the EX-NOR circuits 200_0 to 200_127, generate a predetermined delay, and output the image signal from the output buffer 201. In addition, the 128 flip-flops 300_0 to 300_127 propagate either the BD signal or the calibration signal input to the switching circuit 27 (FIG. 4) through the EX-NOR circuits 200_0 to 200_127 from the upstream to the downstream. Read and output the state of progress. The output result is used for skew adjustment and calibration described later.

  Next, the calculation result of the pixel data of the pixels 1 to 3 subjected to the subtraction processing in the pulse generation unit 25 is input to the flip-flops 100_0 to 100_127 of the delay chain circuit 26, and has a predetermined width. The operation output as a pulse will be described with reference to FIGS. FIG. 9 is a timing chart showing a flow of outputting an image signal for causing the laser semiconductor to emit light from the subtraction result by the pulse generator 25, where (a) is a dot clock, (b) is a basic clock, ( c) shows an image signal output from the output buffer 201. In the figure, the data shown only by numbers means data in units of delay stages.

  As described above, the result of subtraction of the pixels 1 to 3 by the pulse generation unit 25 is that the rising edge position is the basic clock 3 + 24 and the falling edge position is the basic clock 5 + 10 in the pixel 1. In pixel 2, the rising edge position is the basic clock 4 + 37, and the falling edge position is not generated. In pixel 3, the rising edge position does not occur, and the falling edge position is the basic clock 0 + 23.

  First, the flip-flops 100_0 to 100_127 are cleared for each scan line. Thereafter, as the rising edge position of the pixel 1, three basic clocks have elapsed from the starting point of the dot clock corresponding to the pixel 1, that is, the first starting point of the basic clock, and the delay chain circuit 26 simultaneously with the rising of the fourth basic clock. The input terminal of the 24th flip-flop 100_23 from downstream is set to HIGH (hereinafter referred to as H). Then, the H level is output from the flip-flop 100_23 and input to one terminal of the EX-NOR 200_23, and is output from the output buffer 201 after being delayed by 24 stages, that is, through the number of 24 delay stages. Next, after five basic clocks have elapsed from the starting point of the dot clock corresponding to the pixel 1, the L level is given to the input terminal of the flip-flop 100_9. Then, the output of the flip-flop 100_9 becomes L level and is given to one input terminal of the EX-NOR circuit 200_9. Thereafter, the L level is delayed by 10 stages and the output of the output buffer 201 is set to the L level.

  Next, as the data of the pixel 2, after four basic clocks have elapsed from the starting point of the dot clock corresponding to the pixel 2, that is, simultaneously with the rising of the fifth basic clock, the input to the flip-flop 100_36 of the delay chain circuit 26 Set the terminal to H level. Then, similarly to the pixel 1, the H level is delayed by 37 stages, that is, is output as an H level from the output buffer 201 after passing through 37 delay stages. Next, since there is no falling edge position of the pixel 2, the processing of the pixel 3 is started. Further, since there is no rising edge position of the pixel 3, the processing shifts to the falling edge position of the pixel 3. That is, after 0 basic clocks have elapsed from the origin of the dot clock corresponding to the pixel 3, that is, at the same time as the rise of the basic clock corresponding to the origin of the dot clock of the pixel 3, the input terminal of the flip-flop 100_22 is at the L level. Is given. Then, the L level is delayed by 23 stages, that is, is output from the output buffer 201 as the L level after passing through the 23 delay stages. Therefore, the image signal shown in FIG. 9C is output from the output buffer 201 in order to irradiate the semiconductor laser corresponding to the pixels 1 to 3.

  Next, detection of the skew value fed back to the skew adjusting unit 24 will be described with reference to FIGS. 4, 8, and 10. FIG. 10 is a timing chart for detecting a skew value. FIG. 10A is an example in which the BD signal is delayed by 30 delay stages from the basic clock, and FIG. 10B is an example in which the BD signal is delayed by 20 delay stages from the basic clock. This is an example. In order to detect and feed back the deviation between the BD signal and the basic clock before starting scanning for each line, first, a clear signal is given to a clear terminal (not shown) of the flip-flops 300_0 to 300_127 in FIG. Subsequently, the switching circuit 27 in FIG. 4 selects the BD signal, and preparations for inputting the BD signal to the input buffer 202 in FIG. 8 are completed.

  From the top of FIG. 10A, the basic clock, the BD signal, the BD signal output from the output buffer 201, the output state of the flip-flops 300_0 to 300_127 by the skew detector 28, the skew value based on the output state, and the image signal are displayed. Each is illustrated.

  At time T1a, the BD signal is input to the most upstream EX-NOR circuit 200_127 via the input buffer 202. Thereafter, the BD signal is delayed and propagated downstream through the EX-NOR circuit 200_n. Therefore, the output of the EX-NOR circuit 200_n that changes every moment is received, and the output of the flip-flop 300_n is detected by the skew detector 28 every time the basic clock input to the flip-flop 300_n rises. In other words, the first detection is performed at time T2a. At that time, the BD signal has already advanced the EX-NOR circuit from the upstream by 10 delay stages, so that the H level is detected from flip-flop 300_1-27 to flip-flop 300_118 ( Number of remaining stages 118). In the figure, it is simply indicated by 118 and a numerical value.

  Since the number of delay stages per basic clock is 40, the flip-flop 300_127 to flip-flop 300_78 are detected as H level (remaining stage number 78) at the next basic clock. Similarly, the flip-flop 300_127 to the flip-flop 300_38 are detected as H level with the basic clock at time T3a (the remaining number of stages 38). Further, the delay propagates, and the BD signal is output from the output buffer 201 at time T4a when the remaining number of stages of 38 delays has elapsed. Thereafter, the flip-flop 300_0 is detected as H level with the basic clock at time T5a.

  In this example, the skew value fed back is the value detected by the skew detection unit 28 immediately before all the flip-flops 300_127 to 300_0 become H level, that is, the number of delay stages 38. This value is also a value detected by the previous basic clock in which the value detected by the skew detector 28 becomes zero. Furthermore, this value is also a value in which n of the flip-flop 300 — n detected by the basic clock or the number of remaining stages is less than the number of delay stages per basic clock (less than 40 in this example).

  Thereafter, data output based on the pixel data is started from time T6a, which is delayed by one basic clock (delay stage number 40) from time T5a when the value detected by the skew detection unit 28 becomes 0. As described above, since the skew values are added to the rising and falling edge positions of the pixel data, data output is substantially started from time T7a delayed by the skew value (38 in this example) from time T6a. Will be. When the skew value is detected, a delayed BD signal is output from the output buffer 201. Therefore, all the flip-flops 100_0 to 100_127 are output before the image signal is output from the same output buffer at time T7a. Is cleared, the EX-NOR circuits 200_0 to 200_127 are cleared, and the flip-flops 300_0 to 300_127 are also cleared.

  In the example of FIG. 10B, the BD signal is delayed by 20 delay stages from the basic clock. At time T1b, the BD signal is input to the most upstream EX-NOR circuit 200_127 via the input buffer 202. Thereafter, the BD signal is delayed and propagated downstream through the EX-NOR circuit 200_n. Therefore, the output of the EX-NOR circuit 200_n that changes every moment is received, and the output of the flip-flop 300_n is detected by the skew detector 28 every time the basic clock input to the flip-flop 300_n rises. In other words, the first detection is performed at time T2b. At that time, the BD signal has already advanced the EX-NOR circuit by 20 delay stages from the upstream, and therefore, the H level is detected from flip-flop 300_127 to flip-flop 300_108 ( Number of remaining stages 108). In the figure, it is simply indicated by 108 and a numerical value.

  Since the number of delay stages per basic clock is 40, the H level is detected from the flip-flop 300_127 to the flip-flop 300_68 with the next basic clock (remaining stage number 68). Similarly, the flip-flop 300_127 to the flip-flop 300_28 are detected as H level with the basic clock at time T3b (remaining stage number 28). Further, the delay propagates, and the BD signal is output from the output buffer 201 at time T4b when the remaining number of stages of 28 delays has elapsed. After that, the basic clock at time T5b is detected as the H level up to the flip-flop 300_0.

  In this example, the skew value fed back is the value detected by the skew detection unit 28 immediately before all the flip-flops 300_127 to 300_0 become the H level, that is, the delay stage number 28. This value is also a value detected by the previous basic clock in which the value detected by the skew detector 28 becomes zero. Furthermore, this value is also a value in which n of the flip-flop 300 — n detected by the basic clock or the number of remaining stages is less than the number of delay stages per basic clock (less than 40 in this example).

  Thereafter, data output based on the pixel data is started from time T6b, which is delayed by one basic clock (delay stage number 40) from time T5b when the value detected by the skew detection unit 28 becomes 0. As described above, since the skew values are added to the rising and falling edge positions of the pixel data, data output is substantially started from time T7b delayed by the skew value (28 in this example) from time T6b. Will be. When the skew value is detected, the delayed BD signal is output from the output buffer 201. Therefore, all the flip-flops 100_0 to 100_127 are output before the image signal is output from the same output buffer at time T7b. Is cleared, the EX-NOR circuits 200_0 to 200_127 are cleared, and the flip-flops 300_0 to 300_127 are also cleared.

  As is clear from the above description, in both the examples of FIGS. 10A and 10B, the time T7a or the time T7a Data output start of T7b is performed. Alternatively, pulse output at time T4a or T4b is performed after a certain number of delay stages have always passed since the rise of the BD signal at time T1a or T1b. Therefore, as described above, the time from the BD signal to the start of image signal output does not vary from scan line to scan line, and it is possible to control a semiconductor laser with little image quality degradation.

  In the control from the LUT unit 22 to the skew detection unit 28, the number of delay stages per basic clock has been described as 40. However, even if the same delay chain circuit 26 is used, the delay chain depends on temperature and power supply fluctuations. A case where the delay speed of the circuit 26 changes is also conceivable. In this case as well, the influence appears as a change in pixel density or a start timing of the scan line, but it does not occur for each scan line like the difference between the BD signal and the basic clock, so it affects the image quality. The impact is not significant. However, the influence cannot be ignored in a high-speed or high-resolution image forming apparatus. For this reason, in the present embodiment, the number of delay stages per basic clock generated due to fluctuations in the operating environment is corrected by the following method.

  In the control of the image forming apparatus 1, the delay stage number is calibrated for each print job or each print page. When calibration is performed, a calibration signal is selected as an input signal by the switching circuit 27 shown in FIG. The selected calibration signal is delayed and propagated downstream from the EX-NOR circuit 300_127 in FIG. Similar to the description of the skew detection unit 28, for each basic clock, the skew detection unit 28 detects the state of the flip-flops 300_127 to 300_0, and sequentially acquires the number of delay stages per basic clock. Finally, an average of these is calculated and set as the number of delay stages per basic clock to be fed back to the LUT unit 22.

  Actually, as shown in FIG. 4, when an output switching circuit 29 is provided on the output side of the skew detector 28 and the skew value is detected, the feedback to the skew adjuster 24 is made effective and the delay per basic clock is made. When detecting the number of stages, control is performed to enable feedback to the LUT unit 22.

  In the first embodiment described above, when the operating environment does not change abruptly, for example, when the image forming apparatus 1 is installed in a general office or indoor and used with a stable power source, the delay stage number is corrected between print jobs. This is effective because it is performed between pages. However, when the image forming apparatus 1 is installed outdoors or used under conditions where there is a high possibility that the operating environment in which the power supply voltage fluctuates rapidly changes, the second embodiment described below is used. Thus, a method of feeding back the correction of the number of delay stages for each scan line is more effective.

Second embodiment

  FIG. 11 is a block diagram for outlining the pulse width modulation signal generation device 7 of the second embodiment. In the description of the second embodiment, parts having the same configuration, operation or function as those in the first embodiment are denoted by the same reference numerals as those in FIG. 4, and different parts are denoted by the same reference numerals as those in FIG. Although additionally described, the description of the same portions as the first embodiment may be omitted or simplified.

  Unlike the LUT unit 22 of the first embodiment, the LUT unit 22b of the present embodiment does not convert the rising edge position and the falling edge position based on the pixel data shift data described with reference to FIG. Also, when falling and rising occur almost simultaneously, in order to prevent noise and pixel breaks, when the falling edge position is 200, it has been replaced with 4095 so that it can be distinguished by subsequent edge conversion. This work is also not performed. The LUT unit 22b of the second embodiment converts the density data portion of the pixel data composed of the shift data (2 bits) and the density data (4 bits) output from the image processing unit 21 to a theoretical density value. Only the data is converted into density data in line with the engine characteristics of the image forming apparatus 1. Therefore, although nonlinear conversion is normally performed, in order to make the explanation easy to understand, it is assumed that linear conversion is performed in this embodiment.

  Pixel data that has undergone density conversion is sent from the LUT unit 22b to the edge conversion unit 23b. The edge conversion unit 23 described in the first embodiment compares adjacent pixels of the pixel data converted by the LUT unit 22, and performs processing so that the pixels are completely continuously exposed when the pixels are continuous. However, the edge conversion unit 23b according to the second embodiment does not perform the process, and converts the rising edge position and the falling edge position based on the pixel data by a method described later. Further, the method includes a calibration process related to the number of delay stages per dot clock that is fed back for each scan line from the skew detector 28b according to the present embodiment.

  The edge conversion of the second embodiment will be specifically described with reference to FIG. FIG. 12 is a diagram illustrating a pixel data conversion method by the edge conversion unit 23b. Here, the theoretical density included in the pixel data output from the image processing unit 21 is N, and the maximum density width that can be converted by the LUT unit 22b is represented by n. Further, m is the number of delay stages per dot clock that is fed back from the skew detector 28b described later for each scan line (fixed to 200 in the first embodiment). Since the actual number of delay stages per dot clock detected for each scan line is fed back and used for edge position conversion, it is necessary to replace it with a large value even when adjacent pixels are continuous. There is no risk that the output pulse will be broken even if the edge position is accurate.

  Since the next skew adjustment unit 24, pulse generation unit 25, and delay chain circuit 26 are the same as those in the first embodiment, the description thereof will be omitted. However, in the second embodiment, since the configuration signal input upstream of the EX-NOR circuit of the delay chain circuit 26 is omitted, the switching circuit 27 shown in FIG. 4 is unnecessary.

  Next, the skew detector 28b has the same basic configuration and operation as the skew detector 28 of the first embodiment. Since the method for detecting the skew value for each scan line fed back to the skew adjustment unit 24 is the same, the description thereof is omitted. However, an arithmetic circuit for extracting the difference is added to the skew detection unit 28b of the second embodiment, and when the skew value is detected based on the BD signal, the number of delay stages per basic clock is also detected. Then, it is converted into the number of delay stages per dot clock, and the value is fed back to the edge conversion unit 23b as m.

  For example, as shown in FIG. 10A, when the BD signal rises and propagates through the EX-NOR circuit by delay, the skew detection unit 28b sets the H level states of the flip-flops 300_127 to 300_0 to 118, Like 78, 38, 0, it is detected at every rising edge of the basic clock. At this time, the newly added arithmetic circuit extracts the difference between the number of the H level two levels before the detection of 0 and the number of the H level the previous one, that is, the difference between 78 and 38. In this example, it is 40, and this numerical value is converted into m (200) which is the number of delay stages per dot clock, and fed back to the edge converter 23b.

  For example, when the delay state changes due to a change in the operating environment and is detected as 118, 81, 42, 3, 0 in the above example, the difference 39 between 42 and 3 is converted per dot clock, As m = 195, it is fed back to the edge converter 23b. In this way, since the number of delay stages in operation can be reliably detected simultaneously with the skew value calculated for each scan line, the edge conversion unit 23b can accurately convert the rising edge position and the falling edge position. Is possible. Further, since a new arithmetic circuit is added, the skew value output section and the delay stage number output section can be separated, and the output switching circuit 29 shown in FIG. 4 becomes unnecessary. Further, only the BD signal is sufficient for the delay propagation, and the calibration signal shown in FIG. 4 is not necessary.

  In both the first and second embodiments, an example in which the so-called image smoothing process is performed so that the shift data is included in the pixel data has been described. However, the present invention is also applied to pixel data having only density data without performing the smoothing process. Needless to say, you can. Moreover, although it demonstrated using a specific numerical value so that it may be understood easily, this invention is not limited to these numerical values.

1 is a schematic front view illustrating a configuration of an image forming apparatus to which the present invention is applied. 1 is a top perspective view of a laser exposure apparatus 11 according to the present invention. 4A and 4B are diagrams for explaining the configuration of pixel data when image processing is performed on print data and output as pixel data, where FIG. 5A is pixel data of each density left-justified, and FIG. The pixel data of each density, (c) is an example of pixel data of each density right-justified. It is a block diagram for outlining the pulse width modulation signal generation apparatus 7 concerning 1st Example of this invention. It is a figure which shows the method in which the pixel data which consist of a registration data and density | concentration data are converted into the rising edge position and falling edge position of a delay step number unit. FIG. 7 is a diagram illustrating how the pixel data output from the LUT unit 22 is corrected by the edge conversion unit 23, in which (a) illustrates an example in which adjacent pixel data is originally continuous, and (b) illustrates pixel data d1 to d3. (C) is a diagram showing pixel data subjected to edge conversion, and (d) is a diagram showing an example in which a skew value is added to the pixel data shown in (c). 4 is a timing chart for explaining operations of a pulse generation unit 25 and a delay chain circuit 26. 3 is a logic circuit diagram of a delay chain circuit 26. FIG. 4 is a timing chart showing a flow of outputting an image signal for causing a laser semiconductor to emit light from a subtraction result by a pulse generation unit 25, where (a) is a dot clock, (b) is a basic clock, and (c) is an output. An image signal output from the buffer 201 is shown. In the timing chart when detecting the skew value, (a) is an example in which the BD signal is delayed by 30 delay stages from the basic clock, and (b) is an example in which the BD signal is delayed by 20 delay stages from the basic clock. is there. It is a block diagram for outlining the pulse width modulation signal generation apparatus 7 of 2nd Example. It is a figure which shows the conversion method of the pixel data by the edge conversion part 23b.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 2 Operation part 2a Display part 2b Operation input part 3 Paper feed cassette 4 Paper feed mechanism 5 Image formation part 5a Photoconductor 7 Pulse width modulation signal generation apparatus 8 Fixing part 9 Paper discharge tray 10 Control part 11 Laser exposure apparatus DESCRIPTION OF SYMBOLS 12 Case 13 Semiconductor laser light source 14 Polygon mirror 15 Lens 16 Beam detector 17 Condenser lens 19 Total reflection mirror 21 Image processing part 22, 22b LUT part 23, 23b Edge position 24 Skew adjustment part 25 Pulse generation part 26 Delay chain circuit 27 Switching Circuits 28 and 28b Skew detection unit 29 Output switching circuit 30 Laser drive voltage generation circuit 100_0 to 100_127, 300_0 to 300_127 Flip-flop 200_0 to 200_127 EX-NOR circuit 201 Output buffer 202 Input buffer P Paper

Claims (6)

A pulse width modulation signal generating device that outputs an image signal for forming an image based on pixel data including pixel density information in synchronization with the main scanning synchronization signal while repeatedly scanning based on the main scanning synchronization signal In
The pulse width modulation signal generation device includes a delay unit including a plurality of delay elements that sequentially delay and output the input main scanning synchronization signal and the pixel data input thereafter.
When the main scanning synchronization signal is delayed and propagated by the delay means, the remaining delay elements until the main scanning synchronization signal is output for each basic clock for driving the pulse width modulation signal generation device For each scan by delaying the number of stages detected by the basic clock immediately before the basic clock where the remaining stage number is detected as 0 as the delay adjustment stage number. An apparatus for generating a pulse width modulation signal, wherein the image signal is always output after a predetermined time from the main scanning synchronization signal and is synchronized with the main scanning synchronization signal. The pulse width modulation signal generation device further includes a dot clock generation unit that divides the basic clock to generate a dot clock that defines a processing time for each pixel;
Conversion means for converting the pixel data into a rising position and a falling position of a pulse represented by the number of delay stages of the delay means per period of the dot clock according to the contents;
Delay adjustment means for adding the number of delay adjustment stages to each of the rising position and falling position of the pixel data converted by the conversion means;
The rising position to which the number of delay adjustment stages is added is delayed by a basic clock corresponding to the quotient divided by the number of delay stages per basic clock, and then input to the delay element corresponding to the divided remainder, and the delay adjustment The falling position to which the number of stages has been added is delayed by a basic clock corresponding to the quotient divided by the number of delay stages per basic clock, and then input to the delay element corresponding to the divided remainder from the delay means. The pulse width modulation signal generating apparatus according to claim 1, wherein an image signal is output.   When the main scanning synchronization signal and the pixel data are not input to the delay means, a calibration signal is input to the delay means, and the number of delay stages per period of the basic clock while the calibration signal propagates through the delay means The pulse width modulation signal generation device according to claim 2, wherein the number of delay stages per period of the dot clock is corrected according to the detection result.   When the main scanning synchronization signal is delayed and propagated by the delay means, the remaining delay elements until the main scanning synchronization signal is output for each basic clock that drives the pulse width modulation signal generation device The number of stages is detected, and the difference between the number of stages detected with the basic clock two times before the basic clock whose remaining number of stages is detected as zero and the number of stages detected with the previous basic clock is detected. 3. The pulse width modulation signal generating apparatus according to claim 2, wherein the number of delay stages per period of the dot clock is corrected according to a result.   The pixel data includes, together with the density information, shift information for moving the rising and falling positions of the pixel data in parallel to the front, center, or back as they are within one period of the dot clock. The pulse width modulation signal generation device according to any one of claims 2 to 4, wherein the pulse width modulation signal generation device is provided.   An image forming apparatus comprising the pulse width modulation signal generating device according to claim 1 to form an image.

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