JP2014233872A - Image processing apparatus, image formation apparatus, and drive pulse generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate and output a stable drive pulse without influence of a change in the operation rate of image processing.SOLUTION: A control unit 5 of an image formation apparatus 10 includes: a delay chain circuit 59; an edge converter 54; and a pulse generator 56. The delay chain circuit 59 is constituted by a plurality of delay elements converting pixel data to drive pulses driving an exposure scanning device. The pulse generator 56 inputs the pixel data to any of the delay elements in the delay chain 59 on the basis of the number of delay stages in response to pixel concentration information included in the pixel data. The edge converter 54 corrects the number of delay stages in addition to an edge conversion process. The edge converter 54 detects a delay amount of the delay chain circuit 59 in a state in which a voltage to the delay chain circuit 59 falls by a predetermined amount when a laser beam emitted from the exposure scanning device is out of a scan area, and corrects the number of delay stages based on the delay amount.

Description

  The present invention relates to an image processing apparatus, an image forming apparatus, and a driving pulse generation method for generating a driving pulse for driving an exposure scanning apparatus by sequentially delaying input pixel data.

  An electrophotographic image forming apparatus includes an exposure scanning device that exposes a photosensitive member by irradiating the photosensitive member with a laser beam. The exposure scanning device exposes the photosensitive member by scanning a laser beam corresponding to the image signal in the axial direction of the photosensitive member. Such scanning is also called main scanning, and the scanning amount in one main scanning is called a scanning line. During the main scanning, a laser beam moving to the scanning start position is detected by a beam detector attached at a location slightly deviated from the scanning start position. Conventionally, the scanning start timing on the photosensitive member is determined based on the detection timing of the detection signal (referred to as a BD signal) (see, for example, Patent Document 1).

  The laser beam scanned by the exposure scanning device is generated based on a drive pulse output from a PWM circuit included in the image forming apparatus. Specifically, a drive pulse having a pulse width corresponding to the density of each pixel included in the input image data is generated by a PWM circuit, and a pulse signal obtained by repeatedly turning these drive pulses on and off is exposed. A laser beam corresponding to the pulse signal is generated by being output to the scanning device. Therefore, the laser beam includes information on the density of each pixel in the scanning line. The pulse width (or duty ratio) of the drive pulse per pixel is the beam lighting time per pixel, and this pulse width is the density information per pixel.

  The PWM circuit is provided with a plurality of stages of delay circuits composed of a plurality of delay elements. This PWM circuit detects the number of delay stages in the delay circuit that determines the beam lighting time per pixel, and converts pixel data into the pulse width in accordance with the number of delay stages. Conventionally, since the delay amount (delay capability for each delay element) in the delay element changes depending on the operating environment, a calibration signal is input to the delay circuit at the timing when the BD signal is detected, and The delay amount of the delay circuit is detected to correct the number of delay stages.

JP 2005-153366 A

  However, the BD signal is detected at a timing outside the scanning area (outside the image area) as described above. Therefore, even if the delay amount of the delay circuit is detected at that timing, it is not possible to detect an accurate delay amount that reflects the change in the operating environment before and after image processing. Specifically, image processing is not performed at the timing when the BD signal is detected, and the operation rate of image processing is extremely low. On the other hand, when the image processing is actually performed after the laser beam is irradiated in the scanning region, the operation rate of the image processing is high. This difference in operating rate varies the delay amount of the delay circuit. That is, the higher the image processing operation rate, the larger the current consumption in the PWM circuit, and the greater the IR drop (voltage drop on the power supply wiring) of the power supply wiring. As the IR drop increases, the delay amount of each delay element in the delay circuit also increases in proportion thereto. For this reason, when the number of delay stages in each pixel is corrected based on the delay amount measured at the timing when the operation rate is low, a driving pulse having a pulse width corresponding to the density indicated by the pixel data is not generated with high accuracy. When image formation is performed in this state, the image quality may deteriorate.

  An object of the present invention is to provide an image processing apparatus, an image forming apparatus, and a drive pulse generation method capable of generating and outputting a stable drive pulse without affecting the operation rate of image processing.

  An image processing apparatus according to one aspect of the present invention includes a delay circuit, an input unit, and a correction unit. The delay circuit is constituted by a plurality of delay elements, and sequentially converts the input pixel data into drive pulses for driving the exposure scanning apparatus. The input unit inputs the pixel data to one of the delay elements of the delay circuit based on the number of delay stages corresponding to the density information of the pixels included in the pixel data. The correction unit reduces the delay amount of the delay circuit in a state where the voltage in the power supply wiring connected to the delay circuit is decreased by a predetermined amount when the light beam emitted from the exposure scanning apparatus is outside the scanning region. Detecting and correcting the number of delay stages based on the delay amount.

  An image forming apparatus according to another aspect of the present invention includes the image processing apparatus.

  According to another aspect of the present invention, there is provided a driving pulse generation method in which the pixel data is input to any one of a plurality of delay elements included in a delay circuit based on the number of delay stages corresponding to the density information of the pixels included in the pixel data. A drive pulse for driving the exposure scanning apparatus is generated. This drive pulse generation method includes a first step and a second step. In the first step, the delay amount of the delay circuit is reduced in a state where the voltage in the power supply wiring connected to the delay circuit is reduced by a predetermined amount when the light beam emitted from the exposure scanning device is outside the scanning region. Is detected. In the second step, the delay element to which the pixel data is input is changed by correcting the number of delay stages based on the delay amount detected in the first step.

  According to the present invention, it is possible to generate and output a stable drive pulse without affecting the fluctuation of the operation rate of image processing.

1 is a diagram illustrating a configuration of an image forming apparatus according to a first embodiment of the present invention. FIG. 2 is a top perspective view of a laser exposure apparatus provided in the image forming apparatus shown in FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a control unit included in the image forming apparatus illustrated in FIG. 1. It is a logic circuit diagram which shows the delay chain circuit of the control part shown in FIG. 4 is a timing chart of an image processing operation rate and a delay amount in the control unit shown in FIG. 3. It is a block diagram which shows the structure of the control part with which the image forming apparatus which concerns on 2nd Embodiment of this invention is provided. 8 is a timing chart of an image processing operation rate and a delay amount in the control unit shown in FIG. 7.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings for understanding of the present invention. In addition, the following embodiment is an example which actualized this invention, Comprising: The thing of the character which limits the technical scope of this invention is not.

[First Embodiment]
First, the configuration of the image forming apparatus 10 according to the first embodiment of the present invention will be described with reference to FIG.

[Image forming apparatus 10]
FIG. 1 is a schematic diagram showing a configuration of an image forming apparatus 10 (an example of the image forming apparatus of the present invention) according to an embodiment of the present invention. As shown in FIG. 1, the image forming apparatus 10 forms an image on a print sheet based on read image data of a document or image data input from the outside. The image forming apparatus 10 includes a scanner 12 at the top and an electrophotographic image forming unit 14 at the bottom. The specific example of the image forming apparatus 10 according to the embodiment of the present invention has a function of performing image processing on input image data. For example, a printer, a copier, a facsimile, or each of these functions is provided. It is a multifunction machine equipped.

  The image forming unit 14 forms an image on a print sheet based on image data read by the scanner 12 or print data (print job) input from the outside. The image forming unit 14 mainly includes an operation display unit 17, a paper feed tray 16, a transport roller 19, a laser exposure device 11 (an example of an exposure scanning device of the present invention), a transfer device 15, and a fixing device 18. And a control unit 5 for controlling these operations. These components are arranged inside a casing 20 that constitutes a housing of the image forming unit 14. A plurality of printing sheets are held in the sheet feeding tray 16. The laser exposure device 11 exposes the photosensitive member 13 included in the transfer device 15 by irradiating a laser beam. The transfer device 15 transfers the toner image onto the printing paper fed from the paper feed tray 16. The fixing device 18 fixes the toner image transferred to the printing paper on the printing paper. Between the upper part of the casing 20 and the scanner 12, a paper discharge space 21 that is open at the front is formed. A paper discharge tray 23 is provided on the lower surface of the paper discharge space 21. The printing paper fed from the paper feed tray 16 is conveyed by the conveyance roller 19 along the conveyance path 20A provided in the casing 20, and the toner image is transferred to the printing paper by the transfer device 15 in the conveyance process. The The toner image transferred to the printing paper is fixed to the printing paper by being heated and melted when passing through the fixing device 18. The printing paper that has passed through the fixing device 18 is discharged to the paper discharge space 21 and held on the paper discharge tray 23.

  As shown in FIG. 2, the laser exposure apparatus 11 includes a housing 25, a semiconductor laser light source 26, a polygon mirror 27, an fθ lens 28, a beam detector 29, a condenser lens 30, and a total reflection mirror 31. And a slit (injection port) 32. The semiconductor laser light source 26 emits a laser beam. The polygon mirror 27 rotates at high speed, reflects the laser beam, and scans in the main scanning direction. The beam detector 29 detects the presence or absence of a laser beam. The condenser lens 30 converts the laser beam into parallel light together with the fθ lens 15. The total reflection mirror 31 changes the optical path of the laser beam that has passed through the condenser lens 17 to a right angle. The slit 32 is formed in the housing 12 and is an exit port that guides the optical path of the laser beam from the total reflection mirror 19 to the irradiation surface of the scanned medium such as the photosensitive member 13.

  In the laser exposure apparatus 11, the polygon mirror 27 rotates at high speed clockwise (in the direction of the arrow in FIG. 2) when viewed from above. Therefore, the laser beam emitted from the semiconductor laser light source 26 is reflected in the direction of the fθ lens 28 by the rotating polygon mirror 27. The laser beam that has passed through the fθ lens 28 then performs main scanning for each line while moving from the right end to the left end of the total reflection mirror 31 in the drawing. As a result, the laser beam reflected by the total reflection mirror 31 is scanned in the same direction as the axial direction of the photosensitive member 13 to expose the photosensitive member 13.

  Further, the side surface of the polygon mirror 27 is constituted by a reflecting surface that forms a polygon (in FIG. 2, a hexagon as an example). Therefore, as the polygon mirror 27 rotates in the clockwise direction, the laser beam is irradiated not only in the scanning area irradiated on the total reflection mirror 31 but also outside the scanning area not irradiated on the total reflection mirror 31. At this time, if the beam detector 29 provided outside the scanning region is irradiated with the laser beam before the main scanning of the photosensitive member 13 is performed, the laser beam is detected by the beam detector 29. The beam detector 29 generates a beam detector signal (also referred to as a BD signal or a main scanning synchronization signal) for taking a scanning start timing for each line when irradiated with a laser beam. This BD signal is used to determine the scanning start timing at which the laser exposure device 11 actually starts scanning the photosensitive member 13 with a laser beam. The BD signal is sent to the control unit 5.

  An image forming apparatus 10 shown in FIG. 1 is connected to an information processing apparatus (not shown), and print data (print job) including image data is transmitted from the information processing apparatus. In this case, the control unit 5 performs a process of expanding the image data into a plurality of pixel data for each pixel in the image processing unit 52 described later. Such pixel data is input from the image processing unit 52 to the LUT unit 53 described later.

  The control unit 5 is a computer having control devices such as a CPU, a ROM, a RAM, and an EEPROM. The CPU is a processor that executes various arithmetic processes. The ROM is a non-volatile storage unit in which information such as a control program for causing the CPU to execute various processes is stored in advance. The RAM is volatile storage means, and the EEPROM is nonvolatile storage means. The RAM and the EEPROM are used as a temporary storage memory (working area) for various processes executed by the CPU. The ROM stores dummy data to be described later.

  Then, the control unit 5 performs overall control of the image forming apparatus 10 by executing various control programs stored in advance in the ROM using the CPU. The control unit 5 may be configured by an electronic circuit such as an integrated circuit (ASIC, DSP), and the image forming unit 14 and the like separately from the main control unit that controls the image forming apparatus 10 in an integrated manner. An engine control unit for controlling may be provided separately.

  In the present embodiment, the control unit 5 generates, for each pixel data, a driving pulse having a width corresponding to the gradation (density information) for each pixel included in each pixel data constituting the input image data. Then, the control unit 5 sequentially sends the generated drive pulses to the laser exposure apparatus 11 as an image signal (drive pulse) for driving the semiconductor laser light source 26 shown in FIG. Upon receiving the drive pulse, the laser exposure device 11 modulates (turns on) the semiconductor laser light source 26 for a time corresponding to the pulse width of the drive pulse, thereby exposing the electrostatic latent image of one pixel (dot). An image is formed on the photoreceptor 13. Note that the image signal actually sent to the laser exposure apparatus 11 is a pulse wave signal in which a plurality of the driving pulses corresponding to each pixel are continuous.

  In order to generate the drive pulse, as shown in FIG. 3, the control unit 5 includes an input switching unit 51, an image processing unit 52, an LUT unit 53, an edge conversion unit 54, a pulse generation unit 56, and a correction value detection unit. 57 and the like. In the present embodiment, these are described as being configured by an electronic circuit such as an integrated circuit (ASIC, DSP). However, the processing of each unit may be executed by the CPU based on a control program. . Hereinafter, each part with which the control part 5 is provided is explained in full detail.

  The input switching unit 51 selects either image data input from the outside or the dummy data stored in the ROM and inputs the selected image data to the image processing unit 52. Specifically, the input switching unit 51 reads the dummy data from the ROM and inputs it to the image processing unit 52 only when a BD signal is input from the beam detector 29. When the BD signal is not input, the image data input to the input switching unit 51 is preferentially selected and input to the image processing unit 52. Here, the dummy data is data for causing the image processing unit 52 to execute a processing load equivalent to the image processing (development processing or the like) for the image data executed by the image processing unit 52. This dummy data is obtained by previously obtaining average image data to be executed by the image processing unit 52 by an experiment or the like and storing it in the ROM in advance. Note that the average image data varies depending on the frequency of use of the image forming apparatus 10. Therefore, image data that has been subjected to image processing in the image forming apparatus 10 may be stored, and the average image data may be calculated from the stored image data and used as the dummy data.

  The image processing unit 52 performs processing for expanding the input image data or dummy data into a plurality of pixel data for each pixel. The developed pixel data is input to the next LUT unit 53. Here, in the present embodiment, it is assumed that the maximum exposure time of one pixel on one scanning line corresponds to one period of a so-called dot clock. The basic clock for controlling each part from the LUT unit 53 to the correction value detection unit 57 is 250 MHz, and the dot clock is 50 MHz obtained by dividing the basic clock. That is, the maximum exposure time for one pixel is 20 ns for calculation.

  Each pixel data output from the image processing unit 52 is supplied to an LUT unit (lookup table unit) 53. The LUT unit 53 adjusts the density of each pixel data to a density according to the characteristics of the image forming apparatus 10, particularly the development characteristics at the time of image formation, and the rising edge of the drive pulse according to the density after the adjustment. The falling edge position (pulse width or duty ratio) is converted into a unit of the number of delay stages per dot clock based on the number of delay stages (the number of delay stages) of the delay chain circuit 59 described later. That is, the LUT unit 53 delays the pixel data in the delay chain circuit 59 so that a drive pulse having a pulse width indicating the density is generated by the delay chain circuit 59 based on the density of the pixel data. The number of stages (the number of passing delay elements) is calculated. The number of delay stages (specifically, the number obtained by converting the pulse width of the drive pulse into the number of delay stages per dot clock) is output to the edge converter 54 together with the pixel data.

  The edge conversion unit 54 compares adjacent pixels on one scanning line based on a plurality of input pixel data, and when originally continuous pixels have the same falling and rising edge positions, Edge conversion processing is performed so that the pixels are continuously connected.

  Further, the edge conversion unit 54 detects a correction value (delay chain circuit 59) detected by a correction value detection unit 57 described later before outputting the pixel data after the edge conversion process and the number of delay stages to the next pulse generation unit 56. The delay stage number is corrected on the basis of the delay amount). This correction is executed at timing Tb (see FIG. 5 (A1)) when the BD signal is input to the control unit 5. In other words, when the laser beam emitted from the laser exposure apparatus 11 is outside the scanning region, the edge conversion unit 54 is based on the correction value detected by the correction value detection unit 57 described later, and the pulse generation unit 56. The number of delay stages output to is corrected. For example, when the correction value is larger than the previously detected correction value (the delay amount is large), the delay stage number is shifted in the increasing direction. On the other hand, when the correction value is smaller than the previously detected correction value (the delay amount is small), the delay stage number is shifted in the direction of decreasing. Then, together with the pixel data, the corrected number of delay stages (specifically, the number obtained by converting the pulse width of the drive pulse into the number of delay stages per dot clock) is output to the pulse generator 56. The edge conversion unit 54 that performs such correction is an example of the correction unit of the present invention. The correction operation in the edge converter 54 will be described later. Note that the above-described correction does not necessarily have to be performed by the edge conversion unit 54, as long as the number of delay stages is corrected before being input to the delay chain circuit 59 of the pulse generation unit 56.

  The pulse generator 56 has a delay chain circuit 59 (an example of the delay circuit of the present invention) shown in FIG. The delay chain circuit 59 is a delay circuit including a plurality of delay elements that sequentially delay input pixel data and convert the pixel data into the drive pulses that drive the laser exposure apparatus 11. The pulse generation unit 56 is an example of an input unit of the present invention, and the pixel data is obtained based on the number of delay stages (the number of delay stages input from the edge conversion unit 54) according to the density of the pixels included in the pixel data. The data is input to one of the delay elements 100_n (n = 0 to 127) included in the delay chain circuit 59.

  The delay chain circuit 59 outputs a drive pulse (image signal) having a pulse width corresponding to the density of the pixel data to the laser drive voltage generator 11A based on the input. The precursor driving pulse is converted into a pulse having voltage capability and current capability for causing the semiconductor laser light source 26 to emit light by the laser driving voltage generation unit 11A, and is supplied to the laser exposure apparatus 11 (see FIGS. 1 and 2). Corresponding exposure is performed. Note that the laser drive voltage generation unit 11A and the laser exposure apparatus 11 are not included in the control unit 5, and are illustrated by broken lines in FIG. Of course, the controller 5 may include the laser drive voltage generator 11A.

  The correction value detector 57 detects a correction value for correcting the number of delay stages in the edge converter 54 every time the BD signal is supplied to the controller 5. The BD signal supplied to the control unit 5 is input to the delay chain circuit 59 as a calibration signal, and operates according to the BD signal under an operation state in which the image processing unit 52 performs image processing on the dummy data. The amount of delay per basic clock period of the delay chain circuit 59 is detected by the correction value detector 57 as a correction value. Here, the correction amount is represented by the number of delay elements (the number of delay stages) that have passed since the BD signal was input to the delay chain circuit 59 until one basic clock cycle elapses. This correction value is fed back to the edge conversion unit 54, and the number of delay stages per dot clock used by the edge conversion unit 54 is corrected (changed) based on the correction value before main scanning by the laser exposure apparatus 11 is started. ) That is, even if the delay speed of the delay chain circuit 59, that is, the number of delay stages per basic clock varies depending on the operating environment, the edge converter 54 corrects the number of delay stages by feeding back the correction value as described above. It is possible to (change).

  As described above, in the present embodiment, the dummy data is input to the image processing unit 52 when the BD signal is input to the control unit 5. Originally, as shown in FIG. 5, at the timing Tb when the BD signal is input (see FIG. 5A1), no image data is input to the image processing unit 52, and the operation rate of the image processing unit 52 is low. (See FIG. 5 (A3)). Therefore, the current consumption in the control unit 5 is small (see FIG. 5 (A4)), and the voltage (power supply voltage) of the power supply wiring for supplying the control voltage to the control unit 5 is rated without causing IR drop (voltage drop). The voltage is maintained (see FIG. 5 (A5)). In this state, if the correction value is detected by the correction value detector 57 at the timing Tb when the BD signal is input, the power supply voltage at the time of detection is approximately the same as the rated voltage (reference voltage). Voltage), and a correction value at this reference voltage is obtained. However, when an image is actually formed, the delay stage number is corrected when the image processing unit 52 is processing image data and the operation rate of the image processing unit 52 is high. Therefore, the correction value needs to be detected when the operation rate of the image processing unit 52 is high. The reason is that if the operation rate of the image processing unit 52 is higher than that at the time of detecting the correction value, the IR drop (voltage drop on the power supply wiring) of the power supply wiring also increases, and the delay chain circuit 59 This is because the delay amount (correction value) also increases (see FIG. 5 (A6)), and thus the number of delay stages cannot be accurately corrected.

  On the other hand, in the present embodiment, the dummy data is input at the timing Tb when the BD signal is input. Therefore, the image processing unit 52 operates to develop the dummy data, and the operation rate thereof is the same as that in the case where normal image processing is performed, as indicated by the dashed box in FIG. 5 (A7). It becomes the operation rate of. Thereby, at the timing Tb at which the correction value is detected by the correction value detection unit 57, the current consumption and the power supply voltage in the control unit 5 are both during the period Tc during which the image processing unit 52 performs normal image processing. This is equivalent to the correction value when detected (see FIGS. 5A8 to A10). As a result, by using the correction value detected by the correction value detection unit 57 in this way, the edge conversion unit 54 adjusts the number of delay stages according to the fluctuation of the operating environment (particularly, the operation rate of the image processing unit 52). It becomes possible to correct well.

  As described above, in the edge converter 54, the correction value per basic clock is fed back to the edge converter 54. Since the edge converter 54 processes in units of dot clocks, the number of delay stages per basic clock is set. Then, a process of replacing with the number of delay stages per dot clock is performed. For example, in this embodiment, as shown in FIG. 4, the total number of delay stages of the delay chain circuit 59 is 128, and the delay time when there is no change in the operating environment is, for example, 0.1 ns per stage. I use it. Therefore, the number of delay stages per basic clock generated at 250 MHz is 40. As described above, since the frequency of the dot clock is 50 MHz, the number of delay stages per dot clock is 200. When the full exposure is performed for one dot clock, the maximum density is reached. Therefore, the maximum density is 200 when the number of delay stages is replaced. Further, the minimum density is 0 when replaced with the delay stage number unit.

  Next, the delay chain circuit 59 will be described with reference to FIG. FIG. 4 is a logic circuit diagram of the delay chain circuit 59. In the upper part of FIG. 4, 128 D-type flip-flops (hereinafter referred to as flip-flops) 100_0 to 100_127 are connected as illustrated. Let a specific flip-flop be 100_n. Pixel data and a basic clock are input to the flip-flops 100_0 to 100_127 from terminals illustrated in the drawing. Further, when a signal is input to a clear terminal (not shown), the flip-flops 100_0 to 100_127 are cleared. The flip lip 100_127 side is referred to as upstream, and the flip lip 100_0 side is referred to as downstream.

  In the middle stage of FIG. 4, 128 EX-NOR circuits 200_0 to 200_127 are connected as shown. A specific EX-NOR circuit is set to 200_n. Each EX-NOR circuit is an example of the delay element of the present invention. The EX-NOR circuit 200_n has one input terminal connected to the output terminal of the flip-flop 100_n, and the other input terminal connected to the upstream (right adjacent to FIG. 4) output terminal of the EX-NOR circuit 200_n + 1. Has been. The EX-NOR circuit 200_127 side is referred to as upstream, and the EX-NOR circuit 200_0 side is referred to as downstream.

  In the lower part of FIG. 4, 128 D-type flip-flops (hereinafter referred to as flip-flops) 300_0 to 300_127 are connected as illustrated. A specific flip-flop is assumed to be 300_n. Data and a basic clock are input to the flip-flops 300_0 to 300_127 from terminals shown in the drawing, respectively. Further, when a signal is input to a clear terminal (not shown), the flip-flops 300_0 to 300_127 are cleared. The flip lip 300_127 side is referred to as upstream, and the flip lip 300_0 side is referred to as downstream.

  An input buffer 202 is provided on the upstream side of the EX-NOR circuit, and an output terminal thereof is connected to the other input terminal of the EX-NOR circuit 200_127. The BD signal is input to the input buffer 202. An output buffer 201 is provided on the downstream side of the EX-NOR circuit, and its input terminal is connected to the output terminal of the EX-NOR circuit 200_0. Further, from the output terminal of the output buffer 201, when scanning is performed based on pixel data, a driving pulse (image signal) for causing the semiconductor laser light source 26 to emit light is output to the laser driving voltage generator 11A. Is done.

  The 128 flip-flops 100_0 to 100_127 receive the pixel data from the pulse generation unit 56, pass the pixel data to the EX-NOR circuits 200_0 to 200_127, generate a predetermined delay, and output the drive pulse from the output buffer 201. . The 128 flip-flops 300_0 to 300_127 read and output a state in which the BD signal input to the input buffer 202 is delayed and propagated from the upstream to the downstream in the EX-NOR circuits 200_0 to 200_127. The output result is supplied to the edge converter 54 and used for correcting (changing) the number of delay stages.

  The operation of the delay chain circuit 59 when the BD signal is input to the input buffer 202 will be described. First, a clear signal is given to a clear terminal (not shown) of the flip-flops 300_0 to 300_127 to be cleared. In this state, when the BD signal as a calibration signal is input to the input buffer 202, the BD signal is input to the most upstream EX-NOR circuit 200_127. Thereafter, the BD signal propagates through the EX-NOR circuit 200_n in a delayed manner toward the downstream. Therefore, the correction value detector 57 detects the output of the flip-flop 300_n (H level output) every time the basic clock input to the flip-flop 300_n is received in response to the output of the EX-NOR circuit 200_n that changes every moment. Is done. At this time, the output from the rising edge of the basic clock to the rising edge of the next basic clock is counted by the correction value detector 57. In the present embodiment, as described above, the number of delay stages per basic clock when there is no change in the operating environment is 40. However, since the correction value detection unit 57 detects and counts the output when the dummy data is image-processed by the image processing unit 52, the basic delay stage number of 40 to several stages is affected by the influence of IR drop. Many outputs are counted. Of course, even when the operating environment has changed since the correction value was detected, the correction value (count value) detected next also varies. This count value is fed back to the edge converter 54 as a correction value. When the correction value is detected, all the flip-flops 100_0 to 100_127 are cleared and the EX-NOR circuits 200_0 to 200_127 are cleared before the image signal is output from the output buffer 201. Steps 300_0 to 300_127 are also cleared.

  In the image forming apparatus 10 of the present embodiment described above, the control unit 5 determines a delay element for inputting pixel data by the following method (drive pulse generation method). That is, every time the BD signal is input, the control unit 5 inputs dummy data to the image processing unit 52 via the input switching unit 51 at a timing Tb before the start of main scanning. For this reason, even when the laser beam is outside the scanning region, the image processing unit 52 performs image processing on the dummy data at the timing Tb. Therefore, the operation rate at the timing Tb temporarily increases. The power supply voltage causes an IR drop by a predetermined amount, and the delay amount in the delay chain circuit 59 varies under the influence of the IR drop. That is, the power supply voltage decreases, the current consumption increases, and the delay speed in the delay chain circuit 59 increases. In this state, the control unit 5 causes the delay chain circuit 59 to input the BD signal as a calibration signal, and detects the delay amount per basic clock in the delay chain circuit 59 at that time as a correction value (first step). ). Thereafter, the detected correction value is fed back to the edge converter 54. Based on the correction value fed back in this way, the edge conversion unit 54 of the control unit 5 corrects the number of delay stages for determining the pulse width of the drive pulse, and thereby the pixel determined before the correction. The data input position is changed to a delay element corresponding to the corrected delay stage number (second step). That is, the control unit 5 inputs a pixel signal to the delay element corresponding to the corrected delay stage number, and causes the delay chain circuit 59 to generate the drive pulse.

  As a result, the number of delay stages approximated to the number of delay stages that could have been detected if the correction value was detected while the image processing unit 52 performed image processing on the image data is obtained as the correction value. Therefore, the number of delay stages can be corrected without being affected by the operation rate of the image processing unit 52. As a result, a stable drive pulse can be generated and output to the laser drive voltage generator 11A, and a stable high quality image can be formed without being affected by the fluctuation of the operation rate.

  In the above-described embodiment, the example in which the correction value is detected at the timing Tb when the BD signal is input to the control unit 5 has been described. However, the present invention is not limited to this. The correction value may be detected at a timing before the main scanning of the photosensitive member 13 by the laser beam is performed. Moreover, although the example which uses the said BD signal as a calibration signal was demonstrated, of course, you may use signals other than a BD signal for a calibration signal. Further, the delay chain circuit 59 is exemplified as having a total number of delay stages of 128, but the total number of delay stages is not limited to this, and the present invention can be applied to any delay chain circuit having a plurality of delay stages.

  In the above-described embodiment, the dummy data is input to the image processing unit 52 to forcibly increase the operation rate of the image processing unit 52. However, the dummy data is not used and the timing Tb is used. Only the voltage of the power supply wiring supplied to the image processing unit 52 and the delay chain circuit 59 in the control unit 5 may be decreased by a predetermined amount. For example, a circuit configuration is conceivable in which a switching element or the like operates on the condition that the BD signal is input, and the power supply voltage is reduced by a predetermined amount by a voltage dividing circuit or a voltage down converter.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. In addition, about the structure similar to the above-mentioned 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted. As shown in FIG. 6, in addition to the image processing unit 52 and the like, the control unit 5A of the image forming apparatus 10 according to the second embodiment includes a reverse phase conversion unit 60 and a dummy circuit 61 (a dummy processing unit of the present invention). For example). Note that the input switching unit 51 provided in the first embodiment is not provided.

  The reverse phase conversion unit 60 performs reverse phase conversion on the same image data as the image processing target image data input to the image processing unit 52. In the present embodiment, the image data input to the control unit 5 is input not only to the image processing unit 52 but also to the reverse phase conversion unit 60. The reverse phase image data (reverse phase image data, dummy data) subjected to the reverse phase conversion by the reverse phase conversion unit 60 is output to the dummy circuit 61.

  The dummy circuit 61 can execute at least delay processing by the delay chain circuit 59 and image processing by the image processing unit 52. In the present embodiment, the dummy circuit 61 includes an image processing unit 52A, an LUT unit 53A, an edge conversion unit 54A, and a pulse generation unit having the same configuration as the image processing unit 52, the LUT unit 53, the edge conversion unit 54, and the pulse generation unit 56, respectively. 56A. The control unit 5A causes the dummy circuit 61 to input the reverse phase image data from the reverse phase conversion unit 60, and the reverse phase image in the order of the image processing unit 52A, the LUT unit 53A, the edge conversion unit 54A, and the pulse generation unit 56A. Data is being processed. However, in the pulse generator 56A, only the drive pulse is generated in the delay chain circuit 59A, and this drive pulse is not used.

  With this configuration, in the image forming apparatus 10 according to the second embodiment, as shown in FIG. 7A3, the image processing unit 52 has a high operating rate only during the period Tc. On the other hand, as shown in FIG. 7A11, in the dummy circuit 61, the operation rate is increased only in the period excluding the period Tc. In this case, the operation rate of the entire control unit 5 is a combination of the operation rate of the image processing unit 52 and the dummy circuit 61, and is not limited to the timing Tb at which the correction value is detected. (See FIG. 7 (A12)). As a result, the current consumption and the power supply voltage in the control unit 5A both show substantially the same value, and the correction value detected at the timing Tb is substantially the same as the correction value when detected in another period. Value. By using such a correction value, the edge converter 54 can accurately correct the number of delay stages. As a result, a stable drive pulse can be generated and output to the laser drive voltage generator 11A, and a stable high quality image can be formed without being affected by the operating rate.

  In each of the above-described embodiments, the image forming apparatus 10 including the control units 5 and 5A is illustrated as the image forming apparatus of the present invention. However, the image forming apparatus 10 includes the control units 5 and 5A and applies to input image data. The present invention can also be understood as an image processing apparatus that performs image processing. Further, in the drive pulse generation method applied to the image forming apparatus or the image processing apparatus, a plurality of delay elements provided in the delay chain circuit 59 based on the number of delay stages according to the density information of the pixels included in the pixel data It can also be understood as a driving pulse generation method for generating a driving pulse for driving the beam exposure apparatus 11 by inputting the pixel data to any of the above.

10: Image forming device 5, 5A: Control unit 11: Laser exposure device 29: Beam detector 51: Input switching unit 52, 52A: Image processing unit 53, 53A: LUT unit 54, 54A: Edge conversion unit 56, 56A: Pulse Generation unit 57: correction value detection unit 59, 59A: delay chain circuit

Claims (6)

A delay circuit comprising a plurality of delay elements that sequentially delay input pixel data and convert the pixel data into drive pulses for driving the exposure scanning device;
An input unit that inputs the pixel data to one of the delay elements of the delay circuit based on the number of delay stages according to the density information of the pixel included in the pixel data;
When the light beam emitted from the exposure scanning device is outside the scanning region, the delay amount of the delay circuit is detected in a state where the voltage in the power supply wiring connected to the delay circuit is reduced by a predetermined amount, and the delay is detected. A correction unit that corrects the number of delay stages based on a quantity.   The correction unit causes the image processing apparatus to process dummy data indicating a processing burden equivalent to the image processing executed by the image processing apparatus when the light beam emitted from the exposure scanning apparatus is outside the scanning region. The image processing apparatus according to claim 1, wherein the voltage in the power supply wiring is dropped by the predetermined amount.   The image processing apparatus according to claim 1, wherein the correction unit detects the delay amount when a scanning synchronization signal for determining a scanning start timing by the exposure scanning apparatus is input. A dummy processing unit capable of executing at least delay processing by the delay circuit and image processing by the image processing apparatus;
The said correction | amendment part makes the said dummy process part perform the dummy data which carried out the reverse phase conversion of the said pixel data at the time of image processing the pixel data of the image processing target input into the said image processing apparatus. Image processing device.   An image forming apparatus comprising the image processing apparatus according to claim 1. Drive pulse generation for generating a drive pulse for driving the exposure scanning apparatus by inputting the pixel data to any one of a plurality of delay elements included in the delay circuit based on the number of delay stages corresponding to the density information of the pixel included in the pixel data A method,
A first step of detecting the delay amount of the delay circuit in a state where the voltage in the power supply wiring connected to the delay circuit is reduced by a predetermined amount when the beam light emitted from the exposure scanning device is outside the scanning region. When,
And a second step of changing the delay element to which the pixel data is input by correcting the number of delay stages based on the delay amount detected in the first step.

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