JP2005142391A - Optical semiconductor device and its producing process - Google Patents

Optical semiconductor device and its producing process Download PDF

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JP2005142391A
JP2005142391A JP2003377943A JP2003377943A JP2005142391A JP 2005142391 A JP2005142391 A JP 2005142391A JP 2003377943 A JP2003377943 A JP 2003377943A JP 2003377943 A JP2003377943 A JP 2003377943A JP 2005142391 A JP2005142391 A JP 2005142391A
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optical semiconductor
dicing
substrate
semiconductor device
degrees
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Takashi Tomarino
貴司 泊野
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical semiconductor device and its producing process in which production yield can be enhanced by suppressing cracking of a substrate in the production process without deteriorating the characteristics. <P>SOLUTION: The optical semiconductor device comprises an optical semiconductor element having an element region on a compound semiconductor substrate wherein an angle of 5-85° is set between the dicing direction of the optical semiconductor element and the orientation of cleavage surface of the compound semiconductor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、化合物半導体基板を用いた光半導体装置とその製造方法に関する。   The present invention relates to an optical semiconductor device using a compound semiconductor substrate and a manufacturing method thereof.

一般に、LED等の光半導体装置に用いられる光半導体素子(チップ)は、化合物半導体基板上に素子領域を形成し、これをダイシングすることにより形成される(例えば特許文献1参照)。   In general, an optical semiconductor element (chip) used in an optical semiconductor device such as an LED is formed by forming an element region on a compound semiconductor substrate and dicing it (see, for example, Patent Document 1).

このとき、通常化合物半導体基板の結晶方位に沿うようにダイシングされる。例えば、図8に示すように、GaP基板11(100)表面に素子領域を形成した後、(100)オリエンテーションフラット16と平行(0度)/90度となるように、格子状にパターニングされ(ダイシングパターン17)、素子領域側より1stダイシング(ハーフダイシング)される。そして、メサエッチングを経て、基板側より2ndダイシングされ、メサエッチング後、各チップに分離される。
特開2002−231994号公報
At this time, dicing is usually performed along the crystal orientation of the compound semiconductor substrate. For example, as shown in FIG. 8, after an element region is formed on the surface of the GaP substrate 11 (100), it is patterned in a lattice shape so as to be parallel (0 degree) / 90 degrees with the (100) orientation flat 16 ( The dicing pattern 17) is 1st dicing (half dicing) from the element region side. Then, after mesa etching, 2nd dicing is performed from the substrate side, and after mesa etching, the chips are separated.
Japanese Patent Laid-Open No. 2002-231994

しかしながら、1stダイシング後において、基板の分離がなされていないにもかかわらず、基板が割れてしまうという問題が発生した。このような問題の原因としては、各工程及び工程間におけるハンドリングに起因するものが考えられるものの、特に量産時においてこれを抑制することは困難であった。   However, after the first dicing, there is a problem that the substrate is broken even though the substrate is not separated. Although the cause of such a problem can be attributed to each process and handling between processes, it has been difficult to suppress this particularly during mass production.

そこで、本発明は、従来の問題を取り除き、特性を劣化させることなく、製造工程における基板の割れを抑制し、歩留りを向上させることが可能な光半導体装置及びその製造方法を提供することを目的とするものである。   Therefore, the present invention aims to provide an optical semiconductor device and a method of manufacturing the same that can eliminate the conventional problems and suppress the cracking of the substrate in the manufacturing process and improve the yield without deteriorating the characteristics. It is what.

本発明の一態様によれば、化合物半導体基板上に素子領域が形成された光半導体素子を備え、前記光半導体素子のダイシング方向と、前記化合物半導体の割れ結界面方位との角度が、5〜85度であることを特徴とする光半導体装置が提供される。   According to one aspect of the present invention, an optical semiconductor element having an element region formed on a compound semiconductor substrate is provided, and an angle between a dicing direction of the optical semiconductor element and a fracture interface direction of the compound semiconductor is 5 to 5 An optical semiconductor device characterized in that the angle is 85 degrees is provided.

また、本発明の一態様によれば、化合物半導体基板上に素子領域を形成する工程と、前記化合物半導体の割れ結界面との角度が5〜85度となるように、所定のダイシングパターンを形成する工程と、前記ダイシングパターンにより前記化合物半導体基板をダイシングして、光半導体素子を形成する工程を備えることを特徴とする光半導体装置の製造方法が提供される。   According to another aspect of the present invention, the predetermined dicing pattern is formed so that the angle between the step of forming the element region on the compound semiconductor substrate and the fracture interface of the compound semiconductor is 5 to 85 degrees. And a method of forming an optical semiconductor element by dicing the compound semiconductor substrate with the dicing pattern.

本発明の一実施態様によれば、特性を劣化させることなく、製造工程における基板の割れを抑制し、歩留りを向上させることが可能な光半導体装置及びその製造方法を提供することができる。   According to one embodiment of the present invention, it is possible to provide an optical semiconductor device and a method for manufacturing the same that can suppress the cracking of the substrate in the manufacturing process and improve the yield without degrading the characteristics.

以下本発明の実施形態について、図を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

(実施形態1)
図1に、本実施形態の光半導体装置における光半導体素子の断面図を、図2に、上面図を示す。図に示すように、GaP基板1上に素子領域2が形成され、さらに、各面にn側、p側電極部3、4が形成されている。GaP基板の割れ結界面(へき界面)である(100)面((010)面)5は、素子の対角線方向となっている。
(Embodiment 1)
FIG. 1 is a cross-sectional view of an optical semiconductor element in the optical semiconductor device of this embodiment, and FIG. 2 is a top view. As shown in the figure, an element region 2 is formed on a GaP substrate 1, and n-side and p-side electrode portions 3 and 4 are formed on each surface. A (100) plane ((010) plane) 5 which is a fracture interface (peel interface) of the GaP substrate is in the diagonal direction of the element.

このような光半導体素子は以下のように形成される。図3に示すように、(100)オリエンテーションフラット6の形成されたGaP基板1の(100)面に、素子領域を形成し、通常のPEP(Photo Etching Process)により、一軸がオリエンテーションフラットと45度となるように、格子状にダイシングパターン7を形成する。   Such an optical semiconductor element is formed as follows. As shown in FIG. 3, an element region is formed on the (100) surface of the GaP substrate 1 on which the (100) orientation flat 6 is formed, and one axis is 45 degrees with the orientation flat by a normal PEP (Photo Etching Process). Then, the dicing pattern 7 is formed in a lattice shape.

次いで、図4に示すように、蒸着、リフトプロセスによりp側、n側に所定パターンの電極部3、4を形成した後、素子領域2の形成面側より、GaP基板1までダイシングブレード8による1stダイシング及びメサエッチングを行う。このとき、従来のオリエンテーションフラットと平行(0度)/90度となるパターンのものと比較して、エッチング形状、エッチングレートにおける有意差は認められなかった。   Next, as shown in FIG. 4, electrode portions 3 and 4 having a predetermined pattern are formed on the p side and the n side by vapor deposition and lift processes, and then the dicing blade 8 extends from the formation surface side of the element region 2 to the GaP substrate 1. 1st dicing and mesa etching are performed. At this time, a significant difference in the etching shape and the etching rate was not recognized as compared with the pattern having a parallel (0 degree) / 90 degree pattern with the conventional orientation flat.

そして、さらに図5に示すように、基板側より2ndダイシング、メサエッチングを行い、各光半導体素子を分離する。2ndダイシングの際には、従来の割れ結界面でダイシングしたものと比較すると、断面が凹凸を有しているものの、メサエッチングにより従来と同様にフラットとなる。   Further, as shown in FIG. 5, 2nd dicing and mesa etching are performed from the substrate side to separate the respective optical semiconductor elements. At the time of 2nd dicing, compared with what was diced by the conventional cracking interface, although a cross section has an unevenness | corrugation, it becomes flat similarly to the past by mesa etching.

このようにして、GaP基板のオリエンテーションフラットと45度でダイシングされた光半導体素子が形成され、マウント・ボンディング等工程を経て光半導体装置が構成される。   In this way, an optical semiconductor element diced at 45 degrees with the orientation flat of the GaP substrate is formed, and an optical semiconductor device is configured through processes such as mounting and bonding.

このようにして形成された光半導体装置を通電させ、光出力が70%となる時間を測定してライフ評価を行ったところ、従来の光半導体素子に対する有意差は認められず、定電流の印加による出力電圧(DC特性)においても有意差は認められなかった。また、光学的特性においても有意差は認められなかった。   When the life evaluation was performed by energizing the optical semiconductor device thus formed and measuring the time when the optical output was 70%, no significant difference was observed with respect to the conventional optical semiconductor element, and the application of a constant current was confirmed. No significant difference was found in the output voltage (DC characteristics) due to. Also, no significant difference was observed in the optical characteristics.

一方、1stダイシング後の強度評価(簡易抗折強度評価)を行った結果を表1に示す。尚、評価は以下に示すフローで行われる。   On the other hand, Table 1 shows the results of strength evaluation (simple flexural strength evaluation) after 1st dicing. Evaluation is performed according to the following flow.

1)ダイシングパターンの形成された基板1(約230μm厚)を、検査テーブル端面に基板中心部が位置するように固定する。このときテーブル端面8は、図6に示すようにオリエンテーションフラット6と平行(A) 又は45度(B)となる。 1) The substrate 1 (about 230 μm thick) on which the dicing pattern is formed is fixed so that the center portion of the substrate is positioned on the end surface of the inspection table. At this time, the table end surface 8 is parallel (A) or 45 degrees (B) with the orientation flat 6 as shown in FIG.

2)ゲージで基板の周辺より2−3mmに加重をかける。 2) Apply a weight of 2-3mm from the periphery of the substrate with a gauge.

3)徐々に加重をかけ、破損した時点のテンション(ゲージの値)を読み取る

Figure 2005142391
尚、ここで、切り込み量とは、基板表面より1stダイシングにより切り込まれた深さを示す。 3) Apply weight gradually and read the tension (gauge value) at the time of breakage
Figure 2005142391
Here, the cut amount indicates the depth cut by the first dicing from the substrate surface.

このとき、割れ方向性はダイシングパターンラインへの相関が強く、従来の90度方向でのパターニングでの90度方向のストレスに対しては、極端に弱くなっていることがわかる。一方、ダイシングパターンを45度に形成したものについては、従来パターンと比して、割れ強度が強いことがわかる。   At this time, the crack directionality has a strong correlation with the dicing pattern line, and it is found that the crack directionality is extremely weak against the stress in the 90 degree direction in the conventional patterning in the 90 degree direction. On the other hand, it can be seen that the dicing pattern formed at 45 degrees has higher cracking strength than the conventional pattern.

このようにして形成される光半導体装置において、割れ強度が改善されることにより、1stダイシング後の割れロスが削減され、歩留りを向上させることが可能となる。   In the optical semiconductor device thus formed, the crack strength is improved, so that the crack loss after the first dicing is reduced, and the yield can be improved.

(実施形態2)
本実施形態においては、実施形態1とほぼ同様であるが、ダイシングパターン7’の形成方向が45度方向でなく、図7に示すように、一軸がオリエンテーションフラット6と60度の角度を有している点で異なっている。
(Embodiment 2)
In the present embodiment, although it is almost the same as in the first embodiment, the dicing pattern 7 ′ is not formed in the direction of 45 degrees, and one axis has an angle of 60 degrees with the orientation flat 6 as shown in FIG. Is different in that.

本実施形態においても、実施形態1と同様に光半導体装置が形成され、同様に、1stダイシング後の割れロスが削減され、歩留りを向上させることが可能となる。   Also in the present embodiment, an optical semiconductor device is formed as in the first embodiment, and similarly, the crack loss after the 1st dicing is reduced, and the yield can be improved.

これら実施形態において、化合物半導体基板としてGaP基板を用いたが、これに限定されるものではなく、GaAs基板、LiAlO基板、サファイア基板等の化合物半導体基板を用いることが可能である。また、GaP基板においては、割れ結界面(へき界面)は(100)面であるが、面方位はこれら結晶系により異なり、夫々割れ結界面と所定の角度を有していればよい。 In these embodiments, a GaP substrate is used as the compound semiconductor substrate, but the present invention is not limited to this, and a compound semiconductor substrate such as a GaAs substrate, a LiAlO 2 substrate, or a sapphire substrate can be used. Further, in the GaP substrate, the cracking interface (peeling interface) is the (100) plane, but the plane orientation differs depending on these crystal systems, and each has only to have a predetermined angle with the cracking interface.

この場合、5〜85度の角度を有していることが必要である。5度未満或いは85度を越えると、割れ結界面との角度が小さいため、1stダイシング後に応力が加わると、割れ結界面でへき開してしまう。より好ましくは、30〜60度である。   In this case, it is necessary to have an angle of 5 to 85 degrees. If it is less than 5 degrees or exceeds 85 degrees, the angle with the cracking interface is small, so if stress is applied after 1st dicing, it will cleave at the cracking interface. More preferably, it is 30 to 60 degrees.

これら実施形態において形成される光半導体素子においては、その形状自体は従来のものと差異がないが、破壊試験(例えば、中心部に集中的に応力を加えて破壊させる)により形成される破断面が、素子のダイシング方向と所定の角度(5〜85度)に形成されることにより差異を見出すことが可能である。
尚、本発明は、上述した実施形態に限定されるものではない。その他要旨を逸脱しない範囲で種々変形して実施することができる。
In the optical semiconductor element formed in these embodiments, the shape itself is not different from the conventional one, but the fracture surface is formed by a destructive test (for example, intensive stress is applied to the central portion to cause destruction). However, it is possible to find a difference by forming it at a predetermined angle (5 to 85 degrees) with respect to the dicing direction of the element.
In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

本発明の一態様における光半導体素子の断面図。1 is a cross-sectional view of an optical semiconductor element in one embodiment of the present invention. 本発明の一態様における光半導体素子の上面図。1 is a top view of an optical semiconductor element in one embodiment of the present invention. 本発明の一態様における半導体素子のダイシングパターンを示す図。FIG. 6 illustrates a dicing pattern of a semiconductor element according to one embodiment of the present invention. 本発明の一態様における半導体素子の製造工程を示す図。4A and 4B illustrate a manufacturing process of a semiconductor element in one embodiment of the present invention. 本発明の一態様における半導体素子の製造工程を示す図。4A and 4B illustrate a manufacturing process of a semiconductor element in one embodiment of the present invention. 本発明の一態様における半導体素子の評価方法を示す図。10A and 10B illustrate a method for evaluating a semiconductor element according to one embodiment of the present invention. 本発明の一態様における半導体素子のダイシングパターンを示す図。FIG. 6 illustrates a dicing pattern of a semiconductor element according to one embodiment of the present invention. 従来の半導体素子のダイシングパターンを示す図。The figure which shows the dicing pattern of the conventional semiconductor element.

符号の説明Explanation of symbols

1、11 GaP基板
2 素子領域
3 n側電極部
4 p側電極部
5 割れ結界面
6、16 オリエンテーションフラット
7、17 ダイシングパターン
8 検査テーブル端面
DESCRIPTION OF SYMBOLS 1, 11 GaP board | substrate 2 Element area | region 3 N side electrode part 4 P side electrode part 5 Cracking interface 6, 16 Orientation flat 7, 17 Dicing pattern 8 Inspection table end surface

Claims (5)

化合物半導体基板上に素子領域が形成された光半導体素子を備え、
前記光半導体素子のダイシング方向と、前記化合物半導体の割れ結界面方位との角度が、5〜85度であることを特徴とする光半導体装置。
Comprising an optical semiconductor element having an element region formed on a compound semiconductor substrate;
An optical semiconductor device, wherein an angle between a dicing direction of the optical semiconductor element and a cracking interface direction of the compound semiconductor is 5 to 85 degrees.
前記角度が、30〜60度であることを特徴とする請求項1に記載の光半導体装置。   The optical semiconductor device according to claim 1, wherein the angle is 30 to 60 degrees. 前記化合物半導体基板はGaP基板であることを特徴とする請求項1又は2に記載の光半導体装置。   The optical semiconductor device according to claim 1, wherein the compound semiconductor substrate is a GaP substrate. 化合物半導体基板上に素子領域を形成する工程と、
前記化合物半導体の割れ結界面との角度が5〜85度となるように、所定のダイシングパターンを形成する工程と、
前記ダイシングパターンにより前記化合物半導体基板をダイシングして、光半導体素子を形成する工程を備えることを特徴とする光半導体装置の製造方法。
Forming an element region on the compound semiconductor substrate;
Forming a predetermined dicing pattern so that an angle with the cracked interface of the compound semiconductor is 5 to 85 degrees;
A method of manufacturing an optical semiconductor device, comprising: a step of dicing the compound semiconductor substrate with the dicing pattern to form an optical semiconductor element.
前記角度が、30〜60度であることを特徴とする請求項4に記載の光半導体装置の製造方法。   The method of manufacturing an optical semiconductor device according to claim 4, wherein the angle is 30 to 60 degrees.
JP2003377943A 2003-11-07 2003-11-07 Optical semiconductor device and its producing process Pending JP2005142391A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234902A (en) * 2006-03-01 2007-09-13 Toyoda Gosei Co Ltd Light-emitting element, and manufacturing method thereof
JP2007294804A (en) * 2006-04-27 2007-11-08 Matsushita Electric Ind Co Ltd Semiconductor light emitting element and wafer
WO2007126158A1 (en) * 2006-04-27 2007-11-08 Panasonic Corporation Semiconductor light emitting element and wafer
US10014123B2 (en) 2011-12-14 2018-07-03 Intel Corporation Overcoming variance in stacked capacitors
JP2020088093A (en) * 2018-11-21 2020-06-04 三菱電機株式会社 Manufacturing method of semiconductor chip and semiconductor wafer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007234902A (en) * 2006-03-01 2007-09-13 Toyoda Gosei Co Ltd Light-emitting element, and manufacturing method thereof
JP2007294804A (en) * 2006-04-27 2007-11-08 Matsushita Electric Ind Co Ltd Semiconductor light emitting element and wafer
WO2007126158A1 (en) * 2006-04-27 2007-11-08 Panasonic Corporation Semiconductor light emitting element and wafer
US7915714B2 (en) 2006-04-27 2011-03-29 Panasonic Corporation Semiconductor light emitting element and wafer
US10014123B2 (en) 2011-12-14 2018-07-03 Intel Corporation Overcoming variance in stacked capacitors
JP2020088093A (en) * 2018-11-21 2020-06-04 三菱電機株式会社 Manufacturing method of semiconductor chip and semiconductor wafer
JP7209513B2 (en) 2018-11-21 2023-01-20 三菱電機株式会社 Semiconductor chip manufacturing method and semiconductor wafer

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