JP2005142338A - Printed wiring board and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board wherein the number of steps can be reduced and a substrate with high density can be formed at a low cost. <P>SOLUTION: The printed wiring board comprises at least one or more insulating layers, two circuit conductor layers formed on both surfaces of the insulating layer, and a via hole filled with an electroless plating metal to connect the two circuit conductor layers with each other. In this case, at least one circuit conductor layer is partly formed by a sputtering method. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a printed wiring board used for mounting a semiconductor device and the like, and a manufacturing method thereof.

In recent years, with higher integration and higher density of semiconductors, a substrate on which the semiconductor is mounted is required to have finer wiring and higher density. As a wiring board that realizes this requirement, there is a thin film multilayer substrate. As the via structure of the thin film multilayer substrate, there are two types of stacked vias (or filled vias) and staggered vias in which the positions of the upper and lower vias are shifted and connected. As a conventional method for forming a stacked via, as disclosed in Patent Document 1, via posts are formed in advance by photolithography and electroplating, an insulating layer is applied, a power supply layer is sputtered, and then a circuit is formed. There is a way to do it.
JP-A-6-302965

  However, the above two types of via formation methods have the following problems.

  First, when forming a stacked via by a conventional method, it is necessary to form a via post in advance, and a power supply layer for performing electroplating is required, which complicates the process.

  Next, since the staggered via cannot be disposed on the via, it is difficult to increase the density.

  The present invention has been conceived under such circumstances, and is intended to solve the problems described above. An object is to reduce the number of steps and form a high-density substrate at low cost.

  (1) The present invention is an electroless plating metal for connecting at least one insulating layer, two circuit conductor layers provided on both surfaces of the insulating layer, and the two circuit conductor layers. A printed wiring board comprising a filled via hole, wherein a part of at least one circuit conductor layer is formed by sputtering.

    (2) Further, according to the present invention, an insulating layer is provided on the inner layer circuit board, a via hole for interlayer connection is formed in the insulating layer, the inside of the via hole is filled by electroless plating, and the surface of the insulating layer is filled. The method includes a step of forming a power supply layer by sputtering, forming a photoresist layer, forming a circuit conductor by plating only at a portion to be a circuit, and etching away an unnecessary portion of the plating. A method for producing a production plate is provided.

    (3) Further, the present invention provides the method for producing a printed board according to (2), further comprising the step of polishing and smoothing the surface of the insulating layer after filling the holes in the electroless plating. .

    Furthermore, the present invention provides the method for producing a printed board according to (2) or (3), wherein electroless palladium plating is performed as a pretreatment for filling electroless plating in via holes.

According to the invention, a high-density multilayer substrate can be manufactured at low cost.

  An embodiment of the present invention will be described with reference to FIG.

  First, a substrate on which a conductor circuit is formed in advance is prepared. Although it does not specifically limit as the board | substrate 1, For example, an epoxy resin, cyanate ester resin, a polyimide resin etc. can be used. Although it does not specifically limit as the circuit 2, For example, copper and aluminum can be used and it is preferable on electrical characteristics to use copper. The circuit 2 can be manufactured using a known method such as etching a copper foil on the substrate 1.

  Next, the insulating layer 3 is formed on the substrate 1 on which a conductor circuit has been previously formed as shown in FIG. The insulating layer is not particularly limited. For example, a thermosetting resin such as phenol resin, cyanate ester resin, epoxy resin, polyimide resin, bismaleimide-triazine resin, or thermoplastic resin such as fluorine resin or polyphenylene ether resin is used. Can be used. Among these, it is preferable to use a thermosetting resin, and a cyanate ester resin and a polyimide resin are particularly preferable because sputtering is performed later. These resins are applied or laminated on a substrate on which a conductor circuit has been previously formed as shown in FIG. 1 (a) and cured to form an insulating layer. The thickness of the insulating layer is preferably about 10 to 40 μm.

    Next, as shown in FIG. 1B, a via 4 for interlayer connection is formed. The via diameter is preferably about 10 to 100 μm. The via is formed by irradiating the insulating layer with a laser and using a photo-curing insulating resin for the insulating layer, exposing a photomask that masks a portion to be a via hole, and exposing the via hole to a portion to be a via hole And a method of developing and removing the insulating layer.

  The type of laser of the laser processing machine used when opening a via hole by irradiating with a laser is not particularly limited, such as a carbon dioxide gas laser or a UV-YAG laser, but a UV-YAG laser is preferable from the viewpoint of small-diameter drillability. The drilling conditions must be adjusted according to the thickness of the plated copper, the type of adhesive, and the thickness of the adhesive, and are preferably obtained experimentally. The amount of energy is within the range of 0.001 W to 1 W. Therefore, it is necessary to control the laser oscillation power supply so that a large amount of energy is not concentrated at a time by applying a pulsed power supply. The adjustment of the drilling conditions is performed by adjusting the pulse waveform duty ratio for driving the laser oscillation power source to 1/1000 to 1/1 in order to make a hole reaching the inner layer circuit of the inner layer circuit board and to make the hole diameter as small as possible. In the range of 10, it is preferably 1 to 20 shots (pulses). If the waveform duty ratio is less than 1/1000, it takes too much time to make a hole and is not efficient. If it exceeds 1/10, the irradiation energy is too large and the hole diameter becomes 1 mm or more, which is not practical. The number of shots (pulses) should be determined experimentally so that the adhesive in the hole can evaporate to reach the inner layer circuit. If less than one shot, a hole cannot be drilled. Even if the waveform duty ratio of the pulse is near 1/1000, the hole diameter becomes large and is not practical.

In a method in which a photomask masking a portion that becomes a via hole is overlaid and exposed, and the insulating layer in the portion that becomes a via hole is developed and removed, it is necessary to mix a photoinitiator with the insulating layer. As the initiator, various onium salts such as a sulfonium salt and an iodonium salt having BF ₆ , PF ₆ , AsF ₆ , and SbF ₆ as a counter anion can be used.

    Next, as shown in FIG. 1C, the via portion 4 is filled with electroless plating 6. In order to fill a hole by electroless plating, it is preferable to perform substitution palladium plating first. The displacement palladium plating is not particularly limited as long as it can form a palladium 5 film on copper by a substitution reaction of palladium ions in the plating solution. After performing the displacement palladium plating, the inside of the via hole is filled with the electroless plating 6. Use of electroless nickel plating or electroless copper plating or alloy plating of both is desirable for filling the hole. The electroless nickel plating solution or electroless copper plating solution includes a complexing agent of nickel (copper) ions and nickel (copper) ions, a reducing agent of nickel (copper) ions, a pH adjusting agent, and if necessary. It is preferable to use those containing additives such as stabilizers. As a reducing agent used for electroless nickel plating or electroless copper plating, it is preferable to use an electroless plating solution containing any one of hydrazine, hypophosphite, and dimethylamine borane. The plating solution used for electroless nickel plating or electroless plating preferably contains at least 0.1 mmol / l or more of nickel (copper) ions. There is a fear. The plating deposition rate is preferably about 1 to 20 μm / min.

    After the plating is finished, in order to polish and smooth the surface of the insulating layer, it is preferable to perform a surface conditioning treatment on the surface of the interlayer resin insulating layer. In this surface treatment, a surface polishing machine, a scrubbing machine, or a century machine using a cloth roll or brush roll is used to mechanically polish the surface of the interlayer resin insulation layer with a cloth roll, brush roll, or abrasive grains. To do. Polishing is performed at about 0.1 to 5 μm so that the height of the insulating layer and the electroless plating is within ± 3 μm.

  Next, as shown in FIG. 1 (d), after conducting plasma treatment or corona discharge treatment on the surface of the insulating layer, a conductor layer 7 is formed by sputtering. Sputtering methods include a glow discharge method, a plasma method, a beam method, and the like, but are not particularly limited here. The conductor layer formed by sputtering contains at least one metal selected from Au, Pt, Ag, Al, Fe, W, Mo, Sn, Ni, Co, Cr, Ti, Cu, and Ta. A layer is preferred. As for the thickness of a conductor layer, 0.01-3.0 micrometers is preferable. A more preferred thickness is 0.1 to 1 μm. If the thickness of the conductor layer 7 formed on the insulating layer for dry process is less than 0.01 μm, conduction is insufficient and defects are likely to occur in the subsequent electroplating process, and if it exceeds 3.0 μm, the amount of conductor dissolved during etching is reduced. There is a case where the formation of fine wiring is greatly hindered.

  Next, a plating resist 8 is formed on the conductor layer as shown in FIG. The thickness of the plating resist 8 is preferably set to a thickness that is about the same as or thicker than the thickness of the conductor to be subsequently plated. Examples of the resin that can be used for the plating resist include dry films such as HW-425 (Hitachi Chemical Industry Co., Ltd., trade name) and RY-3025 (Hitachi Chemical Industry Co., Ltd., trade name). A plating resist is not formed on the IVH and where the conductor circuit is to be formed.

  Subsequently, a circuit pattern 9 is formed as shown in FIG. The circuit pattern 9 can be formed by electroplating. For the electroplating, copper sulfate electroplating or pyrophosphoric acid electroplating usually used for printed wiring boards can be used. The plating thickness may be used as a circuit conductor, and is preferably in the range of 1 to 100 μm, and more preferably in the range of 5 to 50 μm.

  Next, as shown in FIG. 1 (g), the plating resist is stripped using an alkaline stripping solution, sulfuric acid, or a commercially available resist stripping solution, and the circuit formation is completed by etching away the conductor layer other than the circuit pattern. .

  Hereinafter, the present invention will be described in more detail with reference to examples.

(Example)
A circuit is formed by photolithographic method on one side of MCL-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.), an epoxy copper-clad laminate with a thickness of 0.6 mm, and an inner layer board (substrate 1) consisting of an insulating layer and a conductor circuit 2 After that, GXA-67Y (trade name, manufactured by Hitachi Chemical Co., Ltd.), a prepreg having a thickness of 0.06 mm, was laminated and pressed at 210 ° C. for 80 minutes (FIG. 1A).

  With a carbon dioxide impact laser drilling machine L-500 (trade name, manufactured by Sumitomo Heavy Industries, Ltd.), a via 4 having a diameter of 50 μm is opened, and a mixed aqueous solution of potassium permanganate 65 g / liter and sodium hydroxide 40 g / liter is used. It was immersed for 20 minutes at a liquid temperature of 70 ° C. to remove smear (FIG. 1B).

  As a pretreatment for plating, it is immersed in acidic degreasing solution Z-200 (trade name, manufactured by World Metal Co., Ltd.) for 1 minute at a liquid temperature of 60 ° C., then immersed in sodium persulfate 50 g / L for 1 minute, It was immersed in 10 vol% sulfuric acid for 1 minute at room temperature. It is immersed in Melplate Activator 350 (trade name, manufactured by Meltex Co., Ltd.) at room temperature for 5 minutes, and a palladium catalyst is selectively applied onto copper (conductor circuit 2), and electroless nickel-phosphorus alloy plating is performed. It was immersed in a certain NIPS-100 (manufactured by Hitachi Chemical Co., Ltd., trade name) at 90 ° C. for 2 hours to form a copper post (electroless plating 6), and the resin surface was flattened by cloth polishing (FIG. 1 ( c)).

Conductor layer 7 (chromium layer 0.01 μm, copper layer 0.1 μm) as a power feeding layer for electroplating under the conditions shown in Table 1 using magnetron sputtering apparatus MLH6315D (trade name, manufactured by Nippon Vacuum Technology Co., Ltd.) Was formed (FIG. 1 (d)).

  RY-3025 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a dry film photoresist as the plating resist 8 is laminated on the surface of the conductor layer 7, and ultraviolet rays are passed through a photomask which masks a place where electrolytic copper plating is performed. Was exposed and developed to form a plating resist 8 (FIG. 1E).

Using a copper sulfate bath, electrolytic copper plating was performed for about 20 μm under conditions of a liquid temperature of 25 ° C. and a current density of 1.0 A / dm ² , and a circuit pattern 9 was formed by electrolytic copper plating (FIG. 1 (f)). .

  The dry film was removed with HTO (trade name, manufactured by Nichigo-Morton Co., Ltd.), which is a resist stripping solution, and then the substrate was fabricated by removing the electroless plating layer at the excess portion by etching (FIG. 1 (g) ).

(Test method)
A reliability test was performed using the substrate manufactured by the method of the example. The test was performed using a pattern in which the upper and lower layers were connected in a chain with 400 vias as shown in FIG. In FIG. 2, 20 is a via, 21 is an insulating layer, and 22 is a conductor circuit.

(Solder float test)
In order to evaluate the connection reliability between via layers, a solder float test at 260 ° C. was performed. The rate of change in conduction resistance per via was measured every minute, and the time for the rate of change in conduction resistance to be 10% or more was examined. The results are shown in Table 2.

(Hot oil test)
In order to evaluate the connection reliability between the layers, a hot oil test was conducted. This hot oil test is conducted at 260 ° C., 10 seconds (oil) and 20 ° C., 10 seconds (water) as one cycle, and the conduction resistance change rate per via is measured every 10 cycles, and the conduction resistance change rate is 10%. The number of cycles above was examined. If it was 100 cycles or more, it was determined to be acceptable. The results are also shown in Table 2.

(Thermal cycle test)
A thermal cycle test was conducted to evaluate the connection reliability between the layers. In this thermal cycle test, the conduction resistance change rate per via is measured every 10 cycles, with the gas phase 125 ° C. for 30 minutes and −65 ° C. for 30 minutes as one cycle, and the conduction resistance change rate is 10% or more. The number of cycles was examined. If it was 1000 cycles or more, it was determined to be acceptable. The results are also shown in Table 2.

  As described above, it can be seen that the substrate prepared according to the present invention is at a level that is not particularly problematic in actual use.

(A)-(g) is sectional drawing in each process of this invention. It is sectional drawing of the pattern used in the Example.

Explanation of symbols

1. Board
2. Conductor circuit
3. Insulating layer
4. Via
5. Palladium
6. Electroless plating
7. Conductor layer (sputter layer)
8. Plating resist
9. Circuit pattern
20. Via
21. Insulating layer
22. Conductor circuit

Claims (4)

  A print comprising at least one or more insulating layers, two circuit conductor layers provided on both surfaces of the insulating layer, and via holes filled with electroless plating metal for connecting the two circuit conductor layers A printed wiring board, being a wiring board, wherein at least a part of one circuit conductor layer is formed by sputtering.   An insulating layer was provided on the inner layer circuit board, a via hole for interlayer connection was made in the insulating layer, the via hole was filled with electroless plating, and a power feeding layer was formed on the surface of the filled insulating layer by sputtering. Thereafter, a method for producing a printed board comprising forming a photoresist layer, forming a circuit conductor by plating only at a portion to be a circuit, and etching away an unnecessary portion of the plating.   The method for producing a printed board according to claim 2, further comprising a step of polishing and smoothing a surface of the insulating layer after filling the holes in the electroless plating.   The method for producing a printed board according to claim 2 or 3, wherein electroless palladium plating is performed as a pretreatment for filling the via holes with electroless plating.

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