JP2005136696A - A/d conversion circuit and disk playback system using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D conversion circuit which can operate with low voltage and in simple configurations and a disk playback system using it. <P>SOLUTION: This A/D converter generates a binary digital signal by using an encoder by forming a plurality of bit thermometer codes of a plurality of bits by using a plurality of voltage comparators to one input terminal of which a plurality of reference voltages formed by a resistance ladder are inputted, and to the other input terminal of which an input analog signal is commonly supplied. The output terminals of differential amplifier circuits included in the voltage comparator are connected through a resistance ladder for averaging to each other. There are arranged first and second terminating circuits constituted of first and second dummy amplifier circuits constituted in the same circuit configurations as those of the differential amplifier circuits and first and second resistance elements arranged between both ends of their low level and high level saturated output voltages and the resistance ladder for averaging and the output terminals of the first and second dummy amplifier circuits corresponding to them. Thus, it is possible to correct the input/output characteristics of the differential amplifier circuit to ideal characteristics. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an A / D conversion circuit and a disk reproduction system using the A / D conversion circuit, and more particularly to a technique effective for use in a parallel A / D conversion circuit.

  In a read channel of an ODD (Optical Disk Drive) such as a DVD (Digital Versatile Disk) or an HDD (Hard Disk Drive), that is, a system that reads a signal recorded on a disk, signal processing (demodulation) is performed by digital signal processing. In this case, an A / D (Analog Digital) converter is essential. In recent years, with ODD, intersymbol interference has occurred as the reading speed has increased and the recording density has increased, and data cannot be read correctly with the current mainstream analog method. The breakthrough of this problem is data demodulation by digital signal processing. For this purpose, an A / D converter that converts an analog signal from the pickup into a digital signal is indispensable.

  Among the ODDs described above, for DVD use, the A / D converter needs to have a resolution of about 6 bits and a conversion rate of several hundred MSps (Mega Samples Per second). In this specification, a parallel type (flash type) A / D converter (hereinafter also referred to as ADC) is generally used. The parallel type is a group of comparators provided for the number of resolutions, and is a system that simultaneously converts an input signal and a plurality of reference voltages corresponding to codes to obtain a digital output, but the offset of the comparator is the non-linearity of the ADC Influences. Although a comparator having an offset correction mechanism may be used, a technique for reducing the offset by averaging (averaging) is often used. The averaging method suppresses the offset by the averaging effect obtained by connecting adjacent comparator outputs with resistors, and only adds a resistor, which increases the comparator offset without increasing the area and power consumption. It is an effective technique that can reduce the above.

"A 6b 1.3G Samples / s A / D Converter in 0.35um CMOS" IEEE 2001 International Solid State Circuits Conference as an example of a parallel A / D converter with a comparator that performs offset suppression by averaging using a resistor ladder Proceedings pp.126-127, K. Choi et al. In this document, the averaging resistor ladder termination is provided with nine dummy comparators on one side. Also, as an example of the termination circuit for the averaging resistor ladder, "A 6b 1.6GSample / s Flash ADC in 0.18um CMOS using Averaging Termination" IEEE 2002 International Solid State Circuits Conference Proceedings pp.168-169, P. Scholtens et al. There is.
"A 6b 1.3GSamples / s A / D Converter in 0.35um CMOS" IEEE 2001 International Solid State Circuits Conference Proceedings pp.126-127, "A 6b 1.6GSample / s Flash ADC in 0.18um CMOS using Averaging Termination" IEEE 2002 International Solid State Circuits Conference Proceedings pp.168-169,

  In the present inventors, when the resolution is n bits as shown in FIG. 11 prior to the present invention, 2 n resistance groups (resistance ladder), 2 n power-1 voltage comparison A parallel A / D converter composed of a group of devices and an encoder was studied. In this parallel A / D converter, each voltage comparator determines the amplifier that amplifies the differential input signal and the polarity of the amplifier output, and holds it as logic “1” or logic “0” data. Consists of a latch. The reference voltage group obtained by dividing the input reference voltage with a resistor ladder and the input voltage are simultaneously compared using the voltage comparator group, and 2 n-1 comparator output signals are obtained. This signal becomes “1” when the input reference voltage is low and the comparator output signal is “0” when the input reference voltage is low, and “0” when the input voltage is high. Yes. This is called a “thermometer code”, and the encoder is a circuit that obtains an n-bit binary signal from the 2 n-1 thermometer code signals.

  Each voltage comparator in the parallel type A / D converter determines the magnitude relationship between each comparison reference voltage and the input voltage. If there is an error, that is, an offset voltage at the judgment point of this magnitude relationship, A The conversion characteristics of the / D converter deviate from ideal. In such an A / D converter, the analog input voltage range in which a code that is originally expected to be equal in the input voltage range of the A / D converter is output is widened or narrowed. In some cases, it will disappear completely. The former problem appears as degradation of differential nonlinearity, and the latter is an abnormality in conversion characteristics called miscode.

  It is known that the offset is inversely proportional to the element size. Therefore, if the element size is increased, the offset can be kept small. However, when high-speed operation is required, it is necessary to reduce the element size and reduce the parasitic capacitance. For this reason, it is difficult to achieve both offset and speed. Therefore, as described in Non-Patent Documents 1 and 2, the use of a technique called averaging that suppresses the offset by connecting the comparator outputs with resistors and averaging the offsets between adjacent comparators was studied. There is a problem that the comparison characteristics of the comparators at the end of the comparator group fluctuate.

  The problem that the comparison characteristic fluctuates will be described with reference to FIG. The comparator is generally composed of an internal amplifier that amplifies the input and a latch unit that determines whether the output is high or low with respect to a certain threshold value and determines logical “1” or logical “0”. It also has a function to hold data). FIG. 12 shows the input / output characteristics of the internal amplifier constituting the comparator. In FIG. 12, the horizontal axis represents the comparison input voltage of each comparator, that is, the input voltage of the A / D converter, and the vertical axis represents the output voltage of the internal amplifier. When the input voltage is lower than the negative maximum value, all the internal amplifiers output the preamplifier output saturation voltage 2 or a voltage close thereto, and the subsequent latch determines that it is “0”. As the input voltage increases in the positive direction from the negative maximum value, the internal amplifier outputs a voltage exceeding the latch threshold voltage in the order of the comparators 1, 2, 3,..., And the latch output is also “1”. Become. In FIG. 12, the solid line is the ideal input / output characteristic of the internal amplifier, and the alternate long and short dash line is the characteristic when an appropriate measure is not taken at the end of the averaging resistance ladder.

  In order to clarify the problem, the operation when the input voltage Vin = Va at which the comparator at the end of the comparator group operates and when the input voltage Vin = Vb at which the comparator at the center of the comparator group operates is shown. consider. The case of Vin = Va is shown by the equivalent circuit in FIG. The input voltage Vin satisfies VRB <Vin <VRB + Vlsb. Here, Vlsb is a voltage equivalent to 1 LSB ((VRT−VRB) / 2 to the nth power). At this time, only the comparator 1 is expected to output “1”, and the other comparators are expected to output “0”.

  The internal amplifier in FIG. 13 is a model of an actual amplifier, and a resistor Ro corresponding to the amplifier output resistance is connected in series with an ideal signal source output. Now, in order for the comparator 1 to output “1”, the output voltage of the internal amplifier needs to exceed the threshold voltage of the latch in the subsequent stage. At this time, a current flows to the internal amplifier after the comparator 2 that outputs a voltage lower than that of the amplifier 1 through the resistors Ro and Ravg. For this reason, the output potential drops by this current × Ro at the internal amplifier output terminal of the comparator 1. There is a case where the threshold voltage falls below the threshold voltage due to this potential drop. In this case, the subsequent latch remains “0”. In other words, if the input voltage of the comparator is not higher than the original transition point (change point “0” → “1”), the output does not become “1”.

  In addition, this problem occurs not only in the comparator 1. When the input voltage is in the range of VRB + Vlsb <Vin <VRB + 2Vlsb, the comparators 1 and 2 output “1”. However, at this time as well, as in the previous example, a current is generated from the internal amplifiers of the comparators 1 and 2 toward the third and subsequent steps, and the output voltage of the comparators 1 and 2 decreases. In this case, since the current is supplied by the internal amplifiers 1 and 2, the fluctuation is smaller than the case where only the internal amplifier 1 is supplied, but there is still an error in the conversion. As described above, this phenomenon gradually decreases, but it also occurs in the inner comparator. For this reason, a plurality of redundant comparator amplifiers are provided to avoid this problem.

  Next, in the equivalent circuit shown in FIG. 14, the operation of the comparator at the center of the comparator group is considered. In this case, the input voltage Vin is in the range of (VRT + VRB) / 2 <Vin <(VRT + VRB) / 2 + Vlsb. In this case, "1" is output from the comparator 1 to the n-1th power of the comparator 2, and "0" is output thereafter. As shown in FIG. 12, the output voltage difference between the n−1th power amplifier of the comparator 2 and the adjacent internal amplifier is constant at ΔV shown in FIG. 12. The current ΔV / Ravg flowing through the resistor Ravg is equal everywhere in the n−1 power of the internal amplifier 2 and the internal amplifier in the vicinity thereof. Therefore, no current flows in and out of the output terminals of these amplifiers.

  Therefore, fluctuations due to the output resistance and current in the output voltage of these internal amplifiers do not occur. Of course, this current is output from an internal amplifier somewhere in the comparator group and flows into another internal amplifier. However, in the comparator where the current flows in and out, the difference between the input voltage Vb and the comparison reference voltage is large, the internal amplifier is strongly saturated, and a small amount of current does not affect the output. It doesn't matter. FIG. 15 shows the influence of this problem on the A / D converter conversion characteristics, that is, the relationship between the input analog voltage and the output digital code. Whereas the ideal conversion characteristic indicated by the dotted line is a straight line, a converter having a problem has a conversion characteristic of a solid line in the figure. Specifically, it becomes a distortion at a large amplitude.

  In order to avoid this problem, a method of providing an extra comparator as in Non-Patent Document 1 is known. FIG. 16 shows a parallel A / D converter examined prior to the present invention in accordance with the technique of Non-Patent Document 1. In the figure, a portion indicated as “termination circuit” is an amplifier group provided to avoid the above problem. Distortion is avoided by expanding the apparent input range of the A / D converter, adding redundancy to the conversion characteristics, and using only a range where nonlinearity does not become a problem. In the non-patent document 1, for 63 comparators, 9 amplifiers are provided at each end, for a total of 18 amplifiers (hereinafter referred to as dummy amplifiers).

  As a result, the area and power consumption increase by about 30%. In addition, the fact that there is a redundancy in the conversion characteristics means that the maximum signal-to-noise ratio that can be obtained by this A / D converter is also reduced accordingly. In the example of Non-Patent Document 1, the maximum amplitude that can be input to the A / D converter is about 80%, so the maximum signal-to-noise ratio is degraded by 2 dB, and the effective number of bits is degraded by 0.35 bits. It will end up. Further, when the power supply voltage is high, it is easy to take the input range of the A / D converter a little more, but it is difficult at the time of the low power supply voltage. That is, when the above-described method using the dummy amplifier is employed at a low power supply voltage, it becomes difficult to maintain the input range of the A / D converter.

  In order to avoid this problem, Non-Patent Document 2 is an example in which a ladder termination circuit of an averaging resistor is examined. Non-Patent Document 2 proposes a termination circuit in which a resistance having a resistance value of 1.5 Ravg−0.5 Ro is combined with a dummy comparator. As a result, the number of dummy comparators is reduced to four. The details of this termination circuit are not described in the same document 2, so the details are unknown. However, it is not easy addition of resistance but subtraction, and the value of Ro which is the output resistance of the comparator is required. Therefore, it is considered difficult to produce a resistor of “1.5 Ravg−0.5 Ro” with a simple circuit. Naturally, an increase in power and area due to this circuit is expected.

  An object of the present invention is to provide an A / D conversion circuit capable of low voltage operation with a simple configuration and an optical disk reproduction system using the A / D conversion circuit. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of reference voltages formed by a resistor ladder are input to one input terminal, and a multi-bit thermometer code is formed by a plurality of voltage comparators to which an input analog signal is commonly supplied to the other input terminal. In the A / D converter that generates a binary digital signal by the encoder, the output terminals of the differential amplifier circuit included in the voltage comparator are connected to each other by an averaging resistor ladder, and the differential amplifier circuit First and second dummy amplifier circuits having the same circuit configuration as above, respective high-level and low-level saturated output voltages, both ends of the averaging resistor ladder, and corresponding output terminals of the first and second dummy amplifier circuits The first and second termination circuits including the first and second resistance elements provided between the first and second resistors are arranged, and the input / output characteristics of the differential amplifier circuit are corrected toward the ideal characteristics.

  The outline of other representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, in an optical disk reproduction system including a read channel including an A / D conversion circuit that converts an analog electrical signal read by an optical pickup into an analog electric signal at an analog front end and converts the signal into a digital signal, A plurality of formed reference voltages are respectively input to one input terminal, and a multi-bit thermometer code is formed by a plurality of voltage comparators to which an input analog signal is commonly supplied to the other input terminal. A / D converter that generates a binary digital signal, the output terminals of the differential amplifier circuit included in the voltage comparator are connected to each other by an averaging resistor ladder, and the same circuit configuration as that of the differential amplifier circuit First and second dummy amplifier circuits, high-level and low-level saturated output voltages, and the averaging resistor ladder A first and second termination circuit comprising a first and a second resistance element provided between an end and the corresponding output terminal of the first and second dummy amplifier circuits is arranged to input the differential amplifier circuit. Correct the output characteristics toward the ideal characteristics.

  In a parallel A / D converter that performs averaging using a resistance ladder, an increase in power and area due to the addition of a termination circuit for increasing accuracy can be suppressed.

FIG. 1 is a block diagram showing an embodiment of a parallel A / D conversion circuit according to the present invention. In this embodiment, a reference voltage generating resistor group (resistor ladder) composed of 2 n resistors R is composed of 2 ⁿ −1 (2 ⁿ −1) voltage comparator groups and an encoder. In the parallel A / D conversion circuit, an averaging resistor ladder including 2 n averaging resistors Ravg and a termination circuit thereof are provided. The circuit shown in the figure is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

A high-level reference voltage VRT and a low-level reference voltage VRB supplied from the outside are divided by a resistor group (resistor ladder) composed of a resistor R inside the chip to create a 2 n −1 level reference voltage. The voltage and analog input voltage Vin are simultaneously compared by a voltage comparator group. The output of the 2 n-1 bit comparator group is inverted at a certain boundary due to the magnitude relationship between the input voltage and the reference voltage. This comparator group output is called a thermometer code, and the input analog value is known from the output boundary. The thermometer code is converted into an n-bit binary code consisting of b _{0 to} b _n-1 by an encoder.

The comparator includes 1 to 2 ⁿ −1 and includes a differential amplifier circuit (preamplifier) PA corresponding to 2 ⁿ −1 reference voltages formed by the resistor ladder. Although not particularly limited, the differential amplifier circuit PA includes a complementary input terminal including a positive phase input terminal (+) and a negative phase input terminal (−). The analog input voltage Vin is applied to the positive phase input terminal (+). Is supplied, and a reference voltage is supplied to the negative phase input terminal (−). The output signal of the differential amplifier circuit PA is transmitted to the latch, and logic “0” and “1” are judged to generate a temperature code composed of CO1 to CO2 ⁿ −1 and converted into a binary code by the encoder. Is done.

Reference voltages VRT and VRB (VRT> VRB) in 2 n-1 comparators from the comparator (1) corresponding to the comparison outputs CO1 to CO2 ⁿ -1 to the comparator (2 n-1). ) And the input voltage Vin are compared in parallel. In such a parallel A / D converter, termination circuits are added to both ends of an averaging resistor ladder surrounded by a broken line in the figure. Each of the termination circuits includes a resistor Ravg ′ set to a resistance value that corrects the input / output characteristics of the differential amplifier circuit PA toward ideal characteristics, and one dummy differential amplifier circuit (dummy amplifier) DPA1, DPA2. Consists of. 1 resistor Ravg 'is connected between the output terminal of the dummy differential amplifier circuit DPA1 and one end of the corresponding averaging resistor ladder. The other resistor Ravg ′ is connected between the output terminal of the dummy differential amplifier circuit DPA2 and the other end of the corresponding averaging resistor ladder.

  The termination circuit includes another differential amplifier in which the input / output characteristics of the differential amplifier circuit PA of the comparator (2 to the power of 2 −1) receiving the highest reference voltage and the comparator 1 receiving the lowest reference voltage are adjacent thereto. Correction is performed so as to obtain ideal characteristics in relation to the circuit. In the differential amplifier circuit PA as a preamplifier of the comparator for comparison operation, the input signal is input to the (+) input terminal and the reference voltage for comparison is input to the (−) input terminal as described above. Unlike the differential amplifier circuit PA for comparison operation, the intermediate value of the reference potential ((VRT + VRB) / 2) is input to the (+) input terminals of the dummy differential amplifier circuits DPA1 and DPA2 provided in FIG. Although not particularly limited, the input signal Vin is supplied to the (−) input terminal.

  FIG. 2 is an input / output characteristic diagram for explaining an example of the operation of the parallel A / D conversion circuit of FIG. As will be described later, the voltage inputted to the (+) input terminals of the dummy differential amplifier circuits DPA1 and DPA2 is not limited to the intermediate value of the reference potential ((VRT + VRB) / 2), but the dummy differential amplifier circuit DPA1. In order to correct the input / output characteristics of DPA2 to the ideal characteristics, when the input voltage Vin is a predetermined voltage lower than the intermediate voltage, the low level in the saturation region such as the amplifier output saturation voltage 2 as shown in FIG. Alternatively, when the input voltage Vin is a predetermined voltage higher than the intermediate voltage, it may be a high level in the saturation region such as the amplifier output saturation voltage 1 as shown in FIG.

  In FIG. 2, the alternate long and short dash line is a characteristic when there is no termination circuit, and as described above, the difference in transition point voltage between adjacent comparators is not constant at the end of the comparator group. When the input / output characteristics of the dummy differential amplifier circuits DPA1 and DPA2 provided in the termination circuit proposed in this figure are overlapped, a bold broken line in FIG. 2 is obtained. Since the dummy differential amplifier circuits DPA1 and DPA2 of the termination circuit have the connection polarity opposite to that of a normal comparator, the input / output characteristics have a reverse pattern. Attention is now paid to the operation of the comparator 1 when the input voltage Vin of the A / D converter is the voltage Va in FIG. Without the termination circuit, the current flowing through the averaging resistor ladder is supplied, so that the preamplifier output is reduced by δ.

In this embodiment, since the amplifier output saturation voltage 1 of the dummy differential amplifier circuit DPA1 is added via the resistor Ravg ′ through the use of the termination circuit, the one end of the averaging resistor ladder is connected via the resistor Ravg ′. As shown in FIG. 13, there is no current from the differential amplifier circuit PA receiving the lowest reference voltage that has been supplied to one end of the averaging resistor ladder until now. . As a result, the potential drop at the output resistance Ro of the differential amplifier circuit does not occur, the original output voltage of the differential amplifier circuit PA appears at the output terminal, and the comparison characteristic becomes the ideal solid line in FIG. . The magnitude of the current supplied from the dummy amplifier DPA1 is adjusted by the resistance value of the resistor Ravg ′. Now, if the amplifier output saturation voltage 1 is Vsat1 and the logic threshold voltage of the latch is Vth, the following equation (1) must be satisfied in order to supply the current required by the resistor ladder from the dummy amplifier without excess or deficiency: There is.
(Vsat1−Vth) / Ravg ′ = ΔV / Ravg = Av V # 1LSB / Ravg (1) In the above equation (1), V # 1LSB is a voltage corresponding to 1LSB, and Av is the gain of the preamplifier PA. is there. The denominators Ravg and Ravg 'on the right side and the left side of the above equation generally use the same type of element in a semiconductor integrated circuit, and high consistency can be expected if attention is paid to the arrangement. There are some fluctuations in the molecular term depending on the power supply voltage, temperature, etc., but if the parallel A / D converter has a realistic resolution (6 to 8 bits), the influence of the fluctuation can be almost ignored. . A configuration for improving the accuracy of this correction with a small increase in circuit will be described later.

  Although the case where a voltage of (VRT + VRB) / 2 is applied to the (+) input terminals of the dummy amplifiers DPA1 and DPA2 has been described, the present invention is not limited to this voltage. The operation when a voltage other than (VRT + VRB) / 2 is applied will be described. If this voltage is set to a voltage lower than (VRT + VRB) / 2, the amplifier goes out of the saturation region, and the amplifier output voltage becomes smaller than Vsat1 in the equation (1). In this case, the necessary correction current can be secured by reducing Ravg ′ accordingly. On the other hand, when a voltage higher than (VRT + VRB) / 2 is applied, the output voltage does not change at Vsat1. This is because the dummy amplifier is only saturated more strongly and the output voltage does not change. As described above, the voltage applied to the (+) input terminal voltage of the dummy amplifier should normally be (VRT + VRB) / 2, but is not limited to this.

  Although omitted in FIG. 2, in the differential amplifier circuit corresponding to the highest reference voltage, the output saturation voltage 2 of the dummy differential amplifier circuit DPA2 is reversed via a resistor Ravg ′ by using a termination circuit. As a result, the current is drawn from the other end of the averaging resistor ladder via the resistor Ravg ′, and there is no current flowing toward the differential amplifier circuit PA receiving the highest reference voltage from the averaging resistor ladder. As a result, the potential drop at the output resistance Ro of the differential amplifier circuit does not occur, the original output voltage of the differential amplifier circuit PA appears at the output terminal, and the comparison characteristic is corrected to the ideal input / output characteristic. The

  In the embodiment of FIG. 1, the termination circuit of the averaging resistor ladder requires 18 dummy amplifiers in order to obtain the same performance in the example of Non-Patent Document 1, but the dummy amplifiers are connected to DPA1 as described above. , DPA2 can be used, and the maximum input amplitude is not reduced due to the presence of redundancy, and the signal-to-noise ratio is not lowered, and the operating voltage can be lowered. This is because the input voltage of the dummy amplifiers DPA1 and DPA2 uses a signal originally in the A / D converter and does not require redundancy.

  In the input / output characteristics of FIG. 2, when the input voltage of the A / D converter is in the vicinity of the midpoint voltage, the output voltages of the dummy amplifiers DPA1 and DPA2 also decrease as shown. However, at this time, the preamplifier output at the end of the comparator group such as the amplifiers 1 and 2 adjacent to the dummy amplifier DPA1 is saturated at the amplifier output saturation voltage 1, and the drive capability hardly affects the dummy amplifier DPA1. . Furthermore, even if the A / D converter input voltage increases, the situation does not change, and the dummy amplifier DPA1 does not affect the comparison results of the comparators after the comparator 1. As described above, this termination circuit improves the characteristics at the time of input voltage of the A / D converter as judged by the comparator at the end of the comparator group, and operates as an effective termination circuit. It can be seen that this does not affect other comparators.

  The embodiment of FIG. 1 shows a case where the preamplifier output (differential amplifier circuit PA) is single-ended (a system in which a signal is transmitted by a potential difference between a single-phase signal and ground). In this case, by connecting the input terminals as described above, the dummy amplifiers DPA1 and DPA2 having input / output characteristics opposite to those of the differential amplifier circuit PA can be connected in accordance with the principle of the present invention. In the case of a differential configuration (a method in which a signal is transmitted with a potential between two signal lines of normal phase and reverse phase), the above-described reverse input / output characteristics can be obtained not only by the input terminal but also by the connection method of the output terminal. it can. This fully differential preamplifier has a feature of high noise resistance because it transmits differential signals.

  FIG. 3 is a block diagram showing another embodiment of the parallel A / D conversion circuit according to the present invention. In this embodiment, the averaging resistor ladder termination circuit in the parallel A / D conversion circuit is a modified example in which the accuracy is further improved. In the embodiment of FIG. 1, a current obtained by dividing the difference between the output voltage of the nth power-1 of the comparator 2 and the output voltage of the dummy comparator 1 by the averaging resistor Ravg ′ is supplied. As shown in the above formula (1), the current value supplied from the termination circuit does not necessarily match the current value required by the resistance ladder structurally. A technique of placing a small number of dummy amplifiers between the termination circuit and the comparator group is also used. Of course, a large number of dummy amplifiers are not required. This embodiment is a configuration example in which a dummy amplifier and an averaging resistor Ravg are further provided in one stage in the termination circuit as compared with the embodiment of FIG. Even in this case, as in Non-Patent Document 1, about nine dummy required for one side is sufficient.

  FIG. 4 omits the interconnections and transistors connected to each other for receiving the output from the adjacent comparator from FIG. 5 or 6 and correcting the offset. The specific circuit diagram of one Example of the differential amplifier circuit as a preamplifier part used for the parallel type A / D conversion circuit which concerns on this invention, and a back | latter stage amplifier is shown. In this embodiment, as a representative, a fully-differential preamplifier corresponding to one reference voltage, a subsequent amplifier and a bias voltage generation unit corresponding thereto are exemplarily shown.

  The bias voltage generator is operated with a power supply voltage such as 3.3V. A constant current is formed by connecting a reference resistor and a diode-connected N-channel MOSFET Q1 between the power supply voltage and the circuit ground potential. That is, the resistance value of the reference resistor is increased to form a minute constant current that can be regarded as a constant current with respect to fluctuations in the power supply voltage. For the MOSFET Q1, MOSFETs Q2 and Q3 are connected in a current mirror form, and a constant current is drawn from each drain.

  A diode-type P-channel MOSFET Q4 is provided between the drain of the MOSFET Q2 and the power supply voltage. P-channel MOSFETs Q5 and Q6 are also connected in series between the drain of MOSFET Q3 and the power supply voltage. The MOSFET Q5 is connected to the MOSFET Q4 in the form of a current mirror, and the gate of the MOSFET Q6 is connected to the drain of the MOSFET Q5. The gate-source voltage of the MOSFETs Q1, Q2 and Q3 is the bias voltage Vbn for the N-channel MOSFET, the gate-source voltage of the P-channel MOSFET Q6 is the P-channel bias voltage Vbp, and the gate of the P-channel MOSFET Q4. , The source-to-source voltage is the P-channel bias voltage Vbc.

  The preamplifier (differential amplifier circuit) includes a differential circuit and a load circuit. The differential circuit includes N-channel differential MOSFETs Q10 and Q11, an N-channel MOSFET Q12 provided between the common source and the circuit ground potential, and between the drains of the differential MOSFETs Q10 and Q11 and the power supply voltage. P channel MOSFETs Q13 and Q14 provided in the circuit. The gates of the differential MOSFETs Q10 and Q11 are a negative phase input terminal (−) and a positive phase input terminal (+), respectively. The bias voltage Vbn is supplied to the gate of the MOSFET Q3 to operate as a constant current source. Similarly, the bias voltage Vbp is supplied to the gates of the P-channel MOSFETs Q13 and Q14 to operate as a constant current source.

  In this embodiment, in order to enable an operating voltage at a low voltage, the drains of the differential MOSFETs Q10 and Q11 are connected to the sources of P-channel MOSFETs Q15 and Q16, respectively, which receive the bias voltage Vbc at their gates. Between the drains of these MOSFETs Q15 and Q16 and the circuit ground potential, N-channel MOSFETs Q17 and Q18 in the form of diodes are provided as load means. A normal phase output and a negative phase output are formed from the drains of the MOSFETs Q16 and Q17 and the MOSFETs Q16 and Q18 connected in common.

  The MOSFETs Q15 and Q16 make the drain voltages of the differential MOSFETs Q10 and Q11 constant by the bias voltage Vbc. If the current flowing through the MOSFET Q12 is equal to the current flowing through the MOSFETs Q13 and Q14 as the current I, when the differential inputs (+) and (-) are equal, a current of I / 2 flows through the differential MOSFETs Q10 and Q11. Therefore, the remaining I / 2 current flows through the MOSFETs Q17 and Q18 via the MOSFETs Q15 and Q16. When a voltage difference occurs between the differential inputs (+) and (−), the current I formed by the MOSFET Q13 corresponding to the voltage difference is distributed to the differential MOSFETs Q10 and Q11 corresponding to the voltage difference. As a result, a current corresponding to the inverse ratio of the distribution ratios of the corresponding differential MOSFETs Q10 and Q11 flows through the load MOSFETs Q17 and Q18 to form complementary output voltages (+) and (−).

  By such an amplifying operation, in the differential amplifying circuit of this embodiment, the complementary output signal is formed by the N-channel type load MOSFET based on the ground potential of the circuit, so that the amplifying operation and the level shifting operation are performed. Are performed at the same time. As a result, the comparator provided in the subsequent stage can be operated at a low voltage such as 1.5V. Since the comparator section is a digital circuit, it operates sufficiently even at a low voltage such as 1.5V. In the configuration in which the level-shifted output signal is obtained in the preamplifier unit as described above, a special level shift circuit is provided for the digital circuit unit and the preamplifier operating at a low voltage such as 1.5V. It can be connected directly without

  The post-stage amplifier includes an amplification unit and a latch unit. The amplifying unit is provided between the N-channel type differential MOSFETs Q20 and Q21, the common source thereof and the ground potential of the circuit, the N-channel MOSFET Q22 having the gate supplied with the bias voltage Vbn, and the differential MOSFETs Q20 and Q21. MOSFET Q23 provided between the drains. The gates of the differential MOSFETs Q21 and Q22 are connected to the positive phase output (+) and the negative phase output (−) of the preamplifier. A reset pulse reset is supplied to the gate of the MOSFET Q23.

  The latch unit is formed in a latch form by cross-connecting gates and drains of N-channel MOSFETs Q24 and Q25 and P-channel MOSFETs Q27 and Q28, respectively. A power supply voltage such as 1.5 V is supplied to the sources of the P-channel MOSFETs Q27 and Q28, and N receiving the clock clk as an activation signal between the sources of the N-channel MOSFETs Q24 and Q25 and the ground potential of the circuit. A channel MOSFET Q26 is provided.

  In the latch circuit, the MOSFET Q23 is turned on by the reset pulse reset during the non-operating period when the clock clk is at a low level, and the gates and drains of the differential MOSFETs Q20 and Q21 and the latched N-channel Q24 and Q25 and the P-channel MOSFETs Q27 and Q28 Short-circuit to the same potential. When the MOSFET Q23 is turned off by the reset pulse reset, the differential MOSFETs Q20 and Q21 form an output signal corresponding to the output signal of the preamplifier. When the complementary circuit of the amplifying unit becomes a constant voltage difference required for the latch operation and the MOSFET Q26 is turned on by the clock clk to activate the latch circuit, the positive feedback amplification of the N-channel MOSFETs Q24 and Q25 and the P-channel MOSFETs Q27 and Q28 By operation, a high-level / low-level binary signal corresponding to the amplified output from the amplifying unit is formed at a high speed, and the clock clk is held for a high level. The logic threshold value in such a latch circuit is a voltage at which the levels of the two complementary input signals are equal to each other.

  In the case of using a preamplifier (PA) which is provided with such a positive phase output terminal (+) and a negative phase output terminal (−) and transmits a complementary signal to the next stage circuit, the averaging resistor Rave Are provided between the output terminals (+) and (-) of the adjacent amplifiers corresponding to the complementary output terminals (+) and (-), respectively. Here, the term “adjacent” refers to the relationship between the preamplifiers to which adjacent reference voltages are supplied.

  FIG. 5 is a block diagram showing another embodiment of the parallel A / D conversion circuit according to the present invention. In this embodiment, a preamplifier and a post amplifier as shown in FIG. 4 are used. The amplifier provided at the front end of the latch in FIG. 4 corresponds to the rear stage amplifier shown in FIG.

In FIG. 5, each termination circuit is composed of two preamplifiers. These preamplifiers are hatched to distinguish them from preamplifiers that perform ADC operation. In this embodiment, the two preamplifiers are arranged in the same manner as in the embodiment of FIG. 3 so that the mutual specification of the preamplifiers at the ends can be made closer to the ideal characteristics. That is, the input / output characteristics of the first preamplifier are obtained by combining the dummy preamplifier as shown in FIG. 1 and the resistor Rave ′ provided at the end with the dummy preamplifier adjacent to the first preamplifier and the averaging resistor Rave interposed therebetween. The characteristic correction can be easily performed. The same applies to the 2 ⁿ -1 th preamplifier provided on the high voltage side.

In this embodiment, the (+) input terminal of the preamplifier provided in the termination circuit is connected to the analog input terminal in the same manner as the preamplifier PA that performs other ADC operations. The reference voltage VRB is applied to the (−) input terminal of the dummy preamplifier adjacent to the first preamplifier. The reference voltage VRT is applied to the (−) input terminal of the 2 ⁿ −1st adjacent dummy preamplifier. The (+) input terminal of the dummy preamplifier provided at the end of the termination circuit is connected to the analog input terminal in the same manner as the preamplifier PA that performs other ADC operations. An intermediate voltage of the reference voltage is applied to the (−) input terminal. Instead, the (+) output of the dummy preamplifier provided at the end of the termination circuit is connected to the averaging resistor ladder to which the (−) output terminal of the other comparator is connected, and is provided at the end of the termination circuit. The (−) output terminal of the dummy preamplifier is reversed. In this way, the output of the terminal unit is not connected to the output side, but the terminal connection is reversed to that of the comparator for comparison, so that the amplifier output saturation voltage 1 and the amplifier output with the reverse input / output characteristics as shown in FIG. A saturation voltage 2 is formed.

  FIG. 6 is a block diagram showing still another embodiment of the parallel A / D conversion circuit according to the present invention. This embodiment is a modification of FIG. 5, and the number of ladder resistors and preamplifiers is reduced to half that of the embodiment of FIG. However, the number of averaging resistors is the same as that shown in FIG. Corresponding amplifiers and comparators are provided corresponding to such averaging resistors. That is, interpolation (interpolation) can be performed by the averaging resistor, and the ladder resistor and the preamplifier can be halved as described above. In this case, since the intermediate voltage is generated by dividing the resistance between the preamplifier outputs, it is essential to keep the voltage between the adjacent amplifier outputs constant in order to maintain the linearity of the A / D converter.

  FIG. 7 shows a specific circuit diagram of an embodiment of a differential amplifier circuit and a post-stage amplifier as a preamplifier unit used in the parallel A / D converter circuit shown in FIGS. 5 and 6. Yes. In a parallel type high-speed A / D converter, it is preferable to use a multi-stage configuration in order to achieve both a voltage gain and a band (comparison time) in the comparator, and a pre-amplifier and a post-amplifier. In this case, if the preamplifier can secure a sufficient voltage gain (10 times or more, tens of times if possible), offset correction using only the preamplifier is sufficient, but such high voltage gain is difficult as the operation speed increases. In this case, offset correction is necessary for each of the preamplifier and the subsequent amplifier. Here, in addition to the offset correction by the averaging resistor having the termination circuit of the present invention, the offset correction is added in the subsequent amplifier.

  In FIG. 7, the bias voltage generation unit and the preamplifier unit are the same as those in the embodiment of FIG. In this embodiment, P-channel MOSFETs Q29 to Q32 are added to the latch section of the post-stage amplifier in order to perform offset correction in the post-stage amplifier. Signals from adjacent comparators are input to the gates of these MOSFETs for offset correction. At the output of each subsequent amplifier, the fluctuation due to the influence of the comparator input offset is reversed. In this way, all subsequent amplifiers cancel out the offsets through the divided gate connections. Since the output voltage is fed back as a result, variations in all factors affecting the output are corrected. In addition, since this configuration only divides the original load MOSFET, the load accompanying averaging is small and suitable for high-speed operation.

  FIG. 8 shows a circuit diagram of the post-stage amplifier of FIG. This figure is for explaining the relationship with other post-stage amplifiers, and shows the relationship between the i-th post-stage amplifier and the i + 1-th and i-1-th post-stage amplifiers adjacent thereto. In this embodiment, a resistor such as an averaging resistor is not used for coupling with an adjacent rear stage amplifier for offset correction, and the load MOS transistor in the differential amplifier circuit of the rear stage amplifier input stage is 3 as shown in FIG. Dividing and connecting one MOSFET Q27, Q28 gate and drain crosswise, and connecting the remaining two MOSFETs Q29, Q30 and Q31 and Q32 gates to the output of the adjacent subsequent amplifier, respectively, the gate voltage of the load MOS is Since it is determined by itself and the output of the adjacent post-stage amplifier, information on the output of the adjacent post-stage amplifier enters the load resistance when the load MOS is viewed from the input differential pair. This has an averaging effect. This connection also has a positive feedback function.

  Comparing the circuit using the averaging resistor in the present invention and the circuit in which the output information of the adjacent comparator enters the load resistance when the load MOSFET is viewed from the input differential pair, the circuit using the averaging resistor is shown in FIG. 2 (FIG. 12), the output voltage difference between adjacent comparators is constant. On the other hand, the output of the circuit using the mutual connection having the action of positive feedback can forcibly output the comparator saturation voltage 1 or 2 except the switching point from “0” to “1”. For this reason, it is appropriate to employ a circuit using an averaging resistor as a preamplifier and a circuit using a mutual connection having a positive feedback function at the final stage (immediately before the latch). In FIG. 5 and FIG. 6, in the amplifier provided in the previous stage of the latch, the adjacent ones are cross-connected to each other, indicating the connection relationship of FIG. 8.

  FIG. 9 is a block diagram showing an embodiment of a disk reproduction system for reading a signal recorded on a disk to which the present invention is applied. As described above, in an ODD such as a DVD or a read channel of an HDD, that is, a system that reads a signal recorded on a disk, an A / D converter is essential when performing signal processing (demodulation) by digital signal processing. Become. In the figure, the signal read from the laser pickup is input to the PRML read channel section after being subjected to filter processing and signal amplitude adjustment in an analog front end section composed of a filter and an automatic gain control amplifier.

  The PRML read channel section is configured as shown enlarged. The waveform that has passed through the analog front end is converted into a digital signal by the A / D converter ADC, PR waveform equalization is performed by the PR equalizer, and ML format decoding processing is performed by the Viterbi decoder. Data is played back. In addition, a clock synchronized with the reproduction data is reproduced by a loop composed of a frequency / phase comparator and a VCO. As the A / D converter ADC provided in the PRML read channel section, the A / D converter as shown in FIGS. 1, 3, 5 and 7 is used.

  FIG. 10 is a block diagram showing still another embodiment of the parallel A / D conversion circuit according to the present invention. In this embodiment, the dummy amplifiers DPA1 and DPA2 provided in the termination circuit are constantly supplied with a constant voltage so that the output of the dummy amplifier DPA1 becomes the amplifier output saturation voltage 1 in FIG. The output of DPA2 is set so as to be the amplifier output saturation voltage 2 in FIG. In this embodiment, in order to obtain the saturation voltage 1, the midpoint voltage is applied to the (+) input terminal of the dummy amplifier DPA1, and the lowest reference voltage VRB is supplied to the (−) input terminal. In order to obtain the saturation voltage 2, the midpoint voltage is applied to the (+) input terminal of the dummy amplifier DPA2, and the highest reference voltage VRT is supplied to the (−) input terminal. The voltage applied to both the input terminals (+) and (-) may be anything as long as the saturation voltages 1 and 2 are obtained.

  FIG. 17 is a block diagram showing still another embodiment of the parallel A / D conversion circuit according to the present invention having a configuration called a fully differential configuration. In the fully differential configuration, both the input signal and the reference voltage are supplied as two sets of signals, normal phase and reverse phase, and the information (signal component) is transmitted by the difference between the two sets of signals and has high noise resistance. Is a feature. Comparing the difference voltage of the positive and negative phases of the input signal with the difference voltage of the positive and negative phases of the reference voltage is a fully differential dummy amplifier (simply referred to as a dummy amplifier in the drawing), a fully differential amplifier ( In the drawing, the output is simply an amplifier).

  FIG. 18 shows a specific circuit configuration of one embodiment of the dummy amplifier (fully differential dummy amplifier) and the amplifier (fully differential amplifier) of FIG. Complementary to N-channel MOSFETs Q39 and Q40 that act as constant current sources to which a bias voltage is input to the gate, and N-channel MOSFETs Q35 and Q36 in a differential input section to which complementary analog input voltages Vinp and Vinm are input to the gate N-channel MOSFETs Q37 and Q38 in the differential input section to which the reference voltages Vrefp and Vrefm are input to the gates, and P-channel MOSFETs Q33 and Q34 that are diode-connected and function as loads, and are connected to the sources of the MOSFETs Q35 and Q36. Is connected to the drains of the N-channel MOSFET Q39, the sources of the MOSFETs Q37 and Q38 are connected to the drain of the N-channel MOSFET Q40, the drain of the MOSFET Q35 and the drain of the MOSFET Q33 are connected, and the drain of the MOSFET Q37 is further connected. Is connected to Voutm, the drain of MOSFET Q38 and the drain of MOSFET Q34 are connected, and the drain of MOSFET Q36 is further connected to Voutp.

  The 4-input fully differential amplifier has the following characteristics.

Output = gain × (input differential signal voltage−reference voltage difference signal) (2) The mutual conductance of the N-channel MOSFET Q35 and Q36 pair and the N-channel MOSFET Q37 and Q38 pair of this circuit is gmn, and that of the MOSFETs Q33 and Q34 is gmp. And The differential current i flowing through the MOSFETs Q33 and Q34 is
i = gmn (vinp-vinm) + gmn (vrefm-vrefp).

Transforming the second term,
i = gmn (vinp-vinm)-gmn (vrefp-vrefm)
= gmn [(vinp-vinm)-(vrefp-vrefm)] (3) Since the output voltage vout of this circuit is the current multiplied by the load resistance 1 / gmp,
vout = (1 / gmp) ・ gmn [(vinp-vinm)-(vrefp-vrefm)]… (4) ↑ ↑ ↑
Gain Input differential signal Reference voltage difference signal. Equation (4) is in the form of equation (2).

  By applying the present invention, it is possible to reduce the power and area of a parallel A / D converter that performs averaging using an averaging resistor ladder, and to increase the speed of the A / D converter. It becomes possible. That is, since the resistance ladder termination circuit of the averaging method can be configured with a simple element, an increase in power and area due to the addition of the termination circuit can be suppressed. In addition, the fact that power can be suppressed means that high-speed operation is possible when compared with the same power.

  A termination circuit can be configured without a large number of dummy amplifiers or complicated termination circuits, and operation at a low voltage is possible and the effect of averaging can be achieved. Therefore, without increasing the power of the A / D converter, S It is possible to improve the / N ratio, maintain the accuracy of the converter, or improve the accuracy. In the signal processing chip for HDD and DVD, the A / D converter has a considerable area and power consumption. Therefore, by reducing the power consumption and area in this part, the power consumption of the entire chip is reduced. The area can be increased.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the specific configurations of the pre-amplifier and the post-amplifier can take various embodiments. The present invention can be widely used for a parallel A / D conversion circuit and a disk reproduction system using the parallel A / D conversion circuit.

1 is a block diagram showing an embodiment of a parallel A / D conversion circuit according to the present invention. FIG. FIG. 3 is an input / output characteristic diagram for explaining an example of the operation of the parallel A / D conversion circuit of FIG. 1. It is a block diagram which shows another Example of the parallel type A / D conversion circuit based on this invention. FIG. 3 is a specific circuit diagram showing an embodiment of a differential amplifier circuit and a post-stage amplifier as a preamplifier unit used in the parallel A / D converter circuit according to the present invention. It is a block diagram which shows another Example of the parallel type A / D conversion circuit based on this invention. It is a block diagram which shows another one Example of the parallel type A / D conversion circuit based on this invention. FIG. 7 is a specific circuit diagram showing an embodiment of a differential amplifier circuit and a post-stage amplifier as a preamplifier unit used in the parallel A / D converter circuit shown in FIGS. 5 and 6. It is a circuit diagram which shows one Example of the comparator part of FIG. 1 is a block diagram showing an embodiment of a disk reproduction system for reading a signal recorded on a disk to which the present invention is applied. FIG. It is a block diagram which shows another one Example of the parallel type A / D conversion circuit based on this invention. It is a block diagram of a parallel type A / D converter examined prior to the present invention. It is a characteristic view for demonstrating operation | movement of the A / D converter of FIG. FIG. 12 is an equivalent circuit diagram of a part of the amplifier in the comparator of the A / D converter of FIG. 11. FIG. 12 is an equivalent circuit diagram of another part of the amplifier in the comparator of the A / D converter of FIG. 11. It is a conversion characteristic figure of the A / D converter of FIG. It is a block diagram of other parallel type A / D converters examined prior to the present invention. 1 is a block diagram showing an embodiment of a fully differential type of parallel A / D conversion circuits according to the present invention. FIG. FIG. 18 is a specific circuit diagram showing an embodiment of a four-input fully differential amplifier used in the parallel A / D conversion circuit of FIG. 17.

Explanation of symbols

PA ... preamplifier (preamplifier), DPA1, DPA2, DPA1a, 1b, DPA2a, 2b ... dummy preamplifier, Rave ... averaging resistor, Rave '... resistor, Q1-Q40 ... MOSFET.

Claims (15)

A resistance ladder for forming a plurality of reference voltages;
A plurality of voltage comparators each having the plurality of reference voltages input to one input terminal and an input analog signal commonly supplied to the other input terminal;
Each of the voltage comparators includes a differential amplifier circuit that receives signals from the one input terminal and the other input terminal,
The output terminals of the differential amplifier circuit adjacent to the reference voltage are connected to each other by an averaging resistor ladder,
The differential amplifier circuit that receives the highest reference voltage of the differential amplifier circuits at the one input terminal is a first differential amplifier circuit;
The differential amplifier circuit that receives the lowest reference voltage of the differential amplifier circuits at the one input terminal is a second differential amplifier circuit;
A first dummy amplifier circuit comprising a differential amplifier circuit whose characteristics are opposite to the input / output characteristics of the differential amplifier circuit; an output terminal of the second differential amplifier circuit; and an output terminal of the first dummy amplifier circuit; A first termination circuit comprising a first resistance element that is provided between the first resistance element and corrects input / output characteristics of the first differential amplifier circuit;
A second dummy amplifier circuit comprising a differential amplifier circuit whose characteristics are opposite to the input / output characteristics of the differential amplifier circuit; an output terminal of the first differential amplifier circuit; and an output terminal of the second dummy amplifier circuit; A second termination circuit comprising a second resistance element that is provided between the second resistance element and corrects input / output characteristics of the second differential amplifier circuit;
And an A / D conversion circuit formed on a single semiconductor substrate. In claim 1,
Each of the voltage comparators comprises an A / D conversion circuit comprising a latch circuit that determines and holds a logic 1 or a logic 0 based on a logic threshold voltage for the output signal of the differential amplifier circuit. . In claim 2,
The A / D conversion circuit, wherein the first and second dummy differential amplifier circuits receive a predetermined reference voltage corresponding to a midpoint voltage and the input analog signal, respectively, at differential input terminals. In claim 1,
A multi-bit thermometer code formed by the plurality of voltage comparators, and an encoder that forms a digital signal consisting of a plurality of bits,
The A / D converter circuit, wherein the first and second dummy differential amplifier circuits are composed of a differential amplifier circuit having the same circuit configuration as that of the differential amplifier circuit. In claim 4,
A space between the first dummy amplifier circuit of the first termination circuit and the second differential amplifier circuit is a differential amplifier circuit having the same circuit configuration as the differential amplifier circuit, and is the lowest in the input analog signal. A third dummy amplifier circuit for receiving a first reference voltage lower than the reference voltage is disposed;
The first resistance element is provided between the output terminal of the first dummy amplifier circuit and the output terminal of the third dummy amplifier circuit, and the output terminal of the third dummy amplifier circuit and the second differential amplifier are provided. Between the output terminal of the circuit, an averaging resistive element is provided,
The space between the second dummy amplifier circuit of the second termination circuit and the first differential amplifier circuit is a differential amplifier circuit having the same circuit configuration as the differential amplifier circuit, and is the highest of the input analog signal and the highest A fourth dummy amplifier circuit for receiving a second reference voltage higher than the reference voltage is disposed;
The second resistance element is provided between the output terminal of the second dummy amplifier circuit and the output terminal of the fourth dummy amplifier circuit, and the output terminal of the fourth dummy amplifier circuit and the first differential amplifier are provided. An A / D conversion circuit, wherein an averaging resistance element is provided between the output terminal of the circuit. In claim 4,
The voltage comparator includes a differential MOSFET having a gate connected to one input terminal and the other input terminal, and a pair of first, second, and third loads respectively provided at the drains of these differential MOSFETs. MOSFET and
Of the plurality of reference voltages, the pair of first MOSFETs of the i-th voltage comparator, in which the i-th reference voltage is input to the one input terminal, have a gate and drain cross-connected to each other in a latch form. The output signal of the (i + 1) th voltage comparator receiving the (i + 1) th reference voltage is input to the gates of the pair of second MOSFETs of the ith voltage comparator, and the ith voltage comparison is performed. The output signal of the (i-1) th voltage comparator that receives the (i-1) th reference voltage is input to the gates of the pair of third MOSFETs of the comparator crosswise,
An A / D conversion circuit characterized in that input / output characteristics of the third and fourth dummy amplifier circuits are made to be forward characteristics of the differential amplifier circuit. In claim 6,
To the differential amplifier circuit receiving a resistor ladder and the reference voltages to form the reference voltage to form an interpolation signal by said Abe les Jingu resistance,
A post-stage amplifier is provided corresponding to the interpolation signal to form a temperature code having a bit number twice as large as the number of reference voltages. In claim 6,
The differential MOSFET constituting the voltage comparator is provided with a differential amplifying MOSFET in parallel, and a reset MOSFET for short-circuiting both is provided between the differential MOSFETs. D conversion circuit. A resistance ladder for forming a plurality of reference voltages;
A plurality of voltage comparators each having the plurality of reference voltages input to one input terminal and an input analog signal commonly supplied to the other input terminal;
Each of the voltage comparators includes a differential amplifier circuit that receives signals from the one input terminal and the other input terminal,
The output terminals of the differential amplifier circuit adjacent to the reference voltage are connected to each other by an averaging resistor ladder,
The differential amplifier circuit that receives the highest reference voltage of the differential amplifier circuits at the one input terminal is a first differential amplifier circuit;
The differential amplifier circuit that receives the lowest reference voltage of the differential amplifier circuits at the one input terminal is a second differential amplifier circuit;
The first differential amplifier circuit outputs a first saturation voltage, and the second differential amplifier circuit outputs a voltage between the first saturation voltage and a second saturation voltage different from the first saturation voltage. And a first dummy amplifier circuit that outputs the first saturation voltage, and an output terminal of the second differential amplifier circuit and an output terminal of the first dummy amplifier circuit. A first termination circuit comprising a first resistance element that corrects input / output characteristics of the two differential amplifier circuits;
When the second differential amplifier circuit outputs the second saturation voltage, and the first differential amplifier circuit outputs a voltage between the first saturation voltage and the second saturation voltage, A second dummy amplifier circuit for outputting the second saturation voltage; and a first differential amplifier circuit provided between an output terminal of the first differential amplifier circuit and an output terminal of the second dummy amplifier circuit. A second termination circuit comprising a second resistance element for correcting the input / output characteristics of
And an A / D conversion circuit formed on a single semiconductor substrate. In claim 9,
The first dummy differential amplifier circuit is supplied with a predetermined fixed voltage between a non-inverting input and an inverting input to constantly output the first saturation voltage,
The second dummy differential amplifier circuit is a circuit in which a predetermined fixed voltage is supplied between a non-inverting input and an inverting input to constantly output the second saturation voltage. D conversion circuit. In claim 1,
An A / D conversion circuit characterized in that the polarity of the connection of the input section or output section of the first and second dummy differential amplifier circuits is opposite to that of the differential amplifier circuit. With a pickup,
An analog front end that converts the signal read by the pickup into an analog electrical signal;
Including an A / D conversion circuit that receives an analog electrical signal formed by the analog front end and converts it into a digital signal;
The A / D conversion circuit is
A resistance ladder for forming a plurality of reference voltages;
A plurality of voltage comparators each having the plurality of reference voltages input to one input terminal and an input analog signal commonly supplied to the other input terminal;
Each of the voltage comparators includes a differential amplifier circuit that receives signals from the one input terminal and the other input terminal,
The output terminals of the differential amplifier circuit adjacent to the reference voltage are connected to each other by an averaging resistor ladder,
The differential amplifier circuit that receives the highest reference voltage of the differential amplifier circuits at the one input terminal is a first differential amplifier circuit;
The differential amplifier circuit that receives the lowest reference voltage of the differential amplifier circuits at the one input terminal is a second differential amplifier circuit;
Provided between a first dummy amplifier circuit whose characteristics are opposite to the input / output characteristics of the differential amplifier circuit, an output terminal of the second differential amplifier circuit and an output terminal of the first dummy amplifier circuit; A first termination circuit comprising a first resistance element for correcting input / output characteristics of the first differential amplifier circuit;
A second dummy amplifier circuit whose characteristics are opposite to the input / output characteristics of the differential amplifier circuit; and an output terminal of the first differential amplifier circuit and an output terminal of the second dummy amplifier circuit, 2. A disk reproducing system comprising: a second termination circuit comprising a second resistance element for correcting input / output characteristics of the second differential amplifier circuit. In claim 12,
Each of the voltage comparators includes a latch circuit that determines and holds a logic 1 or a logic 0 based on a logic threshold voltage for the output signal of the differential amplifier circuit. In claim 13,
The disk reproducing system according to claim 1, wherein the first and second dummy differential amplifier circuits receive a predetermined reference voltage corresponding to a midpoint voltage and the input analog signal, respectively, at differential input terminals. In claim 12,
The A / D converter includes an encoder that forms a digital signal composed of a plurality of bits from a plurality of bits of a thermometer code formed by the plurality of voltage comparators;
A disc reproducing system comprising the first and second dummy differential amplifier circuits which are differential amplifier circuits having the same circuit configuration as the differential amplifier circuit.

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