JP2010034728A - Comparison operation amplification circuit, ad conversion circuit, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further reduce circuit scales and power consumption in a comparison operation amplification circuit and an AD conversion circuit. <P>SOLUTION: A sample and hold circuit 503, regarding a differential analog signal pair to be A/D converted, outputs output signal pairs in time division in a hold mode by using a plurality of sample and hold circuits and a signal selection circuit. In A/D conversion adopting no holding system, the comparison operation amplification circuit 501 outputs a plurality of amplified output signal pairs in time division by amplifying a difference between each output signal pair and each differential reference signal pair by each differential amplification circuit while switching a plurality of output signal pairs supplied in time division by the signal selection circuit so that a plurality of differential reference signal pairs may be processed in time division. A digital data acquisition part 6 acquires digital data by respectively binarizing the differences of the plurality of amplified output signal pairs supplied in time division. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a comparative operational amplifier circuit, an AD conversion circuit, and an electronic device. In more detail, a comparison operational amplifier circuit that compares and amplifies two types of signals, outputs them, an AD converter circuit that converts an analog signal into digital data, and a recording / reproducing apparatus that uses a mechanism of the AD converter circuit Regarding equipment.

  In various electronic devices such as a recording / reproducing apparatus, a comparison operational amplifier circuit that compares and amplifies two kinds of signals and outputs an AD converter circuit that converts an analog signal into digital data may be used.

  Various AD conversion methods have been considered from the viewpoint of circuit scale, processing speed (higher speed), resolution, and the like. As an example, a parallel type (flash type) AD conversion circuit is known. The parallel AD converter circuit obtains digital data corresponding to an analog input voltage by comparing the analog input voltage according to a plurality of reference voltages and a clock signal all at once.

  As a basic configuration, the parallel AD conversion circuit is configured by using power-of-two comparison operation amplification circuits with bit resolution. Therefore, when the number of bits increases, there is a problem that the circuit scale and power consumption become enormous.

  For example, in a parallel type AD converter circuit, an analog input signal and a plurality of reference potentials are compared using a comparison operational amplifier circuit. If the analog signal is lower than the reference potential, the difference is negative, and if the analog signal is higher, the differential is An analog differential signal (referred to as a zero-cross signal or an amplified output signal pair) that follows the input signal with a certain gain is generated. Then, the difference between the amplified output signal pair is binarized using a comparator and a latch circuit (positive / negative discrimination is performed), thereby converting the reference potential into a digital code corresponding to the resolution.

  The comparison operational amplifier circuit, the comparator, and the latch circuit increase in the number of elements of the circuit as the resolution becomes finer. In addition, as the voltage is reduced due to process miniaturization, the resolution becomes finer, and a high-precision comparison operation amplification circuit / comparator / latch circuit is required. Furthermore, the area and power increase in order to realize high-speed operation.

  In order to solve such a problem, various techniques have been proposed. As an example, AD conversion circuits described in Patent Documents 1 and 2 are known.

JP 2007-189519 A Japanese Patent Publication No. 07-061018

  The mechanism described in Patent Document 1 is a configuration that employs the folding method described in Patent Document 2. The analog signal is folded back multiple times by using a folding operation circuit, and the circuit scale and power consumption are reduced by the amount of folding. , Less than the basic configuration.

  However, in the comparative operational amplifier circuit and the parallel AD converter circuit, further improvements are desired in each aspect of circuit scale and power consumption. Similarly, in the folding AD conversion circuit, further improvements are desired in each aspect of circuit scale and power consumption.

  The present invention has been made in view of the above circumstances, and in a case where a folding method is not employed, at least one aspect of the circuit scale and power consumption of a parallel AD conversion circuit that can further reduce the circuit size and power consumption. The purpose is to provide a mechanism.

  The present invention has been made in view of the above circumstances, and in the case of adopting a folding method, the mechanism of a parallel AD conversion circuit capable of further reducing at least one of the circuit scale and power consumption. The purpose is to provide.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a mechanism of a comparative operational amplifier circuit capable of further reducing at least one of the circuit scale and power consumption.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a mechanism of an electronic device that can achieve further reduction in at least one aspect of circuit scale and power consumption.

  The AD converter circuit according to the present invention first temporarily holds the level of a differential analog signal pair to be AD converted at a different timing by a plurality of sample and hold circuits, and outputs one of the output signal pairs in each hold mode. Are selected by the first signal selection circuit. That is, the output signal pair in the hold mode is output in a time division manner for the differential analog signal pair by the plurality of sample hold circuits and the first signal selection circuit.

  And in the 1st mode which does not take a folding system, about the plurality of output signal pairs supplied by time division, while switching so that a plurality of differential reference signal pairs may be handled by time division by the 2nd signal selection circuit. The comparison operation amplification unit amplifies the difference between each output signal pair and each differential reference signal pair by each differential amplifier circuit, thereby outputting a plurality of amplified output signal pairs in a time division manner. In response to this, the digital data acquisition unit acquires the digital data by binarizing the difference between the plurality of amplified output signal pairs supplied in time division.

  Further, in the second aspect employing the folding method, the folding operation circuit shifts the phase by a predetermined amount based on each amplified output signal pair output in a time division manner from the comparison operation amplification unit for a plurality of differential reference signal pairs. The P-phase folded differential signal pair is output in a time-sharing manner. In the sample-and-hold circuit, the P-phase folded differential signal pair is distributed by the fourth signal selection circuit, and the P-phase folded differential signal pair distributed by the fourth signal selection circuit is held. Hold in circuit. In response, the digital data acquisition unit binarizes the difference between the P-phase folded differential signal pairs, and converts the differential analog signal pair into digital data based on each binarized data.

  In the folding method, processing divided into upper bits and lower bits may be further performed. In such a third aspect, it is preferable to apply the second aspect described above for the processing of the lower bits.

  Further, in the second and third modes employing the folding method, there are cases where it is combined with the interpolation method. In this case, in the second aspect described above, the differential signal pair having the P × Q phase folded is further interpolated between the differential signal pair having the P phase folded after the sample hold circuit. An interpolation unit for generation is provided. Then, the difference between the P × Q phase folded differential signal pairs is binarized, and the differential analog signal pair is converted into digital data based on each binarized data.

  The comparison operational amplification circuit according to the present invention switches the differential analog signal pair and the multiple differential reference signal pairs in the comparative operational amplification unit while switching the multiple differential reference signal pairs to be handled in a time division manner by the signal selection circuit. Are amplified by each differential amplifier circuit, so that a plurality of amplified output signal pairs are output in a time division manner.

  The electronic apparatus according to the present invention has a mechanism similar to that of the above-described AD conversion circuit according to the present invention.

  The comparison operational amplifier circuit according to the present invention can be applied not only to an AD converter circuit but also to a general electronic device.

  In the AD converter circuit, the comparative operational amplifier circuit, and the electronic device according to the present invention, the signal selection circuit switches the differential reference signal pair to be handled in a time division manner, and the differential analog signal pair or the amplified output signal pair A similar configuration is provided in that the differential reference signal pair is comparatively amplified by a common comparison operational amplifier circuit.

  Since the differential analog signal pair or the amplified output signal pair and the plurality of differential reference signal pairs are compared and amplified by a common comparison operation amplifier circuit, depending on the configuration of the signal selection circuit and the comparison operation amplifier circuit, The overall circuit scale and power consumption can be reduced as compared with the case where a comparison operational amplifier circuit is provided for each differential reference signal pair.

  For example, when the present invention is not applied, for each of a plurality of differential reference signal pairs, a plurality of comparison operational amplifier circuits for comparing and amplifying the differential analog signal pair or the amplified output signal pair and each differential reference signal pair are provided. Are provided for each of the differential reference signal pairs. Since the plurality of comparison operation amplifier circuits operate simultaneously in parallel, the power consumption is equivalent to the plurality of comparison operation amplifier circuits operating in parallel.

  On the other hand, in the present invention, the differential selection of the differential analog signal pair or the amplified output signal pair and the plurality of differential reference signal pairs is compared with each other while the signal selection circuit handles the plurality of differential reference signal pairs in a time division manner. Comparative amplification is performed by an amplifier circuit. The power consumption of the added signal selection circuit may be considered to be small, and comparison amplification is performed in a time-sharing manner, so that the power consumption is that of one comparative operational amplifier circuit that is commonly used. Power consumption is reduced compared to when not.

  In addition, the circuit scale of the added signal selection circuit can be reduced by using the signal selection circuit so that all or part of the comparison operation amplification circuit can be used in common. If it is less than minutes, the circuit scale is reduced as compared with the case where the present invention is not applied. From this point of view, it is preferable that the number of elements is as small as possible as the configuration of the signal selection circuit that time-divides a plurality of differential reference signal pairs, and that a transistor switch that uses one transistor for each differential reference signal is used. Good. This transistor switch applies not only to a signal selection circuit that time-divides a plurality of differential reference signal pairs, but also to other signal selection circuits. This is to prevent the circuit scale from being increased as much as possible.

  According to the present invention, the circuit scale and power consumption can be reduced compared to the case where the present invention is not adopted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. When distinguishing each functional element according to the embodiment, an uppercase English reference such as A, B,... Is added and described, and when not particularly described, this reference is omitted. To describe. The same applies to the drawings. Hereinafter, an n-channel MOS transistor is referred to as an nMOS, and a p-channel MOS transistor is referred to as a pMOS. For a pair of various signals, the code name of each signal is followed by a “P” or “N” code in lower case.

<Comparison operational amplifier circuit: first example>
FIG. 1 is a diagram illustrating a comparative operational amplifier circuit according to a first example of this embodiment. Here, FIG. 1 (1) is a diagram showing an overall outline of the first comparative operational amplifier circuit 1A, and FIG. 1 (2) is a timing for explaining the operation of the first comparative operational amplifier circuit 1A. It is a chart.

  The comparative operational amplifier circuit 1A of the first example is an example of a comparative operational amplifier that includes a first differential amplifier circuit 110A having a differential configuration, a second differential amplifier circuit 120A having a differential configuration, and a load circuit 130. The comparison operational amplifier circuit 100A (preamplifier, PreAMP) and the signal selection circuit 140 (second signal selection circuit) are combined.

  The comparative operational amplifier circuit 100A amplifies a potential difference between a differential analog input signal (a pair of analog input signals VIP and VIN) and a differential reference voltage (a pair of reference potentials VRP and VRN). The comparison operation amplifier circuit 100A performs a comparison operation between the reference potential REFA (reference potentials VRPA and VRNA) and the analog input differential voltage signals (analog input signals VIP and VIN), and performs differential amplification output signals VOP and VON (summary). Output zero cross signal VO).

  Differential analog input signal (analog input signal VIP, VIN pair) between differential analog input signal (analog input signal VIP, VIN pair) and differential reference voltage (reference potential VRP, VRN pair) The common voltage (midpoint potential) is set to the same voltage difference point, that is, (VRP + VRN) / 2 = (VIP + VIN) / 2. With this setting, the voltage difference between the analog input signal VIP and the reference potential VRP and the voltage difference between the analog input signal VIN and the reference potential VRN are always equal.

  The first differential amplifier circuit 110A of the first example includes an nMOS 112 and an nMOS 114 that form a first differential pair, and an nMOS 116 that functions as a current source that supplies a predetermined operating current to the differential TR pair (nMOS 112, 114). Have The second differential amplifier circuit 120A of the first example includes an nMOS 122 and an nMOS 124 that form a second differential pair, and an nMOS 126 that functions as a current source that supplies a predetermined operating current to the differential TR pair (nMOSs 122 and 124). Have The nMOSs 112 and 122 are analog signal input transistors to which an analog input signal AIN (analog input signals VIP and VIN) is input. The nMOSs 114 and 124 are reference signal input transistors to which a reference potential REF (reference potentials VRP and VRN) is input.

  The nMOS 116 has a source connected to the negative power supply Vss and a drain connected to the sources of the nMOSs 112 and 114 in common. The nMOS 126 has a source connected to the negative power supply Vss and a drain connected to the sources of the nMOSs 122 and 124 in common. A bias voltage VIB is commonly supplied to the gates of the nMOSs 116 and 126. The analog input signal VIP is supplied to the gate of the nMOS 112, and the reference potential VRP from the signal selection circuit 140 is supplied to the gate of the nMOS 114. An analog input signal VIN having a differential relationship with the analog input signal VIP is supplied to the gate of the nMOS 122, and a reference potential VRN from the signal selection circuit 140 is supplied to the gate of the nMOS 124.

  The load circuit 130 includes two resistance elements 132 and 134 serving as loads. The resistance element 132 has one terminal connected to the power supply Vdd, the other terminal connected in common to the drains of the nMOSs 112 and 124, and the connection point serving as the inverting output terminal of the comparison operational amplifier circuit 1A. Is output. The resistance element 134 has one terminal connected to the power supply Vdd, the other terminal connected in common to the drains of the nMOSs 114 and 122, and the connection point serving as the non-inverting output terminal of the comparison operational amplifier circuit 1A. Is output. Here, a passive load using a resistance element is used as a load element, but an active load using a transistor as a load such as a pMOS current mirror circuit may be used.

  The comparative operational amplifier circuit 1A of the first example has a control input terminal side to which reference potentials VRP and VRN are input to nMOSs 114 and 124, which are reference signal input transistors, for each of the differential amplifier circuits 110A and 120A ( That is, the signal selection circuit 140 is arranged on the gate side. In this case, unlike the comparative operational amplifier circuit 1B of the second example which will be described later, one nMOS 114, 124 is sufficient.

  The signal selection circuit 140 has two systems of 2-input / 1-output type selectors (multiplexers). For example, a selector 142 is disposed for the first differential amplifier circuit 110A, and a selector 144 is disposed for the second differential amplifier circuit 120A. The selector 142 has switches 142_A and 142_B, and the selector 144 has switches 144_A and 144_B.

  One reference potential VRPA of the reference potential REFA is supplied to the input side of the switch 142_A, and one reference potential VRPB of the reference potential REFB is supplied to the input side of the switch 142_B. The outputs of the switches 142_A and 142_B are connected in common, and one of the reference potentials VRPA and VRPB selected by the selector 142 is supplied to the gate of the nMOS 114 as the reference potential VRP. The other reference potential VRNA of the reference potential REFA is supplied to the input side of the switch 144_A, and the other reference potential VRNB of the reference potential REFB is supplied to the input side of the switch 144_B. The outputs of the switches 144_A and 144_B are connected in common, and one of the reference potentials VRNA and VRNB selected by the selector 144 is supplied to the gate of the nMOS 124 as the reference potential VRN.

  Each of the switches 142_A, 142_B, 144_A, and 144_B is, for example, a transistor switch that includes only one of pMOS and nMOS. As a signal selection circuit, for example, a circuit in which a pair of complementary switches (transfer gate, transmission gate) having a CMOS configuration in which pMOS and nMOS are connected in parallel in a complementary manner is arranged between input and output is known. In view of making the circuit configuration compact, it is composed of one transistor. When a pMOS is used, an active L control signal is input to its gate, and when an nMOS is used, an active H control signal is input to its gate to turn on the transistor.

  Since the selector 142 selects one of the reference potentials VRPA and VRPB by the switches 142_A and 142_B, the gates of the switches 142_A and 142_B are supplied with clock signals ΦPA and xΦPA having a complementary relationship as selection control signals. . The selector 144 is supplied with the complementary clock signals ΦPA and xΦPA to the gates of the switches 144_A and 144_B in order to select one of the reference potentials VRNA and VRNB by the switches 144_A and 144_B. The clock signals ΦPA and xΦPA are collectively referred to as a clock signal CKPA for the comparison operational amplifier circuit 1. Here, each of the switches 142_A, 142_B, 144_A, and 144_B is an nMOS, and the clock signal ΦPA is supplied to the gates of the switches 142_A and 144_A, and the clock signal xΦPA is supplied to the gates of the switches 142_B and 144_B.

  With such a configuration, the comparison operational amplifier circuit 1A of the first example has an analog input differential voltage signal (analog input signals VIP and VIN) and a plurality of different reference differential voltages (reference potentials VRPA, VRNA and reference potential VRPB, VRNB) is input, and the difference voltage between one reference differential voltage (reference potential VRPA, VRNA or reference potential VRPB, VRNB) selected by the signal selection circuit 140 and the analog input differential voltage signal is compared and amplified 100A. Are amplified and output, and the respective amplified outputs are serially (time-division) output as differential amplified output signals VOP and VON (see FIG. 1 (2)).

  For example, when the clock signal ΦPA is at the H level and the clock signal xΦPA is at the L level, the switch 142_A and the switch 144_A are turned on and the switch 142_B and the switch 144_B are turned off, so that the reference operational amplifier circuit 100A has the reference potential REFA (reference potential). VRPA, VRNA) is input. The comparison operation amplifier circuit 100A performs a comparison operation between the reference potential REFA (reference potentials VRPA and VRNA) and the analog input differential voltage signals (analog input signals VIP and VIN), and outputs a zero cross signal VOA. On the other hand, when the clock signal ΦPA is at the L level and the clock signal xΦPA is at the H level, the switch 142_A and the switch 144_A are turned off and the switch 142_B and the switch 144_B are turned on, so that the reference operational amplifier circuit 100A has the reference potential REFB (reference potential). VRPB, VRNB) is input. The comparison operation amplifier circuit 100A performs a comparison operation between the reference potential REFB (reference potentials VRPB and VRNB) and the analog input differential voltage signals (analog input signals VIP and VIN), and outputs a zero cross signal VOB.

  As a result, the zero cross signals VOA and VOB for the two reference potentials REFA and REFB are serially output by one comparison operational amplifier circuit 100A. The comparative operational amplifier circuit 1A uses the comparative operational amplifier circuit 100A twice in one cycle, that is, time-division of two systems of reference potentials to the gates of the reference signal input transistors (nMOSs 114 and 124) of the differential amplifier circuits 110 and 120. It will be supplied by.

  The difference in the number of elements (number of transistors = TR number, number of load elements = R number) and area / power depending on whether or not the comparative operational amplifier circuit 1A of the first example is applied will be considered. When the comparative operational amplifier circuit 1A of the first example is not applied, the comparative operational amplifier circuit 100A (TR number = 6, R number = 2) is used for each of the two systems of reference potentials REFA and REFB. . Therefore, there are 12 transistors (= 6 × 2 systems) and 4 load elements (= 2 × 2 systems) as load elements. On the other hand, the comparative operational amplifier circuit 1A of the first example is composed of one comparative operational amplifier circuit 100A (TR number = 6, R number = 2) and one signal selection circuit 140 (TR number = 4). The number of transistors is 10 (= 6 + 4), the number of load elements is two resistance elements, the number of transistors is reduced by 2, the number of resistance elements as load elements is reduced, and the circuit area is reduced.

  Further, when the comparison operational amplifier circuit 1A of the first example is not applied, the comparison operational amplifier circuit 100A for the two systems of the reference potentials REFA and REFB is in a two-system parallel process that always operates. Since the comparative operational amplifier circuit 1A in the example is a time-sharing process that operates by switching between the two reference potentials REFA and REFB, the power consumption is reduced to approximately ½ or less. Here, “substantially ½ or less” is considered in consideration of power consumption in the signal selection circuit 140 (which is very small).

  As described above, the comparative operational amplifier circuit 1A of the first example employs a mechanism for reducing the circuit area and power consumption by sharing one comparative operational amplifier circuit 100 for two reference potentials REF. By reducing the number of elements (number of transistors) of the signal selection circuit 140 newly added for this reduction as much as possible, the reduction effect can be sufficiently obtained. In other words, in the present embodiment, the signal selection circuit 140 is more than the reduction of the comparative operational amplifier circuit 100 so that the effect of reducing the circuit area is not insufficient or the circuit scale is not increased. Note that the circuit size is reduced for the additional portion.

  In this example, since the signal selection circuit 140 includes 2-input-1 output-type selectors 142 and 144, the zero-cross signal for the reference potentials REFA and REFB can be obtained by switching the two-system reference potentials REFA and REFB in a time-sharing manner. However, it may be configured to switch three or more reference potentials in a time-sharing manner. In this case, an N input-1 output type selector is used, and a control signal for the gates of the transistors constituting the selector is set accordingly, so that zero-cross signals for N reference potentials are serially output.

  In the comparative operational amplifier circuit 1A of the first example, the reference potentials VRP and VRN applied to the gates of the transistors of the first differential amplifier circuits 110A and 120A constituting the comparative operational amplifier circuit 100A are switched. There is an advantage that the circuit scale is smaller than that of the circuit, but there may be a problem with the settling of the reference potentials VRP and VRN. That is, since the reference potentials VRP and VRN are switched between different reference potentials VRPA and VRNA and reference potentials VRPB and VRNB, it is necessary to perform comparison operation after settling (becomes stable) at the time of switching. The time for the comparison operation of the operational amplifier circuit 100A is shortened.

  In order to reduce power consumption, especially when using a reference potential generation circuit (resistance ladder circuit) with a general resistance division as a circuit for setting multiple reference voltages (reference potentials VRPA, VRNA and reference potentials VRPB, VRNB) Increase the resistance value. Therefore, since the time constant of the output node of the resistance ladder circuit becomes large, the settling time when switching between the reference potentials VRP and VRN becomes long. A comparative operational amplifier circuit 1B of a second example to be described later takes measures against this point.

<Comparison operational amplifier circuit: second example>
FIG. 2 is a diagram for explaining a comparative operational amplifier circuit of the second example of the present embodiment. Here, FIG. 2 (1) is a diagram showing an overview of the second comparative operational amplifier circuit 1B, and FIG. 2 (2) is a timing for explaining the operation of the second comparative operational amplifier circuit 1B. It is a chart. The comparative operational amplifier circuit 1B of the second example has a configuration in which nMOSs 114 and 124, which are reference signal input transistors, are individually provided for two systems of reference potentials REFA and REFB for each of the differential amplifier circuits 110B and 120B. For example, the first differential amplifier circuit 110B includes nMOSs 114_A and 114_B, and the second differential amplifier circuit 120B includes nMOSs 124_A and 124_B. The nMOS 112 and the nMOS 114_A, the nMOS 112 and the nMOS 114_B each constitute a differential pair, and the nMOS 122 and the nMOS 124_A, and the nMOS 122 and the nMOS 124_B each constitute a differential pair.

  Further, the signal selection circuit 140 is configured to enter the differential amplifier circuits 110B and 120B. In particular, when the signal selection circuit 140 is configured to enter the differential amplifier circuits 110B and 120B, a configuration in which the signal selection circuit 140 is arranged on the load side (that is, the drain side) with respect to the nMOSs 114 and 124, and the nMOSs 116 and 126 that are current sources. Any of the configurations arranged on the side (that is, the source side) can be adopted, but the latter source side is adopted here. That is, the comparison operational amplifier circuit 100B is provided with a plurality of reference signal input transistors, and a switch is provided on the source side of the transistors.

  Specifically, in the signal selection circuit 140, a selector 142 is disposed for the first differential amplifier circuit 110B, and a selector 144 is disposed for the second differential amplifier circuit 120B. The configurations of the selectors 142 and 144 are the same as those in the first example, but the connection mode of the input / output terminals is different from that in the first example.

  The input side of the switch 142_A is connected to the source of the nMOS 114_A, and the input side of the switch 142_B is connected to the source of the nMOS 114_B. The output sides of the switches 142_A and 142_B are connected in common with the source of the nMOS 112 and are connected to the drain of the nMOS 116. The input side of the switch 144_A is connected to the source of the nMOS 124_A, and the input side of the switch 144_B is connected to the source of the nMOS 124_B. The output sides of the switches 144_A and 144_B are connected in common with the source of the nMOS 122 and to the drain of the nMOS 126.

  The selector 142 selects one of the nMOSs 114_A and 114_B by the switches 142_A and 142_B, and the selector 144 selects one of the nMOSs 124_A and 124_B by the switches 144_A and 144_B. Each gate is supplied with clock signals ΦPA and xΦPA having a complementary relationship as selection control signals. For example, the clock signal ΦPA is supplied to the gates of the switches 142_A and 144_A, and the clock signal xΦPA is supplied to the gates of the switches 142_B and 144_B.

  With such a configuration, the comparative operational amplifier circuit 1B of the second example also has an analog input differential voltage signal (analog input signals VIP and VIN) and a plurality of different reference differential voltages (reference potentials VRPA, VRNA and reference potential VRPB, VRNB) is input, and the difference voltage between one reference differential voltage (reference potential VRPA, VRNA or reference potential VRPB, VRNB) selected by the signal selection circuit 140 and the analog input differential voltage signal is compared and amplified 100A. The amplified outputs are serially output as differential amplified output signals VOP and VON (see FIG. 2 (2)).

  In the first example, the reference differential voltage is directly selected by the signal selection circuit 140, whereas in the second example, the operating current paths of the nMOS 114_A and nMOS 114_B and the operating current paths of the nMOS 124_A and nMOS 124_B are time-shared. Is different in that the reference differential voltage is indirectly selected by the signal selection circuit 140 via the reference signal input transistor, but the same function is provided in that the reference potential REF is switched. Have.

  For example, when the clock signal ΦPA is at the H level and the clock signal xΦPA is at the L level, the switches 142_A and 144_A are turned on and the switches 142_B and 144_B are turned off, so that the reference potential REFA (reference potentials VRPA and VRNA) is input. NMOSs 114_A and 124_A on the other side pass current, and nMOSs 114_B and 124_B on the side to which the reference potential REFB (reference potentials VRPB and VRNB) is input do not pass current. For this reason, the comparison operation amplifier circuit 100B performs a comparison operation between the reference potential REFA (reference potential VRPA, VRNA) and the analog input differential voltage signals (analog input signals VIP, VIN), and zero-crosses as the amplified output signals VOP, VON. The signal (VOA) is output.

  On the other hand, when the clock signal ΦPA is at the L level and the clock signal xΦPA is at the H level, the switches 142_A and 144_A are turned off and the switches 142_B and 144_B are turned on, so that the reference potential REFB (reference potentials VRPB and VRNB) is input. The nMOSs 114_B and 124_B on the other side pass current, and the nMOSs 114_A and 124_A on the side to which the reference potential REFA (reference potentials VRPA and VRNA) is input do not pass current. For this reason, the comparison operation amplifier circuit 100B performs a comparison operation between the reference potential REFB (reference potential VRPB, VRNB) and the analog input differential voltage signals (analog input signals VIP, VIN), and zero-crosses as the amplified output signals VOP, VON. Outputs the signal (VOB).

  As a result, the zero cross signal for the two reference potentials REFA and REFB is serially output by one comparison operational amplifier circuit 100B. This is the same as in the first example in that the comparative operational amplifier circuit 100B is used twice in one cycle.

  In this example, since the signal selection circuit 140 has a 2-input-1 output-type selector, a zero-cross signal for two reference potentials REFA and REFB is serially output. A configuration having an output type selector is set, and a control signal for the gates of the transistors constituting the selector is set accordingly, so that zero-cross signals for N system reference potentials are serially output.

  Since the reference signal input transistors nMOSs 114 and 124 are individually provided for the two reference potentials REFA and REFB, even when the reference potentials VRP and VRN are switched, the reference potential applied to the gate of the reference signal input transistor VRP and VRN are unchanged, and the problem of settling of the reference potential during switching is solved. The comparison operation amplifier circuit 1B does not need to consider the settling time of the reference potential in the comparison operation in the comparison operation amplifier circuit 100B, and the comparison operation output between the two systems of reference potential and the input signal is output by one comparison operation amplifier circuit 100. Output serially.

  This also applies to the case where the signal selection circuit 140 is arranged on the load side (that is, the drain side) with respect to the nMOSs 114 and 124. That is, the same effect as that of the comparative operational amplifier circuit 1B can be obtained by providing a plurality of reference signal input transistors in the comparative operational amplifier circuit 100B and providing a switch on the drain side of the transistors.

  Consider the number of elements (number of transistors = TR number, number of load elements = R number) and the difference in area / power depending on whether or not the comparative operational amplifier circuit 1B of the second example is applied. When the comparative operational amplifier circuit 1B of the second example is not applied, the comparative operational amplifier circuit 100A (TR number = 6, R number = 2) is used for each of the two systems of reference potentials REFA and REFB. . Therefore, there are 12 transistors (= 6 × 2 systems) and 4 load elements (= 2 × 2 systems) as load elements. On the other hand, the comparative operational amplifier circuit 1B of the second example has one comparative operational amplifier circuit 100B (except for the signal selection circuit 140; TR number = 8, R number = 2) and one signal selection circuit 140 (TR number). = 4), the number of transistors is 12 (= 8 + 4), the number of load elements is 2, and the number of transistors is not reduced, but the number of resistance elements that are load elements is reduced, Contributes to reduction of circuit area.

  Further, when the comparative operational amplifier circuit 1B of the second example is not applied, the two comparative operational amplifier circuits 100A for the reference potentials REFA and REFB for the two systems are always operated in parallel, whereas Since the two comparative operational amplifier circuits 1B are time-sharing processes that operate by switching between the two reference potentials REFA and REFB, the power consumption is reduced to approximately ½ or less. Here, “substantially ½ or less” is considered in consideration of power consumption in the signal selection circuit 140 (which is very small).

<Sample hold circuit>
FIG. 3 is a diagram illustrating the sample and hold circuit of the present embodiment. Here, FIG. 3A is a diagram showing an overall outline of the sample-and-hold circuit 3, and FIG. 3B is a timing chart for explaining the operation of the sample-and-hold circuit 3.

  The sample and hold circuit 3 of the present embodiment is configured by a combination of two sample and hold circuits 310_1 and 310_2 and a signal selection circuit 340 (first signal selection circuit). Each of the sample and hold circuits 310_1 and 310_2 is a circuit having a sample and hold function as described in FIG. 1 of Japanese Patent No. 3938727, for example. An analog input signal AIN is input to the input terminals of the sample hold circuits 310_1 and 310_2 in common.

  The signal selection circuit 340 includes a 2-input-1 output type selector 342 (signal selection circuit). The selector 342 includes switches 342_1 and 342_2. The input side of the switch 342_1 is connected to the output of the sample hold circuit 310_1, and the input side of the switch 342_2 is connected to the output of the sample hold circuit 310_2. The selector 342 outputs the output signal AOUT by switching the outputs of the sample and hold circuits 310_1 and 310_2 in a time division manner.

  Each of the switches 342_1 and 342_2 is a transistor switch using only one of pMOS and nMOS as an example in order to prevent the circuit scale from increasing as much as possible. Here, it is assumed that the nMOS is turned on when the H level is input to the gate which is the control input terminal.

  Clock signals ΦSH and xΦSH having a complementary relationship are supplied to the control input terminals of the sample hold circuits 310_1 and 310_2 and the switches 342_1 and 342_2. The clock signals ΦSH and xΦSH are collectively referred to as a clock signal CKSH for the sample hold circuit 3. For example, the clock signal xΦSH is supplied to the gate of the switch 342_1, and the clock signal ΦSH is supplied to the gate of the switch 342_2. A clock signal ΦSH is supplied to the control input terminal of the sample hold circuit 310_1, and a clock signal xΦSH is supplied to the control input terminal of the sample hold circuit 310_2.

  With such a configuration, the sample and hold circuit 3 of the present embodiment includes the signal selection circuit 340 that switches the outputs of the plurality of sample and hold circuits (sample and hold circuits 310_1 and 310_2), and during one cycle of the clock signals ΦSH and xΦSH. Therefore, a plurality of hold outputs are always performed (see FIG. 3 (2)). That is, a sample-and-hold circuit that can perform hold output even during the sample period of the conventional sample-and-hold circuit is configured.

  For example, when the clock signal ΦSH is at the H level and the clock signal xΦSH is at the L level, the sample and hold circuit 310_1 enters the sample mode and outputs a signal following the analog input signal AIN, and the sample and hold circuit 310_2 enters the hold mode and the clock signal ΦSH is Holds and outputs the analog input signal AIN immediately before it becomes H level. At this time, the output destination switch 342_1 of the sample hold circuit 310_1 is turned off, and the output destination switch 342_2 of the sample hold circuit 310_2 is turned on. Therefore, the output signal Aout of the sample hold circuit 3 becomes an output in the hold mode of the sample hold circuit 310_2.

  On the other hand, when the clock signal ΦSH is at the L level and the clock signal xΦSH is at the H level, the sample hold circuit 310_2 enters the sample mode and outputs a signal following the analog input signal AIN, and the sample hold circuit 310_1 enters the hold mode and the clock signal ΦSH is Holds and outputs the analog input signal AIN immediately before it becomes H level. At this time, the output destination switch 342_2 of the sample hold circuit 310_2 is turned off, and the output destination switch 342_1 of the sample hold circuit 310_1 is turned on. Therefore, the output signal Aout of the sample hold circuit 3 becomes an output in the hold mode of the sample hold circuit 310_1.

  Therefore, by using the sample hold circuit 3 of the present embodiment, a held input signal is always output. This is different from the case where there is a period in which a signal following the analog input signal AIN is output in the case of the configuration of either one of the sample hold circuits 310_1 and 310_2 to which the sample hold circuit 3 of the present embodiment is not applied. .

  In this example, since the signal selection circuit 340 includes the 2-input-1 output-type selector 342, two held input signals are output in a time-division manner in one cycle. The held input signal may be switched in a time division manner. In this case, an N input-1 output type selector is used, and a control signal for the gate of the transistor constituting the selector is set accordingly, so that N held input signals in one cycle are time-divisionally divided. Is output. For example, when the first sample and hold circuit 310_1 is in the sample mode, the output in the hold mode of the nth sample and hold circuit 310_n is the output signal AOUT, and thereafter the nth when the nth sample and hold circuit 310_n is in the sample mode. The output in the hold mode of the -1st sample hold circuit 310_n-1 becomes the output signal AOUT, and it may be repeated in the following order.

  Consider the difference in the number of elements (number of transistors = number of TRs), area, and power depending on whether or not the sample hold circuit 3 of this embodiment is applied. When the sample hold circuit 3 is not applied, one of the sample hold circuits 310_1 and 310_2 is provided, whereas the sample hold circuit 3 includes two sample hold circuits 310_1 and 310_2 and a signal selection circuit 340. Is disadvantageous in terms of area and power. However, the output signal has an advantage that an output in the hold mode of any of the sample hold circuits 310_1 and 310_2 can always be obtained. Since the output in the hold mode is always obtained, when the AD converter circuit is configured in combination with the comparative operational amplifier circuit 1 of the present embodiment, the number of comparative operational amplifier circuits 100 serving as loads is reduced and the load capacity is reduced. Therefore, the load driving capability (that is, driving current) may be small, which contributes to reduction of power consumption and operation speed. This point will be described in detail in the next AD conversion circuit item.

<AD conversion circuit: first example>
4 to 4C are diagrams for explaining the AD converter circuit of the first example of the present embodiment. Here, FIG. 4 is a diagram showing an overall outline of the AD conversion circuit 5A of the first example. FIG. 4A is a diagram illustrating an overall outline of an AD conversion circuit 5X of a first comparative example to which the AD conversion circuit 5A of the first example is not applied. FIG. 4B is a timing chart for explaining the operation of the AD converter circuit 5A of the first example. FIG. 4C is a timing chart for explaining the operation of the AD conversion circuit 5X of the first comparative example.

  The parallel AD converter circuit is capable of high-speed processing, but a comparison operation amplification circuit and a master comparator latch corresponding to the resolution are required. Therefore, when the resolution is increased, the circuit scale increases exponentially, As a result, power consumption and chip size increase. Furthermore, since the offset between each circuit becomes serious if high resolution is to be realized, its application range tends to be limited. Therefore, in this embodiment, the circuit scale and power consumption are reduced by devising the analog preprocessing of the input stage of the AD converter circuit using the mechanism of the comparison operational amplifier circuit 1 and the sample hold circuit 3 of the present embodiment. Think about what to do.

  The AD converter circuit 5A of the first example includes a comparison operation amplification circuit 501 (comparison operation amplification unit), a reference potential generation circuit 502, a sample hold circuit 503 (sample hold unit), a latch circuit 508A, and a decode circuit 509. It consists of a combination. The latch circuit 508A and the decode circuit 509 digitalize the difference between a plurality of amplified output signal pairs (zero cross signal VO: amplified output signals VOP, VON) output from the comparison operational amplifier circuit 501 in a time division manner. A digital data acquisition unit 6 for acquiring data is configured. Signal lines related to analog circuits (comparison operational amplifier circuit 501 and sample hold circuit 503) are assumed to be differential notation. In the figure, a configuration corresponding to 4 bits is shown. This configuration is not limited to 4 bits, and can be similarly constructed with 5 bits or more.

  The reference potential generation circuit 502 corresponds to 4 bits, and generates 16 systems of reference potentials REF1 to REF16 (a pair of reference potentials VRP and VRN, respectively). The reference potential generation circuit 502 for generating 16 systems of reference potentials REF1 to REF16 uses a general resistance ladder circuit by resistance division. At this time, the high voltage Vh and the low voltage Vl are equally divided, and the differential reference voltage (a pair of reference potentials VRP and VRN) is obtained by dividing the intermediate voltage (Vh + Vl) / 2 (= common voltage of the input signal). It is preferable to set the same voltage difference as a reference, that is, set so that (VRP + VRN) / 2 = (VIP + VIN) / 2. With this setting, the voltage difference between the analog input signal VIP and the reference potential VRP and the voltage difference between the analog input signal VIN and the reference potential VRN are equal in any of the 16 reference potentials REF1 to REF16.

  The comparison operational amplifier circuit 501 compares the two reference potentials and the input signal for every two systems with respect to the 16 systems of the reference potential REF, and outputs the comparison result serially (1_1 to 1 in the figure). 1_8).

  The latch circuit 508A has a latch 580 (580_1 to 580_8 in the figure) for each comparison operational amplifier circuit 1. The latch 580 binarizes the difference between the amplified output signal pair output from the comparison operational amplifier circuit 1. The latch 580 is also referred to as a master comparator latch, and is a comparator (comparator) that performs comparison processing based on the differential output (zero cross signal) of the comparison operational amplifier circuit 1 (see FIG. 6A (2) described later). It has a D-type flip-flop. The comparator binarizes the difference between the amplified output signal pairs output from the comparison operational amplifier circuit 1, that is, performs positive / negative discrimination based on the zero cross signal VO. The D-type flip-flop generates a thermometer code D by holding the result of positive / negative discrimination by the comparator based on the clock signal CKLT, and outputs it to the decoding circuit 509 at the subsequent stage. The decode circuit 509 combines the thermometer codes DO and DE related to the two reference potentials and outputs a 4-bit digital code DOUT.

  The sample-and-hold circuit 503 uses the sample-and-hold circuit 3 of this embodiment that outputs two held input signals in one cycle for the analog input signals VIP and VIN, respectively. It is used as an analog input signal (VIP, VIN) of each comparison operation amplification circuit 1_1 to 1_8 of the amplification circuit 501.

  As a whole, when the number of inputs corresponding to the selector 142 is N (2 in this example), the comparison operational amplifier circuit 1 is used N times in one cycle, and the output of the comparative operational amplifier circuit 1 is latched by the latch 580. Has the ability to hold in a divided manner.

  As shown in FIG. 4A, in the AD conversion circuit 5X of the comparative example (ordinary flash method) to which the AD conversion circuit 5A of the first example is not applied, a signal (sample output) that follows the analog input signal AIN is sent to the sample hold circuit 503X. ) Is used, a normal sample and hold circuit 310 is used. The comparison operational amplifier circuit 501X includes a normal comparison operational amplifier circuit 100 that compares the reference potential with the input signal and outputs a comparison result for each of the 16 reference potentials REF. The latch circuit 508X includes a latch 580 (580_1 to 580_16 in the drawing) for each of the 16 systems of reference operational amplifiers 100 for reference potential.

  Comparing the AD converter circuit 5X of the first comparative example and the AD converter circuit 5A of the first example, by inputting two reference potentials to the comparative operational amplifier circuit 1, the number of comparative operational amplifier circuits 100 and latches 580 is reduced by half. To do. As can be understood from the above description of the comparative operational amplifier circuit 1, the signal selection circuit 140 is required to halve the comparative operational amplifier circuit 100. However, the circuit scale of the comparative operational amplifier circuit 501 and the latch circuit 508A is small. Clearly it will be reduced. In addition, since time-division processing is performed for the two system reference potentials, the power consumption is approximately halved.

  As can be understood from the above description of the sample and hold circuit 3, the sample and hold circuit 503 requires two sample and hold circuits 310 for each differential signal. The output in the hold mode is always obtained. Compared to the AD conversion circuit 5X, the sample hold circuit 503 (details of each sample hold circuit 310) may be designed with a half operation speed. Since the operation speed is reduced by half, the power consumption is reduced, the transistor size may be small, and the area / power of the AD converter circuit 5X is reduced. Few.

<Operation of AD Conversion Circuit: First Example>
With reference to FIG. 4B, the AD converter circuit 5A of the first example will be described in detail with respect to the point that the operation speed of the sample hold circuit 503 is half that of the AD converter circuit 5X of the first comparative example. In the figure, CKSH is a clock signal for the sample hold circuit 503, CKPA is a clock signal for the comparison operation amplification circuit 501 (comparison operation amplification circuits 1_1 to 1_8), and CKLT is a clock signal for the latch circuit 508A (latch 580_1 to 580_8). It is. The clock signal CKPA has a frequency twice that of the clock signal CKSH, and the clock signal CKLT has a frequency twice that of the clock signal CKPA. Each clock signal is synchronized. As a result, the occurrence of an AD conversion error due to signal delay is prevented, and the AD conversion accuracy is improved.

  The sample hold output is AOUT, the reference potential input to the comparison operation amplification circuit 501 (respective comparison operation amplification circuits 1_1 to 1_8) is REF, the zero cross signal output of the comparison operation amplification circuit 501 is VO, and the latch output thermometer. The code is expressed as D, and the 4-bit digital code output is expressed as DOUT. In addition, a reference O (Odd) is attached to the odd number, and a reference E (Even) is attached to the even number. For convenience of description, full-width characters may be changed to half-width characters as appropriate.

  When the clock signal CKSH changes from the L level to the H level, the sample hold circuit 503 holds the analog signal AOUT1 and outputs it to the comparison operation amplification circuits 1_1 to 1_8 of the comparison operation amplification circuit 501.

  At this time, if the clock signal CKPA is at the H level, the odd-numbered reference potential REFO is input to the comparison operation amplifier circuits 1_1 to 1_8, and the comparison operation result VOO1 is output. The latches 580_1 to 580_8 perform positive / negative discrimination when the clock signal CKLT rises from the L level to the H level in response to the outputs of the comparison operational amplifier circuits 1_1 to 1_8, and the thermometer code DO1 when the reference potential is an odd number is followed by To the decoding circuit 509.

  On the other hand, if the clock signal CKPA is at the L level, the even-numbered reference potential REFE is input to the comparison operation amplifier circuits 1_1 to 1_8, and the comparison operation result VOE1 is output. The latches 580_1 to 580_8 perform positive / negative discrimination when the clock signal CKLT rises from the L level to the H level upon receiving the outputs of the comparison operational amplifier circuits 1_1 to 1_8, and the thermometer code DE1 when the reference potential is the even number is the subsequent stage. To the decoding circuit 509.

  As can be seen, the zero-cross signal VO is switched in a time division manner between the zero-cross signal VOO corresponding to the odd-numbered reference potential REF_O and the zero-cross signal VOE corresponding to the even-numbered reference potential REF_E. Correspondingly, the latch output is switched in a time-sharing manner between the latch output DO corresponding to the odd-numbered reference potential REF_O and the latch output DE corresponding to the even-numbered reference potential REF_E.

  The decode circuit 509 synthesizes the thermometer codes DO1 and DE1 that have been compared and calculated by dividing the reference potential into odd and even numbers, and outputs a 4-bit digital code DOUT1.

  Next, when the clock signal CKSH changes from the H level to the L level, the sample hold circuit 503 holds the analog signal AOUT2 and outputs it to the comparison operation amplification circuits 1_1 to 1_8 of the comparison operation amplification circuit 501. Thereafter, the operation is similar to the above-described operation for the analog signal AOUT1, and finally, the decode circuit 509 outputs the 4-bit digital code DOUT2.

  As can be seen from this result, the AD conversion operation clock in the AD conversion circuit 5A of the first example is not the clock signal CKSH for the sample hold circuit 503 but the clock signal CKPA for the comparison operational amplification circuit 501, and the clock signal The AD conversion result is output for each cycle of CKPA.

  In the AD conversion circuit 5X of the first comparative example, as shown in FIG. 4A, a normal sample hold circuit 310 having a sample output period is used for the sample hold circuit 503X. An example of the operation is shown in FIG. 4C. The normal flash AD conversion circuit 5X outputs an AD conversion result for each cycle of the sample and hold clock signal CKSH. On the other hand, the AD conversion circuit 5A of the first example outputs an AD conversion result with a half period of the sample and hold clock signal as shown in FIG. 4B.

  Therefore, when comparing the case where the AD conversion result is output in the same cycle, the frequency of the sample and hold clock signal CKSH of the AD converter 5A of the first example is 1 compared to the AD conversion circuit 5X of the first comparative example. Therefore, the operation speed of the sample and hold circuit 310 can be halved, which contributes to reduction of power consumption. As a result, it can be said that the influence of the two sample and hold circuits 310 is small.

  Here, the AD converter circuit 5A of the first example requires that each latch 580 of the latch circuit 508A operates at a frequency twice that of the AD operation clock. On the other hand, the AD conversion circuit 5X of the first comparative example may have the same frequency as the AD operation clock. This is because it is considered that the design of the latch 580 is difficult compared with the AD converter circuit 5X of the first comparative example, and there is a concern about an increase in power consumption in the portion of the latch 580, so that the power consumption is reduced by half the latch 580. The effect may be reduced. The AD conversion circuit 5B of the second example described later takes measures against this point.

<AD conversion circuit: second example>
FIG. 5 to FIG. 5A are diagrams for explaining the AD converter circuit of the second example of the present embodiment. Here, FIG. 5 is a diagram showing an overall outline of the AD conversion circuit 5B of the second example. FIG. 5A is a timing chart for explaining the operation of the AD converter circuit 5B of the second example.

  The AD converter circuit 5B of the second example time-divides one signal (in this example, the odd-even amplified output signals VOP and VON between the comparison operation amplification circuits 1_1 to 1_8 of the comparison operation amplification circuit 501 and the latch circuit 508B. Signal selection circuit 540 (third signal selection) having 1-input 2-output type selectors 542_1 to 542_8 (demultiplexer) that distributes the generated zero-cross signal VO) to each (two systems in this example). Circuit). In addition, the latch circuit 508B is provided with a latch 580 (580_1 to 580_16 in the figure) for each of the 16 system reference potentials, similarly to the AD conversion circuit 5X of the first comparative example. Among the 16 latches 580_1 to 580_16, the odd-numbered one is referred to as a latch 580_O, and the even-numbered one is referred to as a latch 580_E.

  The selectors 542_1 to 542_8 have switches 542_O and 542_E, respectively. Each of the switches 542_O and 542_E is a transistor switch using only one of pMOS and nMOS as an example in order to increase the circuit scale as much as possible. Here, it is assumed that the nMOS is turned on when the H level is input to the gate which is the control input terminal. The switch clock signal CKSWO is commonly supplied to the control input terminals of the odd-numbered switches 542_O, and the switch clock signal CKSWE is commonly supplied to the control input terminals of the even-numbered switches 542_E.

  Input sides of the selectors 542_1 to 542_8 (each input side of the switches 542_O and 542_E) are connected to outputs of corresponding ones of the comparison operational amplifier circuits 1_1 to _8. The output side of the switch 542_O is connected to the input of the odd-numbered latch 580 of the latch circuit 508, and the output side of the switch 542_E is connected to the input of the even-numbered latch 580 of the latch circuit 508. The output side of the switch 542_O is connected to the input of the odd-numbered latch 580_O of the latch circuit 508, and the output side of the switch 542_E is connected to the input of the even-numbered latch 580_E of the latch circuit 508.

  As described above, in the AD converter circuit 5B of the second example, the switches 542_O and 542_E are provided at the output of the comparison operation amplifier circuit 1_k of the AD converter circuit 5A of the first example, the latch 580_O is latched to the switch 542_O, and the latch is switched to the switch 542_E. By providing 580_E, the number of latches 580 included in the latch circuit 508 is doubled. The AD conversion circuit 5B has a demultiplexer (signal selection circuit) that switches the output destination of the comparison operational amplifier circuit 1 and outputs the output of the comparative operational amplifier circuit 1 in parallel, although being time-divisional.

  Here, the difference in the number of elements, area, and power depending on whether or not the AD conversion circuit 5B of the second example is applied will be considered. When the AD conversion circuit 5B of the second example is applied, the number of latches 580 included in the latch circuit 508 is the same as that of the AD conversion circuit 5X, and the number of the comparison operational amplification circuits 100 is halved, but the signal selection circuit 540 (selector 542). Need. Since one comparison operation amplification circuit 1 and one selector 542 (TR number = 2) are required for two system reference potentials, whether the comparison operation amplification circuit 1 is the first example or the second example, etc. However, it is not always possible to determine whether the circuit scale is reduced.

  Here, when the comparative operational amplifier circuit 1A (TR number = 10, R number = 2) of the first example is adopted as the comparative operational amplifier circuit 1, as shown in FIG. The number of transistors is 12 (= 10 + 2), and the load elements are two resistance elements, and the number of transistors is not reduced. However, the number of resistance elements that are load elements is reduced, which contributes to a reduction in circuit area.

  On the other hand, when the comparative operational amplifier circuit 1B of the second example (TR number = 12, R number = 2) is adopted as the comparative operational amplifier circuit 1, as shown in FIG. The number of transistors is 14 (= 12 + 2), the number of load elements is two resistance elements, the number of transistors is increased by two, and the number of resistance elements, which are load elements, is reduced. Whether or not is not decided. However, in general, a transistor may have a smaller area than a resistance element, and it can be said that the area reduction by reducing two resistance elements is more effective than the area increase by increasing two transistors. Therefore, in combination with the comparative operational amplifier circuit 1B of the second example, it can be said that the circuit area is reduced by using a resistive element instead of a transistor as the load element of the comparative operational amplifier circuit 100.

  On the other hand, regardless of whether the comparison operational amplifier circuit 1 is the first example or the second example, the time division processing is performed with respect to the two system reference potentials, so that the power consumption is approximately halved. The sample hold circuit 503 is the same as the first example, and may be designed with a half operation speed as compared with the AD conversion circuit 5X, which reduces power consumption and contributes to area and power reduction.

<Operation of AD Conversion Circuit: Second Example>
With reference to FIG. 5A, the operation of the AD conversion circuit 5B of the second example will be described. In the figure, CKSWO and CKSWE are clock signals for the selectors 542_1 to 542_8 connected to the outputs of the comparison operational amplifier circuits 1_1 to 1_8, CKLTO is a clock signal for the odd-numbered latch 580_O, and CKLTE is for the even-numbered latch 580_E. This is a clock signal. The output thermometer code of the odd-numbered latch 580_O is expressed as DO, and the output thermometer code of the even-numbered latch 580_E is expressed as DE.

  When the clock signal CKSH changes from the L level to the H level, the sample hold circuit 503 holds the analog signal AOUT1 and outputs it to the comparison operation amplification circuits 1_1 to 1_8 of the comparison operation amplification circuit 501. If the clock signal CKPA is at H level, the odd-numbered reference potential REFO is input to the comparison operation amplifier circuits 1_1 to 1_8, and the comparison operation result VOO1 is output. At this time, the clock signal CKSWO is at the H level, the clock signal CKSWE is at the L level, the switch 542_O is on, and the switch 542_E is off. Therefore, the outputs (comparison operation results VOO1) of the comparison operation amplifier circuits 1_1 to 1_8 are supplied only to the odd-numbered latches 580_O. When the clock signal CKLTO rises from the L level to the H level upon receiving the outputs (comparison operation result VOO1) of the comparison operation amplifier circuits 1_1 to 1_8, the latch 580_O performs positive / negative discrimination, and the thermometer when the reference potential is an odd number The code DO1 is output to the decoding circuit 509 at the subsequent stage.

  On the other hand, if the clock signal CKPA is at the L level, the even-numbered reference potential REFE is input to the comparison operation amplifier circuits 1_1 to 1_8, and the comparison operation result VOE1 is output. At this time, the clock signal CKSWO is at the L level, the clock signal CKSWE is at the H level, the switch 542_O is off, and the switch 542_E is on. Therefore, the outputs (comparison operation results VOE1) of the comparison operation amplifier circuits 1_1 to 1_8 are supplied only to the even-numbered latches 580_E. When the output (comparison operation result VOE1) of the comparison operation amplifier circuits 1_1 to 1_8 is received and the clock signal CKLTE rises from the L level to the H level, the latch 580_E performs positive / negative discrimination, and the thermometer when the reference potential is the even number The code DE1 is output to the subsequent decoding circuit 509.

  The decode circuit 509 synthesizes the thermometer code DO1 (generated by the latch 580_O) and DE1 (generated by the latch 580_E) by dividing the reference potential into odd and even numbers and outputs a 4-bit digital code DOUT1. .

  Next, when the clock signal CKSH changes from the HL level to the L level, the sample hold circuit 503 holds the analog signal AOUT2 and outputs it to each of the comparison operation amplification circuits 1_1 to 1_8 of the comparison operation amplification circuit 501. Thereafter, the operation is similar to the above-described operation for the analog signal AOUT1, and finally, the decode circuit 509 outputs the 4-bit digital code DOUT2.

  As can be seen from the above, also in the second example, the zero-cross signal VO is switched in a time division manner between the zero-cross signal VOO corresponding to the odd-numbered reference potential REF_O and the zero-cross signal VOE corresponding to the even-numbered reference potential REF_E. Correspondingly, the latch output is switched in a time-sharing manner between the latch output DO corresponding to the odd-numbered reference potential REF_O and the latch output DE corresponding to the even-numbered reference potential REF_E.

  In the first example, one latch 580 transmits the odd-numbered thermometer code DO and the even-numbered thermometer code DE to the decoding circuit 509 in a time division manner, whereas in the second example, the odd-numbered thermometer code DO. Is the latch 580_O and the even-numbered thermometer code DE is the latch 580_E, and there is a difference in dealing with each individually, but the operation of the decoding circuit 509 is not different between the first example and the second example.

  As can be seen from this result, the AD conversion operation clock in the AD conversion circuit 5A of the first example is not the clock signal CKSH for the sample hold circuit 503 but the clock signal CKPA for the comparison operational amplification circuit 501, and the clock signal The AD conversion result is output for each cycle of CKPA. If the operation clock of AD conversion is made the same as the frequency of the clock signal CKPA as before, the clock signal CKPA has a frequency twice that of the clock signal CKSH. The operating speed is reduced by half.

  In addition, since the clock signals CKLTO and CKLTE for the latch 580 have the same cycle as that of the clock signal CKPA, the latch 580 may be a circuit similar to the AD conversion circuit 5X of the first comparative example.

<AD conversion circuit: third example>
6 to 6F are diagrams for explaining the AD converter circuit of the third example of the present embodiment. Here, FIG. 6 is a diagram showing an overall outline of the AD conversion circuit 5C of the third example. FIG. 6A is a diagram illustrating a configuration example of a resistance interpolation circuit used in the AD conversion circuit 5C of the third example. FIG. 6B is a diagram illustrating a configuration example of a folding operation circuit (folding circuit) used in the AD conversion circuit 5C of the third example. FIG. 6C is a diagram illustrating the interpolation process applied in the third example. FIG. 6D is a diagram illustrating an overall outline of an AD conversion circuit 5Y of a second comparative example to which the AD conversion circuit 5C of the third example is not applied. FIG. 6E is a diagram illustrating a configuration example of a folding operation circuit used in the AD conversion circuit 5Y of the second comparative example. FIG. 6F is a timing chart for explaining the operation of the AD converter circuit 5C of the third example.

  The AD converter circuit 5C of the third example has a configuration corresponding to m + n bits, and adopts a method of generating digital data (gray code data) of upper m bits and lower n bits separately. In this example, it is a configuration corresponding to 5 bits, and digital data (gray code data) of upper 2 bits and lower 3 bits are generated separately. For the upper 2 bits, a general folding method is adopted, and for the lower 3 bits, a folding / interpolation type in which a folding method and interpolation (interpolation) are combined is adopted. The folding / interpolation type interpolates between the Q-phase sine wave pairs whose phases are shifted by a predetermined amount P obtained by the folding method to obtain the R / Q-phase sine wave pair. The sine wave pairs are respectively compared to generate binary data, and the binary data is converted to an n (3 in this example) bit Gray code.

  Here, when the AD converter circuit 5C of the third embodiment generates Q sine wave pairs by the folding method, the result of time-sharing the reference potential output from the comparison operational amplifier circuit 1 of the present embodiment. The output signal (a pair of amplified output signals VOP and VON in this example) is used, and the interpolation circuit samples and holds the output signal (sine wave) of each system obtained by the folding method in response to this ( Any one of them is characterized in that it does not require sample hold.

  For this reason, the AD conversion circuit 5C includes an upper bit conversion circuit 504UP that performs AD conversion on the upper 2 bits of the 5 bits by a general folding method. The upper bit conversion circuit 504UP is supplied with a reference potential for upper bit conversion from the reference potential generation circuit 502, and is supplied with a hold output of the analog input signal AIN from the sample hold circuit 503. The upper bit conversion circuit 504UP outputs upper 2 bits of digital data (gray code data) according to an input signal and a plurality of reference potentials.

  That is, the upper bit conversion circuit 504UP receives a differential analog signal pair (analog input signals VIP and VIN) and a differential reference signal pair (reference potentials VRP and VRN), respectively, and performs a comparison operation that amplifies the difference between the two signal pairs. Amplification circuit and a folding operation circuit that outputs a differential signal pair (folding signals FOP, FON) that is folded based on the zero-cross signal VO (amplified output signals VOP, VON) output from the comparison operation amplification circuit, and a folding operation The differential signal pair (folded signals FOP and FON) output from the circuit is compared, and the upper m-bit gray code is generated.

  Further, the AD converter circuit 5C of the third example, as a lower bit conversion circuit 504DN that performs AD conversion for the lower 3 bits of the 5 bits, first, a comparison operational amplifier circuit 501, a latch circuit 508, a decode A circuit 509 is provided. The low-order bit conversion circuit 504DN further includes an R-fold interpolation circuit 506 including an 8-system folding operation circuit 505, a sample hold circuit 560, and a resistance interpolation circuit 570 between the comparison operation amplification circuit 501 and the latch circuit 508. . The loopback operation circuit 505 is a differential output, and the loopback signal FO output from the loopback operation circuit 505 is a pair of the loopback signals FOP and FON. An R-fold interpolation circuit 506 having a configuration corresponding to the loopback signals FOP and FON is provided. Provided.

  Amplified output signals VO_1 to VO_8 (a differential pair of VOP and VON, respectively) based on the two reference potentials switched in a time division manner by the comparison operational amplifier circuit 501 are input to the folding operational circuit 505. As the folding operation circuit 505, for example, based on the method shown in paragraphs 59 to 62 of Japanese Patent Laid-Open No. 2007-143140 and FIG. A folding operation circuit for differential outputs (folding signals FOP, FON), that is, a configuration that folds 8 times may be adopted (details will be described later).

  An R-fold interpolation circuit 506 is shown as an example that receives a P-phase (here, two-phase) signal and performs a two-fold interpolation. As a result, the R-fold interpolation circuit 506 supplies the 4-phase signal IO to the latch circuit 508. The latch circuit 508 has four latches 580_1 to 580_4 corresponding to the number of signals output from the R-fold interpolation circuit 506. The four-phase cycle codes D_1 to D_4 output from the latch circuit 508 are supplied to the decode circuit 509.

  The decoding circuit 509 has a gray code encoder. The Gray code encoder is a circuit that converts, for example, four-phase cycle codes D_1 to D_4 from the R-fold interpolation circuit 506 into a Gray code using an exclusive OR circuit. Since a well-known circuit configuration can be used, description thereof is omitted here.

  The sample hold circuit 560 of the R-fold interpolation circuit 506 includes switches 562 (fourth signal selection circuit), holding capacitors 564, and buffers 566 for two systems for odd systems and even systems. A switch 562 and a holding capacitor 564 are provided for each of the folding signals FOP and FON in each of the odd system and the even system. On the other hand, since the buffer 566 is of the differential input / differential output type, differential folding signals FOP and FON can be input. Therefore, one buffer 566 is provided for each of the odd system and the even system. Is enough.

  Each of the switches 562_O and 562_E is a transistor switch using only one of pMOS and nMOS as an example in order to prevent the circuit scale from increasing as much as possible. Here, it is assumed that the nMOS is turned on when the H level is input to the gate which is the control input terminal. The switch clock signal CKSWO is supplied to the control input terminal of the odd-numbered system switch 562_O, and the switch clock signal CKSWE is supplied to the control input terminal of the even-numbered system switch 562_E. The input sides of the switches 562_O and 562_E are commonly connected to the output of the folding operation circuit 505.

  The output of the switch 562_O is connected to one terminal of the storage capacitor 564_O and the input of the buffer 566_O, and the output of the switch 562_E is connected to one terminal of the storage capacitor 564_E and the input of the buffer 566_E. The other terminals of the storage capacitors 564_O and 564_E are commonly connected to a reference point (for example, ground potential). Incidentally, in the case of this configuration example, it is not essential to provide the storage capacitor 564_E in relation to the operation. The output of the buffer 566_O is connected to the input of the latch 580_1, and the output of the buffer 566_E is connected to the input of the latch 580_3.

  As the resistance interpolation circuit 570 of the R-times interpolation circuit 506, for example, a resistor ring type configuration as shown in the interpolation circuit 12 of FIG. 8 of Japanese Patent Publication No. 07-061018 is adopted. Specifically, as shown in FIG. 6A (1), a ring connection circuit of eight resistance elements 572P, 574P, 576P, 578P, 572N, 574N, 576N, and 578N (in particular, referred to as interpolation resistors) having the same resistance value. It is. The connection point between the resistance element 572P and the resistance element 578N is the node N1P, the connection point between the resistance element 572P and the resistance element 574P is the node N2P, the connection point between the resistance element 574P and the resistance element 576P is the node N3P, and the resistance element 576P and the resistance A connection point with the element 578P is a node N4P. A connection point between the resistance element 572N and the resistance element 578P is a node N1N, a connection point between the resistance element 572N and the resistance element 574N is a node N2N, a connection point between the resistance element 574N and the resistance element 576N is a node N3N, and the resistance element 576N and the resistance element 578N are Let N4N be the connection point of.

  Node N1P is connected to non-inverted output IO1P of buffer 566_O and input IO1P of latch 580_1. Node N2P is connected to non-inverting input IO2P of latch 580_2. Node N3P is connected to non-inverting output IO3P of buffer 566_E and non-inverting input IO3P of latch 580_3. Node N4P is connected to non-inverting input IO4P of latch 580_4. Node N1N is connected to inverted output IO1N of buffer 566_O and inverted input IO1N of latch 580_1. Node N2N is connected to inverting input IO2N of latch 580_2. Node N3N is connected to inverted output IO3N of buffer 566_E and inverted input IO3N of latch 580_3. Node N4N is connected to inverting input IO4N of latch 580_4. As shown in FIG. 6A (2), the comparator (comparator) built in the latch 580 binarizes the difference between the input sine wave pair IOP and ION, that is, performs positive / negative discrimination based on the sine wave pair.

  As described above, the AD conversion circuit 5C of the third example includes the folding calculation circuit 505, the switch 562 for switching the output of the folding calculation circuit 505, and the storage capacitor 564 that holds the output of the folding calculation circuit 505 in a time division manner. The interpolation calculation is performed based on the two systems of information held in the holding capacitor 564.

  As an example, the 8-system input folding operation circuit 505 employs a circuit configuration as shown in FIG. 6B. The folding operation circuit 505 is an eight differential TR pair M (nMOS differential transistor pair: nMOS 550, 552) and a current source for supplying a predetermined operating current to the differential TR pair so as to correspond to eight system inputs. A functioning nMOS 554 and resistance elements 556 and 558 as load elements are provided. Here, a passive load using a resistance element is used as a load element, but an active load using a transistor as a load such as a pMOS current mirror circuit may be used.

  Zero cross signals VO_1 to VO_8 (amplified output signals VOP_1, VON_1 to VOP_8, VON_8) output from corresponding ones of the comparison operational amplifier circuits 1_1 to 1_8 are supplied to the differential TR pairs M_1 to M_8. Specifically, amplified output signals VOP_1 to VOP_8 are supplied to the nMOSs 550_1 to 550_8, and amplified output signals VON_1 to VON_8 are supplied to the nMOSs 552_1 to 552_8. The zero cross signal VO is switched in a time division manner between the zero cross signal VOO corresponding to the odd-numbered reference potential REF_O and the zero cross signal VOE corresponding to the even-numbered reference potential REF_E.

  The resistance element 556 has one terminal connected to the power supply Vdd, the other terminal connected in common to each drain of the odd-numbered nMOS 550_O and each drain of the even-numbered nMOS 552_E, and a folding signal FOP is output from the connection point. The The resistance element 558 has one terminal connected to the power supply Vdd, the other terminal connected in common to each drain of the odd-numbered nMOS 552_O and each drain of the even-numbered nMOS 550_E, and a folding signal FON is output from the connection point. The The output signal of each differential TR pair M has input / output characteristics folded at the position of the reference potential REF.

  The folding operation circuit 505 outputs the folding signal FO (FOP, FON) which crosses zero at the position of each reference potential REF by synthesizing the output signals of the eight differential TR pairs M. For example, FIG. 6C shows an operation waveform diagram showing input / output characteristics (IO vs. AIN) of the R-fold interpolation circuit 506.

  When the zero cross signal VO (amplified output signals VOP, VON) of the comparison operational amplifier circuits 1_1 to 1_8 is the odd reference potential REF_O, the folding operation circuit 505 performs a zero cross signal FO_O (zero crossing at the position of the odd reference potential REF_O). FOP_O, FON_O: IO1) is output. Further, when the zero-cross signal VO (amplified output signals VOP and VON) of the comparison operation amplifier circuits 1_1 to 1_8 is the even-numbered reference potential REF_E, the folding calculation circuit 505 zero-crosses at the position of the even-numbered reference potential REF_E. (FOP_E, FON_E: IO3) is output. There is a 90 degree phase difference between the folding signal FO_O and the folding signal FO_E.

  As can be seen from this, the folding operation circuit 505 outputs the folding signals FO_O and FO_E in a time-sharing manner. Incidentally, since the characteristic (FOP, FON: IO) of the folding signal FO looks like a sine wave, the folding operation circuit 505 is also called a sine wave generation circuit. Therefore, the folding operation circuit 505 outputs the two-phase sine wave pairs IO1 and IO3 having a phase difference of 90 degrees according to the analog input signal AIN in a time division manner.

  The R-fold interpolation circuit 506 is based on the folding signals FO_O and FO_E (two-phase sine wave pairs IO1 and IO3) output from the folding arithmetic circuit 505 in a time-sharing manner, between the two-phase sine wave pairs IO1 and IO3. A sine wave pair IO2 and IO4 is generated by interpolation to obtain a 4-phase sine wave pair. In other words, the R-fold interpolation circuit 506 generates four sine wave pairs obtained by dividing the sine wave pair IO1 and IO3 into two. At this time, the folding operation circuit 505 outputs the folding signals FO_O and FO_E (two-phase sine wave pairs IO1 and IO3) in a time-sharing manner. A sample hold circuit 560 is provided as a mechanism for holding (sine wave pair IO1 in this example). Positive / negative discrimination is performed by inputting the sine wave pairs IO1 to IO4 of each node to the comparator of the latch 580.

  On the other hand, as shown in FIG. 6D, in the AD conversion circuit 5Y of the second comparative example (normal folding method) to which the third embodiment is not applied, the comparison operation amplification circuit 501Y includes the comparison operation amplification circuit 100 for each reference potential REF. The folding operation circuit 505Y has a folding operation circuit 505_O and a folding operation circuit 505_E separately. The folding operation circuit 505_O receives the zero-cross signal VOO corresponding to the odd-numbered reference potential REF_O, and generates a folding signal FO_O (FOP_O, FON_O: IO1) that zero-crosses at the position of the odd-numbered reference potential REF_O. The folding operation circuit 505_E receives the zero-cross signal VOE corresponding to the even-numbered reference potential REF_E, and generates a folding signal FO_E (FOP_E, FON_E: IO3) that zero-crosses at the position of the even-numbered reference potential REF_E.

  As an example, the odd-numbered folding operation circuit 505_O and the even-numbered folding operation circuit 505_E employ a circuit configuration as shown in FIG. 6E. In any case, the basic circuit configuration is the same as that of the folding operation circuit 505, but the zero cross signal VO input to the folding operation circuit 505_O is only the zero cross signal VOO corresponding to the odd-numbered reference potential REF_O. The zero-cross signal VO input to 505_E is only the zero-cross signal VOE corresponding to the even-numbered reference potential REF_O. This is apparent from the fact that the folding operation circuit 505_O and the folding operation circuit 505_E are individually provided.

  Comparing the AD conversion circuit 5C and the AD conversion circuit 5Y, first, time-division processing is performed with respect to two systems of reference potentials, so the power consumption is approximately halved. Regarding the circuit scale, the scale of the comparison operational amplifier circuit 501 and the folding operational circuit 505 can be reduced, but the sample hold circuit 560 is required. Therefore, the circuit scale of the sample hold circuit 560 is smaller than the reduction of the circuit scale of the comparison operational amplifier circuit 501 × the number of input systems to the folding operation circuit 505 (eight systems in this example) + the reduction of the folding operation circuit 505. Keep in mind that Even if the reduction effect on the comparison operational amplifier circuit 501 side is small, the circuit scale of the folding operation circuit 505 is halved. It can be said that a sufficient reduction effect can be obtained. Of course, the comparative operational amplifier circuit 501 preferably uses the comparative operational amplifier circuit 1A of the first example instead of the comparative operational amplifier circuit 1B of the second example.

<Operation of AD Conversion Circuit: Third Example>
With reference to FIG. 6F, the operation of the AD conversion circuit 5C of the third example will be described. In the figure, CKSWO is a clock signal for the switch 562_O, CKSWE is a clock signal for the switch 562_E, and CKLT is a clock signal for the latches 580_1 to 580_4.

  When the clock signal CKSH changes from the L level to the H level, the sample hold circuit 503 holds the analog signal AOUT1 and outputs it to the comparison operation amplification circuits 1_1 to 1_8 of the comparison operation amplification circuit 501. If the clock signal CKPA is at H level, the odd-numbered reference potential REFO is input to the comparison operation amplifier circuits 1_1 to 1_8, and the comparison operation result VOO1 is output. In response, the folding operation circuit 505 supplies the R-fold interpolation circuit 506 with a folding signal FO_O (FOP_O, FON_O: IO1) that crosses zero at the position of the odd-numbered reference potential REF_O.

  At this time, the clock signal CKSWO is at the H level, the clock signal CKSWE is at the L level, the switch 562_O is on, and the switch 562_E is off. Therefore, the folding signal FO_O (FOP_O, FON_O: IO1) output from the folding calculation circuit 505 is sampled in the holding capacitor 564_O and output to the node N1 of the resistance interpolation circuit 570 via the buffer 566_O.

  On the other hand, if the clock signal CKPA is at the L level, the even-numbered reference potential REFE is input to the comparison operation amplifier circuits 1_1 to 1_8, and the comparison operation result VOE1 is output. In response, the folding operation circuit 505 supplies the R-fold interpolation circuit 506 with a folding signal FO_E (FOP_E, FON_E: IO3) that crosses zero at the position of the even-numbered reference potential REF_E. At this time, the clock signal CKSWO is at the L level, the clock signal CKSWE is at the H level, the switch 562_O is off, and the switch 562_E is on. Therefore, the folding signal FO_E (FOP_E, FON_E: IO3) output from the folding calculation circuit 505 is sampled in the holding capacitor 564_E and output to the node N3 of the resistance interpolation circuit 570 via the buffer 566_E.

  At this time, since the switch 562_O is off, the sampled folding signal FO_O (FOP_O, FON_O: IO1) is held in the storage capacitor 564_O, and is output to the node N1 of the resistance interpolation circuit 570 via the buffer 566_O. Has been.

  Therefore, when the folding signal FO_E (FOP_E, FON_E: IO3) is supplied to the node N3 of the resistance interpolation circuit 570 via the buffer 566_E, the R-fold interpolation circuit 506 supplies the sine wave pair IO1 to the node N2 of the resistance interpolation circuit 570. , IO3 is interpolated between the sine wave pairs IO2 and IO3, and a sine wave pair IO4 is generated at the node N4 of the resistance interpolation circuit 570 by interpolating between the sine wave pairs IO3 and IO1.

  As a result, the four-phase sine wave pairs IO1, IO2, IO3, and IO4 are supplied to the latch circuit 508 from the R-fold interpolation circuit 506.

  The latch circuit 508 receives the four-phase sine wave pairs IO1, IO2, IO3, and IO4, and when the clock signal CKLT rises from the L level to the H level, the latches 580_1 to 580_4 perform the positive / negative discrimination and acquire the cycle codes D1_1 to D1_4. Then, the data is output to the decoding circuit 509 at the subsequent stage. The decode circuit 509 outputs a low-order 3-bit digital code DOUT1 (gray code) based on the four-phase cycle codes D1_1 to D1_4. That is, when the four-phase sine wave pairs IO1, IO2, IO3, and IO4 are compared by the comparator, binarized cycle codes D1_1 to D1_4 are obtained. Then, when the cycle codes D1_1 to D1_4 are coded by the decoding circuit 509, a lower three-bit gray code is obtained.

  Next, when the clock signal CKSH changes from the HL level to the L level, the sample hold circuit 503 holds the analog signal AOUT2 and outputs it to each of the comparison operation amplification circuits 1_1 to 1_8 of the comparison operation amplification circuit 501. Thereafter, the operation is the same as that of the analog signal AOUT1, and finally, the decode circuit 509 outputs the lower three bits of the digital code DOUT2 (gray code) based on the four-phase cycle codes D2_1 to D2_4. To do.

  As can be seen from this result, in the AD conversion in the AD conversion circuit 5C of the third example, for the lower 3 bits, the reference potential REF for folding (sine wave generation) is an odd-numbered and even-numbered time-division operation circuit 505. Is different from the AD conversion circuit 5Y of the second comparative example in that the two-phase sine wave pairs IO1 and IO3 are generated in a time-sharing manner, but the subsequent interpolation processing and cycle code generation and gray code conversion are performed. The conversion is the same as the AD conversion circuit 5Y of the second comparative example.

  AD conversion with reduced circuit area and power than the AD conversion circuit 5Y of the second comparative example by switching the output of the folding operation circuit 505 functioning as a sine wave generation circuit and sample-holding each. A vessel is realized.

  In the above description, the configuration corresponding to 5 bits has been described. However, the configuration is not limited to 5 bits, and the configuration can be similarly applied to 6 bits or more. Further, the upper bit and the lower bit can be classified arbitrarily. In general, the upper bits are less than the lower bits.

  In the above description, the configuration including the resistance interpolation circuit 570 has been described. However, it is not essential to include the resistance interpolation circuit 570, and the configuration may be such that the resistance interpolation circuit 570 is removed. Further, it is not necessary to divide into upper bits and lower bits, and in this case, the upper bit conversion circuit 504UP in the above description may be removed. Since these modifications are configurations that do not include the respective functional units, the configuration can be specified without needing to be illustrated, and the operation in that case can also be specified.

<Application to electronic equipment: Recording / playback device>
FIG. 7 is a diagram illustrating the electronic apparatus according to the present embodiment. The electronic apparatus according to the present embodiment is obtained by applying the mechanism of the comparison operational amplifier circuit 1, the sample hold circuit 3, and the AD conversion circuit 5 to a general electronic apparatus. That is, an example in which the comparison operational amplifier circuit and AD conversion circuit according to the present invention are applied to an electronic device is shown. FIG. 7 shows a recording / reproducing apparatus (optical disc apparatus) as an example of the electronic apparatus. In the comparative operational amplifier circuit and the AD conversion circuit, by dealing with a plurality of systems of reference potentials REF in a time-sharing manner, circuit reduction and power consumption reduction can also be achieved as an electronic device.

  The recording / reproducing apparatus 9 of the present embodiment includes a spindle motor 910 that rotates an optical disk PD (Photo Disk) on which information to be reproduced such as music is recorded, and a motor driver 912 that drives the spindle motor 910 as a rotary servo system. The optical pickup 914 includes a laser light source for recording additional information on the optical disc PD or reading information recorded on the optical disc PD.

  As the optical disk PD, in addition to a so-called reproduction-only optical disk such as a CD (compact disk) or a CD-ROM (Read Only Memory), a write-once optical disk such as a CD-R (Recordable), a CD-RW (Rewritable), or the like. Such a rewritable optical disc may be used. Furthermore, it is not limited to a CD-based optical disk, but may be an MO (magneto-optical disk), a normal DVD (Digital Video or Versatile Disk), or a next-generation DVD using a blue laser with a wavelength of about 407 nm, for example. It may be a DVD-type optical disc. Further, it may be a so-called double density CD (DDCD; DD = Double Density), CD-R, or CD-RW in which the recording density is approximately double that of the current format while following the current CD format. .

  The recording / reproducing apparatus 9 includes a spindle motor control unit 930 and a pickup control unit 940. The spindle motor control unit 930 is an example of a rotation control unit (rotation servo system) that controls the motor driver 912. The pickup control unit 940 is an example of a tracking servo system and a focus servo system, and controls the radial position of the optical pickup 914 with respect to the optical disc PD.

  The recording / reproducing apparatus 9 includes a recording / reproducing signal processing unit that is an example of an information recording unit that records information via an optical pickup 914 and an information reproducing unit that reproduces information recorded on the optical disc PD as a recording / reproducing system. 950. As a configuration of the recording / reproduction signal processing unit 950, for example, a phase synchronization circuit and an AD conversion circuit are provided.

  The recording / reproducing apparatus 9 includes, as a controller system, a controller 962 and an interface unit that performs an interface function that is not illustrated. The controller 962 is configured by a microprocessor (MPU: Micro Processing Unit), and controls the operation of a servo system having a spindle motor control unit 930 and a pickup control unit 940 and a recording / reproduction signal processing unit 950. The interface unit has an interface (connection) function with a personal computer (hereinafter referred to as a personal computer) which is an example of an information processing apparatus (host apparatus) that performs various types of information processing using the recording / reproducing apparatus 9. A host IF controller is provided in the interface unit. The recording / reproducing apparatus 9 and the personal computer constitute an information recording / reproducing system (optical disc system).

<Recording / Signal Processing Unit>
The recording / reproduction signal processing unit 950 includes an RF amplification unit 952, a waveform shaping unit 953 (waveform equalizer; Equalizer), and an AD conversion unit 954 (ADC; Analog to Digital Converter) which is an example of an AD conversion circuit. . An analog signal processing system (each functional unit from the optical pickup 914 to the waveform shaping unit 953) arranged in the preceding stage of the AD conversion unit 954 constitutes an analog signal generation unit that generates a differential analog signal pair to be AD converted. .

  The RF amplification unit 952 amplifies a minute RF (high frequency) signal (hereinafter also referred to as a reproduction RF signal) read by the optical pickup 914 to a predetermined level. The waveform shaping unit 953 shapes the reproduction RF signal output from the RF amplification unit 952. The AD conversion unit 954 converts the analog reproduction RF signal output from the waveform shaping unit 953 into digital data.

  The recording / reproduction signal processing unit 950 includes a clock reproduction unit 955, a digital signal processing unit 956 composed of a DSP (Digital Signal Processor), a recording current control unit 957, and a write clock generation unit 960.

  The clock regeneration unit 955 regenerates a clock signal based on the digital data string output from the AD conversion unit 954. The clock recovery unit 955 includes a data recovery type phase synchronization circuit (PLL circuit) that generates a clock signal by locking to digital data (digital data string Din) from the AD conversion unit 954. The clock recovery unit 955 supplies the recovered clock signal to the AD conversion unit 954 as an AD clock (sampling clock) CKad, or supplies it to other functional units. The AD conversion unit 954 converts an analog signal into digital data based on the AD clock CKad. The digital signal processing unit 956 demodulates the digital data sequence (corresponding to the reproduction RF signal) output from the AD conversion unit 954 and performs digital signal processing such as decoding digital audio data or digital image data. .

  The recording current control unit 957 controls (on / off) the recording current of the laser beam for recording information on the optical disc PD. The recording current control unit 957 multi-pulse modulates the optical output power according to the material of the optical disc PD and the recording speed, and also outputs the optical output (light intensity, light intensity) of the laser light emitted from the laser light source (in the optical pickup 914). APC (Auto Power Control) control is performed to keep the optical output power) at a constant value.

  The write clock generation unit 960 generates a write clock for modulating data when recording on the optical disc PD based on a reference clock supplied from a crystal oscillator or the like.

  Also in the recording / reproducing apparatus 9 having such a configuration, the AD conversion unit 954 applies the mechanism of the AD conversion circuits 5A to 5C of the present embodiment that handles the reference potentials REF of a plurality of systems in a time-sharing manner. A mechanism to reduce power consumption is realized.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, the example of application to a recording / reproducing apparatus such as an optical disc apparatus has been described as an electronic device. An AD conversion circuit may be used. The AD conversion circuits 5A to 5C of the above embodiment can be applied to this AD conversion circuit.

  Furthermore, the present invention is not limited to the recording / reproducing device, and can be applied to other electronic devices such as a solid-state imaging device, an imaging device, and a display device.

  Further, the comparison operational amplifier circuit 1 of the present embodiment is not limited to application to the AD conversion circuits 5A to 5C of the present embodiment, but various comparative operational amplifier circuits that handle a plurality of reference potentials REF, and general using the same It can also be applied to typical electronic devices.

It is a figure explaining the comparative operational amplifier circuit of the 1st example of this embodiment. It is a figure explaining the comparative operational amplifier circuit of the 2nd example of this embodiment. It is a figure explaining the sample hold circuit of this embodiment. It is a figure which shows the whole outline | summary of the AD conversion circuit of the 1st example of this embodiment. It is a figure which shows the whole outline | summary of the AD conversion circuit of the 1st comparative example which does not apply the AD conversion circuit of the 1st example of this embodiment. It is a timing chart explaining operation | movement of the AD converter circuit of the 1st example of this embodiment. It is a timing chart explaining operation of an AD conversion circuit of the 1st comparative example. It is a figure which shows the whole outline | summary of the AD conversion circuit of the 2nd example of this embodiment. It is a timing chart explaining operation of the AD converter circuit of the 2nd example of this embodiment. It is a figure which shows the whole outline | summary of the AD conversion circuit of the 3rd example of this embodiment. It is a figure which shows the structural example of the resistance interpolation circuit used with the AD converter circuit of the 3rd example of this embodiment. It is a figure which shows the structural example of the folding | turning arithmetic circuit used with the AD converter circuit of the 3rd example of this embodiment. It is a figure explaining the interpolation process applied in the 3rd example of this embodiment. It is a figure which shows the whole AD converter circuit of the 2nd comparative example which does not apply the AD converter circuit of the 3rd example of this embodiment. It is a figure which shows the structural example of the folding | turning arithmetic circuit used with the AD converter circuit of a 2nd comparative example. It is a timing chart explaining operation of an AD converter circuit of the 3rd example of this embodiment. It is a figure explaining the electronic device of this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Comparison operation amplifier circuit, 100 ... Comparison operation amplifier circuit, 110 ... 1st differential amplifier circuit, 120 ... 2nd differential amplifier circuit, 130 ... Load circuit, 140 ... Signal selection circuit (2nd signal selection circuit) DESCRIPTION OF SYMBOLS 3 ... Sample hold circuit, 310 ... Sample hold circuit, 340 ... Signal selection circuit (first signal selection circuit), 5 ... AD conversion circuit, 501 ... Comparison operation amplification circuit, 502 ... Reference potential generation circuit, 503 ... Sample Hold circuit, 504DN: lower bit conversion circuit, 504UP ... upper bit conversion circuit, 505 ... folding operation circuit, 506 ... R-fold interpolation circuit, 508 ... latch circuit, 509 ... decode circuit, 540 ... signal selection circuit (third signal) Selection circuit), 560... Sample hold circuit, 562... Switch (fourth signal selection circuit), 564... Holding capacitor, 566. Resistance interpolation circuit, 580 ... Latch, 6 ... Digital data acquisition unit, 9 ... Recording / reproducing apparatus, 954 ... AD conversion unit

Claims (12)

A plurality of sample hold circuits that temporarily hold the levels of the differential analog signal pairs at different timings, and a first signal selection circuit that selects one of the output signal pairs in the hold mode of the plurality of sample hold circuits. A sample hold unit;
A second signal selection circuit that switches a plurality of differential reference signal pairs to be handled in a time-sharing manner, two sets of differential amplifier circuits to which the output signal pair and the differential reference signal pair are input, and the output A comparison operation amplification unit that amplifies a difference between each of the signal pair and the plurality of differential reference signal pairs, and outputs a plurality of amplified output signal pairs in a time-sharing manner;
A digital data acquisition unit for acquiring digital data by binarizing the difference between the plurality of amplified output signal pairs output in a time-sharing manner from the comparison operational amplifier circuit;
An AD conversion circuit comprising: A third signal selection circuit for distributing the plurality of amplified output signal pairs separately between the comparison operation amplification unit and the digital data acquisition unit;
The digital data acquisition unit includes a binarization unit that binarizes a difference between the amplified output signal pairs for each of the plurality of amplified output signal pairs distributed by the third signal selection circuit. The AD conversion circuit described. A plurality of sample hold circuits that temporarily hold the levels of the differential analog signal pairs at different timings, and a first signal selection circuit that selects one of the output signal pairs in the hold mode of the plurality of sample hold circuits. A sample hold unit;
A second signal selection circuit that switches a plurality of differential reference signal pairs to be handled in a time-sharing manner, two sets of differential amplifier circuits to which the output signal pair and the differential reference signal pair are input, and the output A comparison operation amplification unit that amplifies a difference between each of the signal pair and the plurality of differential reference signal pairs, and outputs a plurality of amplified output signal pairs in a time-sharing manner;
For the plurality of differential reference signal pairs, a P-phase folded differential signal pair whose phase is shifted by a predetermined amount based on each amplified output signal pair output in a time division manner from the comparison operation amplification unit is output in a time division manner. A folding operation circuit to
A fourth signal selection circuit that distributes the P-phase folded differential signal pair separately and a holding circuit that holds the P-phase folded differential signal pair distributed by the fourth signal selection circuit A sample and hold circuit comprising:
Digital data acquisition for binarizing the difference between the P-phase folded differential signal pairs output from the sample-and-hold circuit and converting the differential analog signal pair to digital data based on each binarized data And
An AD conversion circuit comprising: An upper bit conversion circuit for converting a differential analog signal pair to an upper m-bit Gray code; and a lower bit conversion circuit for converting the differential analog signal pair to a lower n-bit Gray code, the differential analog signal pair With a digital data acquisition unit that converts
The upper bit conversion unit includes a first folding operation circuit that outputs a differential signal pair folded based on an amplified output signal pair on the upper m bit side of a plurality of differential reference signal pairs, By comparing the differential signal pair output from the first folding operation circuit, an upper m-bit gray code is generated,
The lower bit converter is
A plurality of sample hold circuits that temporarily hold the levels of the differential analog signal pairs at different timings, and a first signal selection circuit that selects one of the output signal pairs in the hold mode of the plurality of sample hold circuits. A sample hold unit;
A second signal selection circuit that switches a plurality of differential reference signal pairs to be handled in a time-sharing manner, two sets of differential amplifier circuits to which the output signal pair and the differential reference signal pair are input, and the output A comparison operation amplification unit that amplifies a difference between each of the signal pair and the plurality of differential reference signal pairs, and outputs a plurality of amplified output signal pairs in a time-sharing manner;
For the plurality of differential reference signal pairs, a P-phase folded differential signal pair whose phase is shifted by a predetermined amount based on each amplified output signal pair output in a time division manner from the comparison operation amplification unit is output in a time division manner. A folding operation circuit to
A fourth signal selection circuit that distributes the P-phase folded differential signal pair separately and a holding circuit that holds the P-phase folded differential signal pair distributed by the fourth signal selection circuit A sample and hold circuit comprising:
A digital data acquisition unit that binarizes the difference between the P-phase folded differential signal pairs output from the sample-and-hold circuit and generates a lower-order n-bit gray code based on each binarized data;
An AD conversion circuit. An interpolating unit that generates an R × Q phase folded differential signal pair by interpolating between the P phase folded differential signal pairs at a subsequent stage of the sample hold circuit;
5. The AD according to claim 3, wherein the difference between the R × Q-phase folded differential signal pairs is binarized, and the differential analog signal pair is converted into digital data based on each binarized data. Conversion circuit. The AD conversion circuit according to any one of claims 1 to 5, wherein each signal selection circuit uses one transistor for each signal. A signal selection circuit that switches to handle a plurality of differential reference signal pairs in a time-sharing manner;
Two sets of differential amplifier circuits to which a differential analog signal pair and a plurality of differential reference signal pairs are input;
With
A comparison operation amplification circuit that amplifies a difference between each of the differential analog signal pair and the plurality of differential reference signal pairs and outputs the plurality of amplified output signal pairs in a time division manner. Each of the two sets of differential amplifier circuits includes an analog signal input transistor to which the differential analog signal pair is input and a reference signal input transistor to which the plurality of differential reference signal pairs are input in a time division manner Constitutes a differential pair,
8. The signal selection circuit is arranged on the control input end side of the reference signal input transistor in each of the two sets of differential amplifier circuits, and switches the plurality of differential reference signal pairs in a time division manner. The comparative operational amplifier circuit described in 1. Each of the two sets of differential amplifier circuits includes an analog signal input transistor to which the differential analog signal pair is input and a plurality of reference signal inputs to which the plurality of differential reference signal pairs are separately input. Each of the transistors forms a differential pair,
In each of the two sets of differential amplifier circuits, the signal selection circuit is disposed on an operation current supply end side of the plurality of reference signal input transistors or an output end side on which the amplified output signal pair is output, The comparison operational amplifier circuit according to claim 7, wherein the current path of the operating current is switched in a time division manner. The circuit scale of the signal selection circuit that time-divides the plurality of differential reference signal pairs can be obtained by using all or a part of the comparison operational amplification circuit for the plurality of differential reference signal pairs by using the signal selection circuit. The comparative operational amplifier circuit according to claim 7, wherein the comparative operational amplifier circuit is smaller than a reduction in circuit scale on the side of the comparative operational amplifier circuit due to common use. An analog signal generation unit for generating a differential analog signal pair to be AD converted;
A first signal selection circuit for selecting one of a plurality of sample hold circuits that temporarily hold the level of the differential analog signal pair in accordance with a clock signal and an output signal pair in a hold mode of the plurality of sample hold circuits; A sample hold unit provided;
A second signal selection circuit that switches a plurality of differential reference signal pairs to be handled in a time-sharing manner, two sets of differential amplifier circuits to which the output signal pair and the differential reference signal pair are input, and the output A comparison operation amplification unit that amplifies a difference between each of the signal pair and the plurality of differential reference signal pairs, and outputs a plurality of amplified output signal pairs in a time-sharing manner;
An electronic apparatus comprising: a digital data acquisition unit that acquires digital data by binarizing a difference between the plurality of amplified output signal pairs output in a time-sharing manner from the comparison operational amplifier circuit. An analog signal generation unit for generating a differential analog signal pair to be AD converted;
A first signal selection circuit for selecting one of a plurality of sample hold circuits that temporarily hold the level of the differential analog signal pair in accordance with a clock signal and an output signal pair in a hold mode of the plurality of sample hold circuits; A sample hold unit provided;
A second signal selection circuit that switches a plurality of differential reference signal pairs to be handled in a time-sharing manner, two sets of differential amplifier circuits to which the output signal pair and the differential reference signal pair are input, and the output A comparison operation amplification unit that amplifies a difference between each of the signal pair and the plurality of differential reference signal pairs, and outputs a plurality of amplified output signal pairs in a time-sharing manner;
For the plurality of differential reference signal pairs, a P-phase folded differential signal pair whose phase is shifted by a predetermined amount based on each amplified output signal pair output in a time division manner from the comparison operation amplification unit is output in a time division manner. A folding operation circuit to
A fourth signal selection circuit that distributes the P-phase folded differential signal pair separately and a holding circuit that holds the P-phase folded differential signal pair distributed by the fourth signal selection circuit A sample and hold circuit comprising:
A digital data acquisition unit that binarizes the difference between the P-phase folded differential signal pairs and converts the differential analog signal pair into digital data based on each binarized data;
With electronic equipment.

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