JP2005136626A - Audio signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an audio signal processor which reduces power consumption and performs various signal processings. <P>SOLUTION: A data path part 30 receives voice data A and B, and performs signal processing to those data by time-division control. A mode register 50 stores mode information to designate signal processing to be performed. A state machine part 40 successively generates a control signal, to make the data path part 30 execute one or more arithmetic processings configuring signal processings to be designated by mode information stored in the mode register 50. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an audio signal processing apparatus that performs various kinds of acoustic processing on an audio signal.

  There has been provided an audio signal processing apparatus capable of performing a plurality of types of arithmetic processing such as filter processing, equalizer processing, and sound image localization processing on an audio signal. Here, each arithmetic processing such as filter processing requires a relatively large arithmetic circuit including a multiplier and an accumulator. Therefore, if an audio signal processing apparatus capable of performing complex signal processing combining a plurality of processes is to be configured, a circuit for that purpose becomes extremely large. In addition, if the circuit is large, the power consumption of the audio signal processing apparatus increases in order to operate such a circuit. On the other hand, some audio signal processing apparatuses receive a plurality of channels of audio signals having different formats such as sampling frequency and perform signal processing. In this type of audio signal processing apparatus, signal processing is performed on the input digital audio signal by an arithmetic circuit prepared for each channel, the digital audio signal of each channel subjected to signal processing is D / A converted, mixed and output. It was. Since this type of audio device also has an arithmetic circuit for each channel, a circuit for signal processing is large-scale and power consumption is large. In order to solve such a problem, an audio signal processing apparatus has been proposed in which a common arithmetic circuit is used to sequentially execute a plurality of types of arithmetic processing such as filter processing and equalizer processing by time division control. According to this type of audio signal processing apparatus, since a single arithmetic circuit is used by time-division control, a small circuit configuration can be achieved. Note that this type of audio signal processing apparatus is disclosed in Patent Document 1, for example.

JP-A-12-122650

By the way, the above-described conventional audio signal processing apparatus sequentially executes predetermined types of arithmetic processing in a fixed order. For this reason, when trying to provide the market with many audio signal processing devices of different specifications, the audio signal processing device must be developed and manufactured for each specification, development cost, There was a problem that the manufacturing cost increased. As a method for solving this problem, for example, the audio signal processing device itself is configured as a fully equipped device capable of performing many arithmetic processing such as filter processing, equalizer processing, and sound image localization processing. For example, a method of realizing many specifications by omitting filter processing and not omitting filter processing in another specification is conceivable. For example, in the case of filter processing, such omission of arithmetic processing can be realized by a method in which the filter coefficient for filter operation is set to “1” and the digital audio signal to be processed is passed through the arithmetic circuit. is there. However, even though the arithmetic circuit is passed through, the arithmetic circuit operates at that time, so that there is a problem that wasteful power is consumed for unnecessary signal processing.
The present invention has been made in view of the above-described circumstances, and an object thereof is to provide an audio signal processing apparatus that can suppress power consumption and can perform various signal processing.

In order to solve the above-described problems, the present invention provides a data path unit for performing arithmetic processing on an audio signal, a mode register for storing mode information for designating signal processing to be performed, and mode information stored in the mode register. An audio signal processing apparatus is provided that includes a state machine unit that sequentially outputs a control signal that causes the data path unit to execute one or a plurality of arithmetic processes constituting the signal processing specified by.
According to such an audio signal processing device, various signal processes can be executed by the data path unit by rewriting the mode information in the mode register. In addition, the data path unit executes only the operations constituting the signal processing and does not perform useless operations, so that power consumption can be kept low.
In a preferred aspect, the state machine unit outputs information indicating a location of input data to be subjected to each arithmetic processing and information indicating an output destination of a result of each arithmetic processing as the control signal.
In another preferred embodiment, the audio signal processing apparatus includes a plurality of interfaces that receive an audio signal from the outside or generate an audio signal based on a signal supplied from the outside and supply the audio signal to the data path unit. The state machine unit includes means for generating a control signal for causing the data path unit to perform arithmetic processing for converting the format of the audio signal supplied to the data path unit into a predetermined format.
In this aspect, the state machine unit may include means for generating a control signal that causes the data path unit to perform arithmetic processing for mixing a plurality of audio signals of the same format in the data path unit.
In another preferred aspect, the state machine unit outputs a control signal for causing the data path circuit to perform signal processing specified by mode information stored in the mode register each time a clock having a predetermined period is given. Generate.
In this aspect, the data path unit has means for sending a state signal indicating the state of the arithmetic processing being executed to the state machine unit, and the state machine unit receives a next clock based on the state signal. The content of the control signal sent to the data path unit when given may be determined.

Embodiments of the present invention will be described below with reference to the drawings.
<First Embodiment>
FIG. 1 is a block diagram showing the configuration of an audio signal processing apparatus 10 according to the first embodiment of the present invention. The audio signal processing apparatus 10 is an LSI formed by forming circuits corresponding to the respective components shown in the figure on a semiconductor chip, and is mounted on various audio devices that require functions such as an effector function and a mixing function.

  The audio signal processing apparatus 10 according to the present embodiment is an apparatus that receives time-series audio data obtained by sampling an audio waveform from a source A, receives performance data from a source B, and performs these processes. Here, the source A is an audio playback device such as an external device connected to an audio device on which the audio signal processing device 10 is mounted or an MP3 (MPEG 1 layer 3) decoder built in the audio device. The source B is a host processor that controls the audio signal processing apparatus 10 in an audio device in which the audio signal processing apparatus 10 is mounted, for example.

  In order to receive audio data from the source A, the audio signal processing apparatus 10 is provided with a digital audio I / F 11. In the present embodiment, audio data A having a sampling frequency f1 composed of two channels of L and R is input via the digital audio I / F 11.

  Further, in order to receive performance data from the source B and obtain audio data, the audio signal processing apparatus 10 is provided with a CPU I / F 12, a sequencer 13 and a sound source 14. The performance data is supplied from the source B to the sequencer 13 via the CPU I / F 12. This performance data is sequential data, and this sequential data includes a series of event data for instructing control of the sound source 14 such as note-on and note-off, and duration data for designating the transmission interval of each event data to the sound source 14. Contains. The sequencer 13 controls the transmission timing of the event data to the sound source 14. More specifically, when the sequencer 13 sends certain event data to the sound source 14, the sequencer 13 waits for the time corresponding to the duration data associated with the subsequent event data to elapse and sends the subsequent event data to the sound source 14. Repeat the operation. In a preferred embodiment, the sound source 14 is a sound source that generates stereo-sampled audio data. In this aspect, when the note-on event data is given, the sound source 14 outputs the sound data B having the sampling frequency f2 including the L and R2 channels representing different waveforms. In another preferred embodiment, the sound source 14 is a sound source that generates monaurally sampled audio data. In this aspect, the sound source 14 generates monaural sound data having a sampling frequency f2 when note-on event data is given. This audio data is distributed to the audio data B of the L and R2 channels at a volume ratio corresponding to the panpot coefficient indicating the position of the sound image localization, and is output from the sound source 14.

  The audio signal processing unit 20 is a device that performs signal processing on the audio data A and B obtained from the digital audio I / F 11 and the sound source 14, respectively, and outputs L and R2 channel digital signals as the processing results. Inside the audio signal processing unit 20, a sampling clock CLK having a frequency fs and a faster operation clock MCLK are generated by a clock generator (not shown). In the audio signal processing unit 20, the signal processing for the audio data A and B is executed using the sampling clock CLK as a trigger each time the sampling clock CLK is generated. Further, the timing control of each part for performing this signal processing is performed in synchronization with the operation clock MCLK. In the present embodiment, the frequency fs of the sampling clock CLK is the same as the sampling frequency f2 of the audio data B. Therefore, the audio data B can be processed in the audio signal processing unit 20 as it is without converting the sampling frequency. The sampling frequency f1 of the audio data A is different from the frequency fs (= f2). For this reason, in the present embodiment, the audio data A is taken into the audio signal processing unit 20 and then subjected to SRC calculation processing for converting the sampling frequency from f1 to fs (= f2). The SRC calculation process will be described later.

  As shown in FIG. 1, the audio signal processing unit 20 includes a data path unit 30, a state machine unit 40, and a mode register 50. The data path unit 30 includes a temporary data storage memory 31 and a calculation unit 32. The temporary data storage memory 31 is used as a buffering area for temporarily storing audio data A and B to be processed and a temporary storage area for temporarily storing digital data during signal processing. The arithmetic unit 32 is a device that performs arithmetic processing on the data read from the temporary data storage memory 31, and includes a multiplier 33, an accumulator 34, and an arithmetic coefficient generation circuit 35. Here, the multiplier 33 is a circuit that multiplies the data read from the temporary data storage memory 31 by a calculation coefficient, and the calculation coefficient generation circuit 35 is a circuit that generates the calculation coefficient. Which calculation coefficient is generated is determined based on the type of calculation to be performed on the data to be processed. The accumulator 34 is a circuit that performs accumulation every time a multiplication result is output from the multiplier 33. The accumulator 34 is configured to be capable of performing a through operation for passing the multiplication result without accumulation, in addition to the operation of accumulating the multiplication result of the multiplier 33. What kind of calculation is performed by the above calculation unit 32, which area of data in the temporary data storage memory 31 is to be calculated, and where the output data of the accumulator 34 as the calculation result is supplied It is determined by a control signal supplied from the machine unit 40.

  A state signal indicating the internal state of the data path unit 30 is supplied to the state machine unit 40. The state machine unit 40 monitors a change in the internal state of the data path unit 30 based on the state signal, and outputs various control processes to the data path unit 30 by outputting a control signal based on the monitoring result. It is a device.

The state machine unit 40 includes calculation processing state machines 41 a to 41 h as means for controlling execution of calculations by the data path unit 30. The arithmetic processing performed by the data path unit 30 under the control of these arithmetic processing state machines is listed as follows.
a. SRC (sampling rate conversion) arithmetic processing This is processing for reading out audio data of the sampling frequency f1 from the temporary data storage memory 31 and converting it into audio data of the sampling frequency fs (= f2). It is executed under the control of 41a.
b. VOL (Volume) Arithmetic Processing This is processing for reading out audio data from the temporary data storage memory 31 and adjusting its volume, and is executed under the control of the arithmetic processing state machine 41b.
c. FADE (Fade) arithmetic processing This is processing for reading out audio data from the temporary data storage memory 31 and temporarily setting the volume to the silent state, and is executed under the control of the arithmetic processing state machine 41c. The
d. MIX (Digital Mix) Arithmetic Processing This is processing for reading out and mixing two types of audio data from the temporary data storage memory 31, and is executed under the control of the arithmetic processing state machine 41d.
e. EQ (Digital Equalizer) Arithmetic Processing This is processing for reading audio data from the temporary data storage memory 31 and performing level adjustment for each frequency band, and is executed under the control of the arithmetic processing state machine 41e.
f. VSP (Virtual Speaker Localization) Calculation Processing This is because, as shown in FIG. 2, L-channel and R-channel audio data is read from the temporary data storage memory 31, and the virtual speakers VSP-L and VSP-R are positioned. The FIR (Finite Impulse Response) filter coefficient sequence prepared together is convolved with each other, and the level is further shifted, and is executed under the control of the arithmetic processing state machine 41f. When the audio data of the L channel and the R channel subjected to the VSP arithmetic processing is D / A converted and output from the left and right speakers SP-L and SP-R, the audio of the L channel and the R channel is as if it were a virtual speaker. An auditory effect as if it was output from VSP-L and VSP-R can be given to the listener.
g. LOAD (data load) arithmetic processing This is processing for temporarily storing the audio data A and B in the buffering area of the temporary data storage memory 31 and transferring these data to the arithmetic processing that requires them. It is executed under the control of the state machine 41g.
h. VSP THRU (VSP through) calculation process This is the process of reading the L channel and R channel audio data from the temporary data storage memory 31 and excluding the FIR filter calculation from the VSP calculation process, that is, performing the shift calculation in FIG. This process is executed under the control of the arithmetic processing state machine 41h.

  The audio signal processing unit 20 in the present embodiment can execute various types of signal processing in which the above arithmetic processes are combined. As shown in FIG. 3, there are n types of signal processing modes that can be executed by the audio signal processing unit 20 in modes 0 to n-1. In the mode register 50 in the audio signal processing unit 20, mode information for designating which of the modes 0 to n-1 to perform signal processing is written. In a preferred embodiment, mode information is written in the mode register 50 in accordance with the operation of the operation unit of the device on which the audio signal processing device 10 is mounted. In another preferred embodiment, a host processor that controls the audio signal processing apparatus 10 writes mode information in the mode register 50 according to software. There is also an embodiment in which the mode register 50 is configured by a nonvolatile memory, and predetermined mode information is written into the mode register 50 at the time of factory shipment.

  The operation stage calling state machine unit 42 is a collection of n operation stage calling state machines for causing the data path unit 30 to execute each signal processing corresponding to modes 0 to n-1 shown in FIG. is there. In the state machine unit 40, among these operation stage calling state machines, an operation stage calling state machine corresponding to the mode specified by the mode information in the mode register 50 is activated each time the sampling clock CLK is generated. The

  An arithmetic stage calling state machine corresponding to each mode is an arithmetic processing state machine corresponding to one or a plurality of arithmetic processes constituting the signal processing in order to cause the data path unit 30 to perform signal processing in that mode. Has a function of sequentially starting up. The arithmetic processing state machine activated by the arithmetic stage calling state machine generates a control signal for causing the data path unit 30 to perform the corresponding arithmetic processing. This control signal is supplied to the data path unit 30 via the arithmetic stage calling state machine.

  In addition, the operation stage calling state machine performs control for appropriately transferring data between the operation processes constituting the signal processing. As shown in FIG. 3, the mode of data delivery between the arithmetic processes constituting the signal processing differs depending on the mode. For example, paying attention to the MIX calculation process, in mode 0, the result of the VOL calculation process and the result of the LOAD calculation process are transferred to the MIX calculation process. In mode 1, the result of the VOL calculation process and the result of the EQ calculation process are transferred to the MIX calculation process. Delivered. In mode 0, the result of the MIX calculation process is transferred to the EQ calculation process. In mode 1, the result of the MIX calculation process is transferred to the VSP calculation process. Therefore, in this embodiment, the operation stage calling state machine corresponding to each mode, when a control signal for performing a certain operation process is sent to the data path unit 30, the location of the data to be subjected to the operation process is determined. A control signal including information indicating the information indicating the storage destination or output destination of the result of the arithmetic processing is sent to the data path unit 30. By such control, the acquisition source of input data and the supply destination of output data of each arithmetic processing are set for each mode, and various signal processing can be performed by the data path circuit having the same configuration.

  In addition to the state machine described above, the state machine unit 40 includes a state machine 43 and a main state machine 44 that controls all the state machines in the state machine unit 40. The state machine 43 is activated by the main state machine 44 when the mode information in the mode register 50 is rewritten, and performs initialization processing of the temporary data storage memory 31. This is because, when the mode is switched, if the calculation processing result in the mode before switching remains in the temporary data storage memory 31, the calculation processing in the mode after switching may be hindered. Because. For example, in arithmetic processing with delay processing such as VSP arithmetic processing, if the temporary data storage memory 31 is not initialized at the time of mode switching, the arithmetic processing result in the mode before switching is the arithmetic processing after switching. The intended result is not obtained. In order to avoid such an inconvenience, the state machine 43 is activated when the mode is switched.

The analog unit 60 in FIG. 1 has a D / A converter as a main component, converts the digital signals for L and R2 channels output from the audio signal processing unit 20 described above into analog signals, respectively, Output to a speaker (not shown in FIG. 1).
The above is the details of the configuration of the audio signal processing apparatus 10 according to the present embodiment.

  Next, the operation of this embodiment will be described. In the operation described below, the processing target of the data path unit 30 is the audio data of the L and R2 channels, but is simply referred to as audio data in order to prevent the explanation from becoming complicated.

  In FIG. 1, when audio data from the source A and performance data from the source B are supplied to the audio signal processing apparatus 10, audio data A having a sampling frequency f1 is output from the digital audio I / F 11 and having a sampling frequency f2. The audio data B is output from the sound source 14 and supplied to the audio signal processing unit 20.

  FIG. 4 is a time chart showing the operation of the audio signal processing unit 20 for processing these audio data. Inside the audio signal processing unit 20, a sampling clock CLK having a frequency fs and an operation clock MCLK faster than this are generated. The audio data A and B are respectively output from the digital audio I / F 11 and the sound source 14 at timings asynchronous with these clocks, and are used for the buffering area for the audio data A and the audio data B in the temporary data storage memory 31. Are stored in each buffering area. In the present embodiment, these buffering areas function as a FIFO. That is, the unread audio data A and B stored in the buffering area are read out in order from the oldest.

  The audio signal processing unit 20 performs signal processing on the audio data A and B each time the sampling clock CLK is generated. More specifically, when the mode indicated by the mode information in the mode register 50 is, for example, mode 0, the audio signal processing unit 20 performs signal processing of mode 0 every time the sampling clock CLK is generated as shown in the figure. LOAD calculation processing, SRC calculation processing, VOL processing, MIX processing, EQ processing, VSP processing, and FADE processing are sequentially executed by time division control.

  FIG. 5 is a time chart showing in detail the signal processing corresponding to mode 0 performed by the audio signal processing unit 20 in a certain sampling period (1 / fs). In mode 0, the operation stage calling state machine corresponding to mode 0 in the operation stage calling state machine unit 42 is activated at the rising edge of the sampling clock CLK. The arithmetic stage calling state machine corresponding to mode 0 first activates the arithmetic processing state machine 41g for the LOAD arithmetic processing. The arithmetic processing state machine 41g generates a control signal for causing the data path unit 30 to perform the LOAD arithmetic processing. This control signal is sent to the data path unit 30 via the operation stage calling state machine corresponding to mode 0. At this time, the state machine for calling the operation stage corresponding to mode 0 receives information indicating the storage area of the oldest unread audio data B and the MIX in the temporary data storage memory 31 to which the audio data B is output. A control signal including information designating an arithmetic processing area is sent to the data path unit 30. When the SRC calculation process needs to be supplemented with the audio data A, the calculation stage calling state machine corresponding to mode 0 includes information indicating the storage area of the audio data A to be read in the LOAD calculation process; A control signal including information specifying an SRC calculation processing area in the temporary data storage memory 31 that is the output destination of the audio data A is sent to the data path unit 30. The state in which the SRC calculation process needs to be supplemented with the audio data A will be described later.

  In the data path unit 30, the LOAD calculation process is performed according to the control signal sent from the state machine unit 40 as described above. More specifically, first, the calculation coefficient generation circuit 35 gives “1” as a calculation coefficient to the multiplier 33. Further, the accumulator 34 is set to the through state. In this state, the audio data B is read from the buffering area for the audio data B in the temporary data storage memory 31. The audio data B passes through the multiplier 33 and the accumulator 34 and is stored in the MIX calculation processing area in the temporary data storage memory 31. In a state where the SRC calculation process requires supplementation of the audio data A, the audio data A is read from the buffering area for the audio data A in the temporary data storage memory 31. The audio data A passes through the multiplier 33 and the accumulator 34 and is stored in the SRC calculation processing area in the temporary data storage memory 31. When the LOAD calculation process is completed in this way, the data path unit 30 sends a state signal indicating that the LOAD calculation process is completed to the state machine unit 40.

  When receiving the state signal, the operation stage calling state machine corresponding to mode 0 activates the operation processing state machine 41a for the SRC operation processing. The arithmetic processing state machine 41a generates a control signal for causing the data path unit 30 to perform SRC arithmetic processing. This control signal will be described in detail later. The control signal for the SRC calculation process is sent to the data path unit 30 via the calculation stage call state machine corresponding to mode 0. At this time, the state machine for calling the operation stage corresponding to mode 0 includes information specifying the SRC operation processing area in the temporary data storage memory 31 as the storage destination of the input data to be subjected to the SRC operation processing, and sampling. A control signal including information specifying a VOL calculation processing area in the temporary data storage memory 31 that is an output destination of the audio data after rate conversion is sent to the data path unit 30.

  In the data path unit 30, the SRC calculation process is executed based on the control signal sent from the state machine unit 40 in this way. FIG. 6 shows the state of this SRC calculation process. In the SRC calculation process, every time a sampling clock CLK having a frequency fs is generated, interpolation is performed to obtain one instantaneous sound waveform value at each sampling point arranged at 1 / fs intervals on the envelope of a series of sound data A generated in the past. An operation is performed. In FIG. 6, the instantaneous value obtained with the generation of the sampling clock CLK at a certain time t1 is indicated by a mark X. This instantaneous value is obtained by convolving a coefficient sequence for interpolation calculation with a predetermined number of audio data A before and after the sampling point. FIG. 6 shows a case where an instantaneous value at a sampling point is obtained by using one piece of audio data Ak after the sampling point and three pieces of audio data Ak-1, Ak-2, and Ak-3 before the sampling point. Illustrated. The phase information Δt is information indicating the phase difference between the sampling point for which the instantaneous value is to be obtained and the generation timing of the immediately preceding audio data Ak-1. The control signal for the SRC calculation process described above includes this phase information Δt. The calculation coefficient generation circuit 35 generates a predetermined coefficient sequence for interpolation calculation corresponding to the phase information Δt, and sequentially supplies each interpolation calculation coefficient to the multiplier 33. In parallel with this operation, the audio data Ak to Ak-3 are read from the SRC calculation processing area of the temporary data storage memory 31 and sequentially supplied to the multiplier 33. The multiplier 33 sequentially multiplies each of the audio data Ak to Ak-3 and the coefficient for interpolation calculation, and the accumulator 34 accumulates the multiplication results. In this way, the coefficient sequence for interpolation calculation is convoluted with the audio data Ak to Ak-3. Then, the voice waveform instantaneous value corresponding to the sampling point at time t1 obtained by this convolution calculation is written in the VOL calculation processing area in the temporary data storage memory 31 as the voice data A after the SRC calculation processing.

  Next, in preparation for the next SRC calculation process, the data path unit 30 obtains phase information Δt corresponding to the sampling point next to the sampling point for which the instantaneous value has been obtained this time, and sends it to the state machine unit 40 as a state signal. . This phase information Δt is sent from the state machine unit 40 to the data path unit 30 as a part of the control signal during the next SRC calculation process. The phase information Δt corresponding to the new sampling point can be obtained, for example, by causing the calculation unit 32 to perform a process of adding the frequency ratio f1 / fs to the current phase information Δt.

  Here, when the phase information Δt exceeds “1” by the addition of the frequency ratio f1 / fs by the addition of the frequency ratio f1 / fs, the voice waveform instantaneous value to be obtained next is the newest in the SRC calculation processing area. This is after the audio data Ak. In this case, in the next SRC calculation process, it is necessary to supplement the new voice data Ak + 1 and use the voice data Ak + 1, Ak, Ak-1, and Ak-2. Therefore, the data path unit 30 indicates that the phase information Δt obtained by subtracting “1” from the phase information Δt after the addition of the frequency ratio f1 / fs and that the audio data Ak + 1 needs to be supplemented in the next sampling period. A state signal including information is sent to the state machine unit 40.

In the operation stage calling state machine corresponding to mode 0 in the operation stage calling state machine unit 42, the state signal sent from the data path unit 30 in this way is stored for the next SRC operation processing. . In addition, the status signal from the data path unit 30 may include information indicating that supplementation of new audio data A is necessary. In this case, when the state machine for calling the operation stage corresponding to mode 0 causes the data path unit 30 to perform the LOAD operation processing in the next sampling period, as described above, information indicating the storage area of the audio data A and The control signal including the information for designating the SRC calculation processing area in the temporary data storage memory 31 that is the output destination of the audio data A is sent to the data path unit 30.
The above is the details of the SRC calculation processing performed by the audio signal processing unit 20.

  The actual sampling frequency f1 of the audio data A varies with time, and the frequency fs of the sampling clock CLK also varies with time. When these time fluctuations are large, when the phase information Δt is obtained by accumulating the fixed value f1 / fs as described above, the phase of the voice waveform instantaneous value calculated by the SRC calculation process and the buffering for the voice data A There is a possibility that the phase difference from the phase of the audio data A written in the area increases with time, and overflow or underflow of the buffering area may occur. In order to avoid such inconvenience, the remaining amount of unread audio data A in the buffering area is monitored, and when the remaining amount is smaller than a predetermined value, the increment added to the phase information Δt is reduced every sampling period. It is desirable to prevent underflow and to prevent overflow by increasing the increment added to the phase information Δt when the remaining amount is larger than a predetermined value. This technique is disclosed in, for example, Patent Document 2 filed by the present applicant.

JP-A-11-55075

  When the operation stage calling state machine corresponding to mode 0 in the operation stage calling state machine unit 42 detects the end of the SRC operation processing based on the status signal from the data path unit 30, the operation stage calling state machine is used for the operation processing for the VOL operation processing. The state machine 41c is activated. The arithmetic processing state machine 41 c generates a control signal for causing the data path unit 30 to perform VOL arithmetic processing. This control signal is sent to the data path unit 30 via the operation stage calling state machine corresponding to mode 0. At this time, the state machine for calling the operation stage corresponding to mode 0 is used to store temporary data as an output destination of information indicating the location of input data to be subjected to VOL operation processing and audio data obtained as a result of VOL operation processing. A control signal including information specifying the MIX calculation processing area in the memory 31 is sent to the data path unit 30.

  In the data path unit 30, in accordance with the control signal sent from the state machine unit 40 as described above, the VOL calculation process is performed as follows. First, the audio data A after the SRC calculation processing is read from the VOL calculation processing area in the temporary data storage memory 31. The arithmetic unit 32 performs VOL arithmetic processing on the audio data, and the audio data obtained as a result is stored in the MIX arithmetic processing area in the temporary data storage memory 31. When the VOL calculation process is completed in this way, the data path unit 30 sends a status signal to that effect to the state machine unit 40.

  When the operation stage calling state machine corresponding to mode 0 in the operation stage calling state machine unit 42 detects the end of the VOL operation process from the status signal from the data path unit 30, the operation stage calling state machine is used for the operation process for the MIX operation process. The state machine 41d is activated. The arithmetic processing state machine 41d generates a control signal for causing the data path unit 30 to perform the MIX arithmetic processing. This control signal is sent to the data path unit 30 via the operation stage calling state machine corresponding to mode 0. At that time, the state machine for calling the operation stage corresponding to mode 0 is used for storing temporary data as an output destination of information indicating the location of the input data to be subjected to the MIX operation processing and the audio data obtained as a result of the MIX operation processing. A control signal including information for designating an EQ calculation processing area in the memory 31 is sent to the data path unit 30.

  In the data path unit 30, the MIX calculation process is performed according to the control signal transmitted from the state machine unit 40 as described above. In this MIX calculation process, audio data A and B stored in the MIX calculation processing area in the temporary data storage memory 31 are processed. Here, since the audio data A has undergone the SRC calculation process described above, it is sample data having the same sampling frequency f2 as that of the audio data B. Therefore, in the MIX calculation process, it is only necessary to perform weighted addition of these audio data. Hereinafter, the operation will be described.

First, the audio data A is read from the MIX calculation processing area, and the mixing coefficient for determining the weight of the audio data A is output from the calculation coefficient generation circuit 35, and both are supplied to the multiplier 33. The multiplier 33 multiplies the audio data A and the mixing coefficient, and the multiplication result is given to the accumulator 34 and stored therein. Next, the audio data B is read from the MIX calculation processing area in the temporary data storage memory 31, and the mixing coefficient that determines the weight of the audio data B is output from the calculation coefficient generation circuit 35. Given to. The multiplier 33 multiplies the audio data B and the mixing coefficient, and the multiplication result is given to the accumulator 34. The accumulator 34 performs an accumulation process for adding the multiplication result to already stored data. By this accumulation process, audio data obtained by mixing the audio data A and B is obtained. The audio data after the mixing processing is stored in the EQ calculation processing area in the temporary data storage memory 31. When the mixing calculation process is completed in this way, the data path unit 30 sends a state signal indicating that to the state machine unit 40.
Thereafter, the VSP calculation process and the FADE calculation process are basically advanced under the same control as described above.

  When the final FADE operation process is executed, the operation stage calling state machine corresponding to mode 0 sends information specifying the analog unit 60 to the data path unit 30 as the output destination of the FADE operation process result. The data path unit 30 sends the result of the FADE calculation process to the analog unit 60 according to this information.

  When the final FADE calculation process is completed, the audio signal processing unit 20 enters the IDLE state. In this IDLE state, the data path unit 30 does not perform any signal processing operation, so that the power consumption of the audio signal processing apparatus 10 as a whole is small.

Thereafter, when the sampling clock CLK is generated and a new sampling period is started, the signal processing in mode 0 from the LOAD calculation process to the FADE calculation process is executed again as shown in FIG.
The above processing is repeated each time the sampling clock CLK is generated, and an analog signal that has undergone signal processing in mode 0 shown in FIG. 3 is generated in the analog unit 60 and output as sound from the left and right speakers.

  Even when mode information designating another mode is stored in the mode register 50, signal processing of the mode is performed by the same control as described above. FIG. 7 shows the operation of the audio signal processing unit 20 when the signal processing in mode 1 shown in FIG. 3 is performed. When FIG. 7 is compared with FIG. 5, the positions of the MIX calculation processing area and the EQ calculation processing area are interchanged. However, this is illustrated by switching in order to prevent the illustration from becoming complicated, and the MIX calculation processing area and the EQ calculation processing area are not actually switched.

  In the above-described signal processing in mode 0, each arithmetic processing is started in the order of LOAD, SRC, VOL, MIX, EQ, VSP, and FADE by the operation of the state machine for calling the arithmetic stage corresponding to mode 0. On the other hand, in the signal processing in mode 1, each arithmetic processing is started in the order of LOAD, SRC, VOL, EQ, MIX, VSP, and FADE by the operation of the state machine for operation stage corresponding to mode 1. Further, the data transfer between the respective arithmetic processes is performed in a mode different from that in the mode 0 by the operation of the arithmetic stage calling state machine corresponding to the mode 1.

  As described above, the audio signal processing apparatus 10 according to the present embodiment can perform a plurality of types of signal processing with different contents by using the common data path unit 30, and can perform desired signal processing. By writing the corresponding mode information in the mode register 50, the signal processing can be performed by the audio signal processing unit 20. Therefore, the audio signal processing apparatus 10 having many specifications with different types of signal processing can be realized with one chip. Further, in the audio signal processing device 10 according to the present embodiment, the data path unit 30 operates completely during the period from when the sampling cycle starts and after the signal processing corresponding to the mode information is executed until the next sampling cycle starts. No IDLE state. In addition, in the signal processing corresponding to the mode information, the data path unit 30 performs only the operation for performing the signal processing. Therefore, according to the present embodiment, unnecessary operations for signal processing are avoided, so that unnecessary power consumption can be eliminated and power consumption can be kept low. Therefore, it can be mounted on a portable electronic device that requires low power consumption, such as a mobile phone, and a high-quality audio signal processing function can be provided in these devices.

Second Embodiment
The configuration of the audio signal processing apparatus according to the present embodiment is basically the same as that of the first embodiment shown in FIG. In the first embodiment, the operation stage calling state machine unit 42 is an aggregate of a plurality of operation calling state machines respectively corresponding to modes 0 to n-1. The operation stage calling state machine unit 42 in this embodiment is a single state machine, and controls the data path unit 30 and performs state transition according to the determination table shown in FIG. FIG. 9 is a state transition diagram showing the operation.

As shown in FIG. 9, the operation stage calling state machine unit 42 determines the control content of the data path unit 30 based on the current state and mode (steps S1 and S2). For example, when the SRC operation process by the data path unit 30 is currently controlled and the mode is mode 0, the operation stage calling state machine unit 42 sends a control signal instructing the SRC operation process to the data path unit 30. Send to. At that time, the arithmetic stage calling state machine unit 42 sends to the data path unit 30 a control signal for designating a VOL arithmetic processing area as an output destination of data obtained by the SRC arithmetic processing in accordance with the determination table of FIG. Then, when the operation stage calling state machine unit 42 detects the end of the SRC operation process from the state signal from the data path unit 30, it shifts to a state for controlling the VOL operation process according to the determination table of FIG. Step S3). When the VOL calculation process is controlled, the data path unit 30 is controlled again based on the current state (in this case, the VOL calculation process is controlled) and the mode (steps S1 and S2). .
Also in this embodiment, the same effect as the first embodiment can be obtained.

<Other embodiments>
The first embodiment and the second embodiment of the present invention have been described above. In addition to the above, the present invention includes the following embodiments.
(1) The allocation of the area in the temporary data storage memory used in each arithmetic processing may be changed for each mode. For example, in a mode in which the types of arithmetic processing to be executed are small, a mode in which the capacity of an area allocated to each arithmetic processing is increased compared to a mode in which the types of arithmetic processing to be executed are large.
(2) When the mode switching is not performed dynamically, the state machine 43 for initializing the temporary data storage memory and the main state machine 44 are unnecessary, and may be omitted.

1 is a block diagram showing a configuration of an audio signal processing device 10 according to a first embodiment of the present invention. It is a figure which shows the content of the VSP calculation process performed in the same embodiment. It is a figure which shows the example of the signal processing which can be performed in the embodiment. It is a time chart which shows operation | movement of the embodiment. It is a time chart which shows operation | movement of the embodiment. It is a time chart which shows the SRC calculation process in the same embodiment. It is a time chart which shows operation | movement of the embodiment. It is a figure which shows the judgment table used in the audio signal processing apparatus which is 2nd Embodiment of this invention. It is a state transition diagram showing the operation of the same embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Audio signal processing apparatus, 20 ... Audio signal processing part, 30 ... Data path part, 40 ... State machine part, 41a-41h ... State machine for arithmetic processing, 42 ... State machine for calling an arithmetic stage 50: Mode register, 11: Digital audio I / F, 12: CPU I / F, 13: Sequencer, 14: Sound source, 31: Temporary data storage memory, 32: Arithmetic unit, 33... Multiplier, 34... Accumulator, 35.

Claims (6)

A data path unit for performing arithmetic processing on the audio signal;
A mode register for storing mode information specifying signal processing to be executed;
An audio signal processing apparatus comprising: a state machine unit that sequentially outputs a control signal that causes the data path unit to execute one or more arithmetic processes constituting signal processing specified by mode information stored in the mode register.   The audio signal processing apparatus according to claim 1, wherein the state machine unit outputs information indicating a location of input data to be subjected to each arithmetic processing and information indicating an output destination of a result of each arithmetic processing as the control signal. A plurality of interfaces for receiving an audio signal from the outside or generating an audio signal based on a signal given from the outside and supplying the audio signal to the data path unit;
2. The audio according to claim 1, wherein the state machine unit includes means for generating a control signal for causing the data path unit to perform arithmetic processing for converting the format of the audio signal supplied to the data path unit into a predetermined format. Signal processing device.   4. The audio signal processing apparatus according to claim 3, wherein the state machine unit includes means for generating a control signal for causing the data path unit to perform arithmetic processing for mixing a plurality of audio signals of the same format in the data path unit. .   2. The state machine unit generates a control signal for causing the data path circuit to execute signal processing specified by mode information stored in the mode register every time a clock having a predetermined period is given. Audio signal processing device. The data path unit includes means for sending a state signal indicating a state of an operation process being executed to the state machine unit,
6. The audio signal processing apparatus according to claim 5, wherein the state machine unit determines a content of a control signal to be sent to the data path unit when a next clock is given based on the state signal.

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