JP4075768B2 - Audio signal processing device - Google Patents

Description

  The present invention relates to an audio signal processing apparatus that performs various kinds of acoustic processing on an audio signal.

Audio signal processing apparatuses that can perform various types of signal processing on audio data of a plurality of channels have become widespread. This type of audio signal processing apparatus can be broadly divided into two types when focusing on the configuration for signal processing. As shown in FIG. 4, the first audio signal processing apparatus has a data path for signal processing for each channel, and performs signal processing on audio data of each channel in parallel. As shown in FIG. 5, the second audio signal processing apparatus has a single data path common to each channel, and uses this single data path to time-divide signal processing for audio data of each channel. Sequentially executed under control. As a technical document disclosing the second audio signal processing apparatus, there is, for example, Patent Document 1.
JP 2000-122650 A

  According to the first audio signal processing device described above, power consumption can be reduced by stopping data paths of unused channels. However, since this audio signal processing apparatus must be provided with a data path for each channel, there is a problem that the apparatus becomes large-scale and the chip area becomes large when realized by an LSI. According to the second audio signal processing apparatus, since only a single data path needs to be provided, the apparatus can be small-scaled, and the chip area can be reduced when realized by an LSI. However, since this audio signal processing device always performs operations on all channels even if only some channels of audio data are input, it performs operations that are not necessary and consumes unnecessary power. There was a problem that.

  The present invention has been made in view of the circumstances described above, and it is an object of the present invention to provide a multi-channel audio signal processing apparatus that can be configured in a small scale and can reduce power consumption. And

In order to solve the above problems, the present invention is based on a plurality of interfaces each receiving a plurality of channels of audio data, and a plurality of channels of audio data input via the plurality of interfaces. A detection unit that detects whether each channel is in an activated state or a stopped state, and outputs a channel state signal, a memory for temporarily storing audio data of the plurality of channels, and the memory Means for performing signal processing on the audio data of the plurality of channels read out from the time-division control, specifying the state of each channel based on the channel state signal output by the detection unit, and for the channel in the activated state Performs only signal processing on audio data, and on audio data of channels that are stopped Providing an audio signal processing apparatus having an audio signal processing unit for stopping the issue process.
According to the present invention, the detection unit detects whether each channel is in the activated state or the stopped state, and the audio signal processing unit performs only signal processing on the audio data of the channel in the activated state, The signal processing for the audio data of the channel is stopped. Therefore, useless signal processing can be avoided and power consumption associated with signal processing can be kept low.
In a preferred aspect, the detection unit outputs a channel state signal indicating that the channel is in a stopped state when the audio data of one channel is interrupted for a predetermined time or more.
According to such an aspect, when audio signal processing of a certain channel is interrupted when delay-type signal processing such as reverberation processing is performed in the audio signal processing unit, at the appropriate timing after the predetermined time has elapsed, Channel signal processing stops. Therefore, it is possible to avoid the problem that the reverberation process or the like is interrupted during the execution.
In another preferred aspect, the detection unit outputs a first channel state signal when the state where the sound data of one channel is interrupted continues for a first time or more, and the state where the sound data is interrupted When the audio signal processing unit outputs a second channel state signal when continuing for a second time longer than the first time, the audio signal processing unit outputs a first channel state signal for the certain channel from the detection unit. The predetermined type of signal processing among the signal processing corresponding to the channel is stopped, and when the second channel state signal is output, execution of the entire signal processing corresponding to the channel is stopped.
According to this aspect, for the predetermined type of signal processing that may be interrupted when the audio data is interrupted, the signal processing is stopped when the audio data is interrupted and the first channel state signal is output. The other signal processing is stopped when the voice data has been interrupted for a predetermined time or longer. Accordingly, the power consumption can be further reduced as compared with the aspect described above.

<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of an audio signal processing apparatus 10 according to the first embodiment of the present invention. The audio signal processing apparatus 10 is an LSI formed by forming circuits corresponding to the respective components shown in the figure on a semiconductor chip, and is mounted on various audio devices that require functions such as an effector function and a mixing function.

  The audio signal processing apparatus 10 according to the present embodiment has a CH0 interface 70 corresponding to channel 0, a CH1 interface 71 corresponding to channel 1, and a CH2 interface corresponding to channel 2 as interfaces for inputting audio data into the apparatus. 72 respectively. Each of these interfaces 70 to 72 may receive data output from the same source, or may receive data output from different sources. Each of these interfaces 70 to 72 may handle data in the same format or may handle data in different formats. For example, one interface receives and outputs audio data that is sample data of an audio waveform, and the other interface receives performance data such as MIDI, and generates and outputs audio data according to the performance data. There can also be an aspect of.

  The channel activation / deactivation detection circuit 50 detects whether each channel is activated or deactivated from the audio data input via the interfaces 70 to 72 of each channel, and indicates the result. Output a status signal.

  Here, the channel start / stop detection circuit 50 does not determine that the channel is in a stopped state immediately after the voice data indicating silence is input, but receives voice data indicating silence. Thereafter, when the state in which no audio data is input continues for a predetermined period, it is determined that the channel has reached a stop state. This is because if the channel state signal indicating the stop state is immediately output, the signal processing that has been performed on the voice data that has already been input in the previous sampling cycle may be interrupted. It is. How much it is most desirable to set a period that serves as a standard for determining that the stop state has been reached will be described in detail later.

  The audio signal processing unit 20 is a device that performs signal processing on audio data input via each of the interfaces 70 to 72 and outputs digital signals of L and R2 channels, which are the processing results. The analog unit 60 includes a D / A converter as a main component, converts the digital signals for L and R2 channels output from the audio signal processing unit 20 into analog signals, and outputs left and right speakers (not shown). Output to.

  As shown in FIG. 1, the audio signal processing unit 20 includes a data path unit 30 and a state machine unit 40. The data path unit 30 includes a temporary data storage memory 31 and a calculation unit 32.

  The temporary data storage memory 31 is used as a temporary storage area for temporarily storing audio data to be processed and digital data in the middle of signal processing. Here, since the signal processing executed by the audio signal processing apparatus 10 includes so-called delayed signal processing, the temporary data storage memory 31 has a storage area for storing n pieces of audio data. FIFO (first-in first-out) is secured. The number n of audio data that can be stored in the FIFO is preset according to the ratio between the longest delay time and the sampling period.

  As described above, the channel activation / deactivation detection circuit 50 determines that the channel is in the stopped state only when the voice data indicating that there is no sound is input and the state in which the voice data is not input continues for a predetermined period. It is most desirable that the period serving as a standard for determining the state is set longer than the above-described longest delay time. In delay system signal processing such as reverberation, a specific area of the temporary data storage memory 31 is used as a FIFO (First-In First-Out) for delaying audio data, and the FIFO is used every time the sampling period elapses. Since the calculation using the audio data in the FIFO is sequentially performed while sequentially shifting the audio data in the storage area to the rear, even if the input of the audio data is interrupted, there is a certain time lag until all the signal processing is completed. appear. Therefore, by setting the period for determining the stop state as slightly longer than the time until all the audio data in the temporary data storage memory 31 is cleared, the signal processing for the already input audio data is stopped halfway. You can avoid such a situation.

  The arithmetic unit 32 is a device that performs arithmetic processing on the data read from the temporary data storage memory 31, and includes a multiplier 33, an accumulator 34, and an arithmetic coefficient generation circuit 35. Here, the multiplier 33 is a circuit that multiplies the data read from the temporary data storage memory 31 by a calculation coefficient, and the calculation coefficient generation circuit 35 is a circuit that generates the calculation coefficient. The accumulator 34 is a circuit that performs accumulation every time a multiplication result is output from the multiplier 33. What calculation coefficient is generated by the calculation coefficient generation circuit 35, what calculation is performed by the multiplier 33 and the accumulator 34, which region in the temporary data storage memory 31 is subject to calculation, and calculation Where to output the result is all determined by the control signal supplied from the state machine unit 40 (specifically, the state machine for arithmetic processing).

  The state machine unit 40 is a device that performs control for state transition of the data path unit 30. A state signal indicating the internal state of the data path unit 30 is supplied to the state machine unit 40, and a change in the internal state of the data path unit 30 is monitored based on the state signal. Then, by outputting a control signal based on the monitoring result to the data path unit 30, various signal processes are performed.

  As shown in FIG. 1, the state machine unit 40 includes arithmetic processing state machines 41 to 43 respectively corresponding to channels 0 to 2, and a main state machine 44 that generalizes these arithmetic processing state machines. ing. Here, the arithmetic processing state machines 41 to 43 are state machines that respectively control the data path unit 30 for performing signal processing of the audio data of the channels 0 to 2. More specifically, the arithmetic processing state machines 41 to 43, when activated by the main state machine 44, store temporary data that stores arithmetic coefficients to be generated by the arithmetic coefficient generation circuit 35 and data to be calculated. A series of control signals for designating the address of the memory 31, the calculation contents to be executed by the multiplier 33 and the accumulator 34, the output destination of the calculation result, etc. are sequentially output according to a preset procedure. These series of signals are sequentially output in synchronization with the main clock generated in the audio signal processing unit 20.

  The main state machine 44 sequentially starts up these arithmetic processing state machines 41 to 43 in a predetermined order in each sampling period. However, when a channel state signal indicating that a specific channel has been stopped in a certain sampling period is output from the channel activation / deactivation detection circuit 50, the main state machine 44 transmits to that channel in the next sampling period. The activation of the corresponding arithmetic processing state machine is skipped, and the state machine unit 40 is shifted to the next state. The operation of skipping the signal processing control corresponding to the channel in the stopped state is repeated until a channel state signal indicating that the channel has returned to the activated state is output from the channel activation / deactivation detection circuit 50.

  The relationship between the state transition of the state machine unit 40 and the processing by the calculation unit 32 will be described with reference to FIGS. FIG. 2A is a diagram showing state transition of the state machine unit 40 in a sampling cycle in which all channels are in an activated state, and FIG. 2B is a main state machine 44 in a sampling cycle in which channel 1 is in a stopped state. It is a figure which shows the state transition of. In these drawings, “CH0” indicates a state in which the arithmetic processing state machine 41 controls the data path unit 30 so that the signal processing of the audio data of channel 0 is performed, and “CH1” indicates the audio of channel 1 A state machine 42 that controls the data path unit 30 so that signal processing of data is performed, “CH2” is a state machine for processing so that signal processing of audio data of channel 2 is performed 43 shows a state in which the data path unit 30 is controlled. Further, “IDLE” indicates a state in which no arithmetic processing state machine is activated and no signal processing is performed in the data path unit 30.

  When all the channels are in the activated state, as shown in FIG. 2A, the state of the state machine unit 40 shifts from the “IDLE” state to the “CH0” state at the start of the sampling period. After the transition from “CH1” to “CH2”, the state returns to the “IDLE” state. Therefore, in this sampling period, as shown in FIG. 3A, signal processing is performed on all sample data of CH0, CH1, and CH2.

  When channel 1 is in a stopped state, as shown in FIG. 2B, the state transition of the state machine unit 40 is “IDLE” → “CH0” → “CH2” because the “CH1” state is skipped. After the transition, return to “IDLE”. Therefore, in this sampling period, as shown in FIG. 3B, signal processing is performed on the audio data of channel 0 and channel 2, while signal processing is not performed on the audio data of channel 1. Since the signal processing for the audio data of channel 1 is skipped, the period of the “IDLE” state is lengthened, and the power consumption is reduced accordingly.

  The same applies when a channel state signal indicating that channel 0 or channel 2 has been stopped is output from the channel start / stop detection circuit 50, and the main state machine 44 performs an operation corresponding to the channel in the stopped state. Skips the processing state machine startup. As a result, it is not necessary to perform computation on the channel in the stopped state, so that power consumption required for signal processing computation can be reduced. Therefore, it can be mounted on a portable electronic device that requires low power consumption, such as a mobile phone, and a high-quality audio signal processing function can be provided in these devices.

Second Embodiment
In the first embodiment, the execution of the signal processing for a channel is stopped when the state in which the audio data of a certain channel is interrupted continues for a predetermined time or longer. On the other hand, in the present embodiment, the following operation is performed. First, the channel activation / deactivation detection circuit 50 outputs a first channel state signal when input of audio data indicating silence for a certain channel continues for a first time or more. Then, when input of audio data indicating silence for the same channel continues for a second time longer than the first time, a second channel state signal is output. This second time is the same time as the duration of the silent state when it is determined that the channel has been stopped in the first embodiment. The arithmetic processing state machines 41 to 43 of the state machine unit 40 skip signal processing in accordance with the channel state signal as in the first embodiment, but the aspect is that the first channel state signal is output. And when the second channel state signal is output.

  For example, when the channel 0 is in the activated state, the main state machine 44 activates the arithmetic processing state machine 41 corresponding to the channel 0. In order for this arithmetic processing state machine 41 to perform signal processing of channel 0, the state of the data path unit 30 changes from “processing 1” → “processing 2” → “processing 3” → “processing 4” → “IDLE”. Shall be transitioned. In this state, when the first channel state signal corresponding to channel 0 is output, the arithmetic processing state machine 41 skips, for example, “processing 2” not including delay processing. Thereafter, when the second channel state signal is output for the channel 0, the main state machine 44 skips the activation of the arithmetic processing state machine 41 corresponding to the channel 0. As a result, all signal processing corresponding to channel 0 is stopped. After that, when channel 0 audio data indicating sound is input and a channel state signal indicating that is output, the main state machine 44 activates the arithmetic processing state machine 41 in the subsequent sampling period, and the channel The signal processing corresponding to 0 is resumed.

  Thus, in this embodiment, since it was set as the structure which switches starting and a stop in each processing unit performed under control of the arithmetic processing state machines 41-43, for example, it is silent like an equalizer process. The processing that may be stopped immediately after the audio data is input is stopped immediately when the first channel state signal is output, and the data stored in the temporary data storage memory 31 as in the delay system processing. For a process in which it is desired to stop after waiting for all of them to be cleared, an operation such as stopping when a second channel state signal is output after that can be performed. As a result, unnecessary calculations can be skipped with a finer time resolution, and the power consumption required for signal processing can be further reduced.

1 is a block diagram showing a configuration of an audio signal processing device 10 according to a first embodiment of the present invention. It is a figure which shows the state transition of the apparatus. It is a figure which shows the behavior of the calculating part in the same apparatus. It is a figure which shows the circuit structure of a prior art. It is a figure which shows the circuit structure of a prior art.

Explanation of symbols

10: Audio signal processing device, 20: Audio signal processing unit, 30: Data path unit, 31: Temporary data storage memory, 32: Calculation unit, 33: Multiplier, 34: Accumulator, 35: Calculation coefficient generation circuit 40: State machine section, 41-43: State machine for arithmetic processing, 44: Main state machine, 50: Channel start / stop detection circuit, 60: Analog section

Claims (3)

A plurality of interfaces each receiving multi-channel audio data;
A detection unit that outputs a channel state signal indicating a state of each channel from voice data of a plurality of channels input through the plurality of interfaces;
A memory for temporarily storing the audio data of the plurality of channels;
Channels that execute signal processing on the audio data of the plurality of channels read from the memory by time-sharing control, specify a state of each channel based on a state signal output by the detection unit, and are in an activated state An audio signal processing apparatus comprising: an audio signal processing unit that executes only signal processing on the audio data of the channel and stops signal processing on the audio data of the channel in the stopped state.   The audio signal processing apparatus according to claim 1, wherein the detection unit outputs a channel state signal indicating that the channel is in a stopped state when audio data of one channel is interrupted for a predetermined time or more. The detection unit outputs a first channel state signal when the state where the sound data of one channel is interrupted continues for a first time or longer, and the state where the sound data is interrupted is longer than the first time. Outputs a second channel state signal if continued for a second time or more;
When the first channel state signal is output from the detection unit for a certain channel, the audio signal processing unit stops a predetermined type of signal processing in the signal processing corresponding to the channel, and the second channel state 2. The audio signal processing apparatus according to claim 1, wherein when the signal is output, execution of the entire signal processing corresponding to the channel is stopped.

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