JP2005136220A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2005136220A
JP2005136220A JP2003371053A JP2003371053A JP2005136220A JP 2005136220 A JP2005136220 A JP 2005136220A JP 2003371053 A JP2003371053 A JP 2003371053A JP 2003371053 A JP2003371053 A JP 2003371053A JP 2005136220 A JP2005136220 A JP 2005136220A
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semiconductor element
wiring board
semiconductor device
reinforcing frame
semiconductor
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JP4398223B2 (en
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Kazutaka Maeda
和孝 前田
Shoichi Nakagawa
彰一 仲川
Tomoko Tajiri
智子 田尻
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can keep a firm and stable connection state with an external circuit board over a long period. <P>SOLUTION: The semiconductor device consists of a wiring board 2, having a supporting frame 4 on an upper surface; a semiconductor element 1 which has a solder bump 5 on the bottom surface and which is mounted to the upper surface of a wiring board 2 by a flip-chip via the solder bumps; and a heat radiation plate 3 which is arranged so as to cover the upper surface of the wiring board 2, and which is stuck and fixed to the support frame 1 and the semiconductor element 1. On the upper surface of the wiring board 2, between the semiconductor element 1 and the supporting frame 4, a reinforced frame 10 is provided so as to surround the semiconductor element 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体素子が搭載された配線基板からなる半導体装置に関するものであり、特に配線基板の半導体素子搭載面には、支持フレームを介して放熱板が設けられている半導体装置に関するものである。   The present invention relates to a semiconductor device including a wiring board on which a semiconductor element is mounted, and more particularly to a semiconductor device in which a heat sink is provided on a semiconductor element mounting surface of the wiring board via a support frame. .

半導体素子が搭載された配線基板からなる半導体装置は、半導体収納パッケージとも呼ばれることがあり、各種電子機器などの回路基板に広く使用されている。このような半導体装置において、半導体素子の動作による温度上昇を回避するために、配線基板の半導体素子搭載面に、支持フレームを介して放熱板を設けた構造のものが知られている（例えば特許文献１参照）。   A semiconductor device including a wiring board on which a semiconductor element is mounted is sometimes called a semiconductor storage package, and is widely used for circuit boards of various electronic devices. In such a semiconductor device, in order to avoid a temperature rise due to the operation of the semiconductor element, a structure in which a heat sink is provided on the semiconductor element mounting surface of the wiring board via a support frame is known (for example, a patent) Reference 1).

この特許文献１に記載されているような半導体装置は、図３に示すような構造を有している。   The semiconductor device described in Patent Document 1 has a structure as shown in FIG.

この半導体装置は、いわゆるＢＧＡ（Ball Grid Array)タイプのものであり、大まかにいって、半導体素子（半導体チップ）２１、配線基板２２、リッド（放熱板）２３等から構成されている。   This semiconductor device is of a so-called BGA (Ball Grid Array) type, and roughly comprises a semiconductor element (semiconductor chip) 21, a wiring board 22, a lid (heat radiating plate) 23, and the like.

即ち、半導体素子２１は、その底面に複数の半田バンプ２５が設けられており、この半田バンプ２５を、配線基板２２の上面に形成された接続配線パターンに半田溶融しフリップチップ実装することにより、半導体素子２１は配線基板２２に搭載される。また、半導体素子２１と配線基板２２との接続部には、熱硬化性樹脂からなるアンダーフィル２６が充填され、硬化されている。   That is, the semiconductor element 21 is provided with a plurality of solder bumps 25 on the bottom surface thereof, and the solder bumps 25 are solder-melted to a connection wiring pattern formed on the upper surface of the wiring substrate 22 and flip chip mounted. The semiconductor element 21 is mounted on the wiring board 22. In addition, an underfill 26 made of a thermosetting resin is filled in the connecting portion between the semiconductor element 21 and the wiring board 22 and cured.

配線基板２２は、生産コストが安価であり、薄肉化が容易な樹脂製絶縁基板に所定の配線パターン（図３において省略）を形成したものである。   The wiring board 22 is obtained by forming a predetermined wiring pattern (omitted in FIG. 3) on a resin insulating board that is inexpensive in production and easily thinned.

この配線基板２２の下面には、外部接続端子となるボール（半田ボール）２７が配設されている。また、配線基板２２上面に形成された配線パターンと、その下面に形成された半田ボール２７の接合部とは、配線基板２２の内部に配設されたビアホール導体（図示せず）により電気的に接続された構成となっており、配線基板２２の上面に搭載された半導体素子２１と半田ボール２７とは導通している。   Balls (solder balls) 27 serving as external connection terminals are disposed on the lower surface of the wiring board 22. Further, the wiring pattern formed on the upper surface of the wiring board 22 and the joint portion of the solder ball 27 formed on the lower surface thereof are electrically connected by a via-hole conductor (not shown) disposed inside the wiring board 22. The semiconductor element 21 mounted on the upper surface of the wiring board 22 and the solder ball 27 are electrically connected.

また、図３から明らかな通り、リッド２３は、半導体素子２１で発生する熱を放熱する放熱板として機能するものであり、平板形状で配線基板２２の上面全体を覆うように配置されており、熱伝導性の高い金属材料により形成されている。このリッド２３と半導体素子２１との間には伝熱性の良好なペースト材２８によって接着されている。   Further, as is apparent from FIG. 3, the lid 23 functions as a heat radiating plate that radiates heat generated in the semiconductor element 21, and is arranged so as to cover the entire upper surface of the wiring board 22 in a flat plate shape. It is made of a metal material having high thermal conductivity. The lid 23 and the semiconductor element 21 are bonded by a paste material 28 having good heat conductivity.

また、半導体素子２１が搭載される配線基板２２の上面の周縁部には、支持フレーム２９が設けられており、上記のリッド２３は、この支持フレーム２９の上端に接着剤３０により接着固定されており、これにより、リッド２３が安定に保持され、その機械的安定性が高められている。
特開２００１−１１０９２６号公報 A support frame 29 is provided on the peripheral edge of the upper surface of the wiring board 22 on which the semiconductor element 21 is mounted. The lid 23 is bonded and fixed to the upper end of the support frame 29 with an adhesive 30. Thus, the lid 23 is stably held and its mechanical stability is enhanced.
JP 2001-110926 A

ところで、現在では、半導体素子の動作周波数の向上にともない、配線基板を薄型化して配線基板内の配線長さを短くする傾向がある。しかしながら、上記のような従来構造の半導体装置（パッケージ）では、配線基板の厚みを薄くして外部回路基板に実装すると、配線基板と外部回路基板との半田接合部（図３における半田バンプ２７）が、半導体素子のＯＮ／ＯＦＦ等による熱履歴の繰り返しにより、熱疲労破壊してしまい、信頼性要求を満たすことが出来ないという問題がある。これは、シリコンを主とする半導体素子の熱膨張係数が約３×１０-6／℃であるのに対し、配線基板を構成する樹脂製絶縁基板の熱膨張係数が１５〜１８×１０-6／℃であり、熱膨張係数の差が非常に大きいことに起因している。即ち、温度サイクル試験によって、−４０℃から１２５℃の温度変化を与えると、半導体素子と配線基板との熱膨張差を緩和しようとして配線基板に上に凸の反り変形を生じる。この反り変形にともない、外部回路基板との接合部の半田バンプが繰り返し変形してしまうため、半田バンプが熱疲労破壊してしまうのである。配線基板が厚い場合には反りに伴う変形量も小さいが、基板が薄くなるにつれて基板の変形量は大きくなり、熱疲労寿命は短くなる。 Now, with the improvement of the operating frequency of semiconductor elements, there is a tendency that the wiring board is made thinner and the wiring length in the wiring board is shortened. However, in the semiconductor device (package) having the conventional structure as described above, when the wiring board is thinned and mounted on the external circuit board, the solder joint portion (solder bump 27 in FIG. 3) between the wiring board and the external circuit board. However, there is a problem that the thermal fatigue failure due to the repetition of the thermal history due to ON / OFF of the semiconductor element, etc., cannot satisfy the reliability requirement. This is because the thermal expansion coefficient of the semiconductor element mainly composed of silicon is about 3 × 10 −6 / ° C., whereas the thermal expansion coefficient of the resin insulating substrate constituting the wiring board is 15 to 18 × 10 −6. This is because the difference in thermal expansion coefficient is very large. That is, when a temperature change of −40 ° C. to 125 ° C. is given by the temperature cycle test, a convex warpage deformation is generated on the wiring board in an attempt to alleviate the thermal expansion difference between the semiconductor element and the wiring board. Along with this warp deformation, the solder bump at the joint with the external circuit board is repeatedly deformed, and the solder bump is thermally fatigued. When the wiring substrate is thick, the amount of deformation accompanying warping is small, but as the substrate becomes thinner, the amount of deformation of the substrate increases and the thermal fatigue life becomes shorter.

したがって、本発明の目的は、外部回路基板と長期にわたり強固で安定な接続状態を維持できる半導体装置を提供することを目的とするものである。   Accordingly, an object of the present invention is to provide a semiconductor device capable of maintaining a strong and stable connection state with an external circuit board for a long period of time.

本発明によれば、上面に支持フレームを有する配線基板と、底面に半田バンプを有し且つ該半田バンプを介して配線基板の上面にフリップチップ実装された半導体素子と、配線基板の上面を覆うように配置され且つ前記支持フレーム及び半導体素子に接着固定された放熱板とからなる半導体装置において、
前記配線基板の上面には、前記半導体素子と支持フレームとの間に、該半導体素子を取り囲むように補強フレームが設けられていることを特徴とする半導体装置が提供される。 According to the present invention, a wiring substrate having a support frame on the top surface, a semiconductor element having solder bumps on the bottom surface and flip-chip mounted on the top surface of the wiring substrate via the solder bumps, and covering the top surface of the wiring substrate In the semiconductor device comprising the heat sink arranged and fixed to the support frame and the semiconductor element,
A semiconductor device is provided, wherein a reinforcing frame is provided on the upper surface of the wiring board between the semiconductor element and a support frame so as to surround the semiconductor element.

本発明の半導体装置においては、配線基板上面に搭載された半導体素子の周囲に補強フレームを設けることにより、半導体素子と配線基板を構成する絶縁基板との熱膨張差に起因する配線基板の上に凸の反り変形を有効に回避することができる。従って、この半導体装置は、半田バンプを用いてプリント基板などの外部回路基板に実装した場合でも、配線基板の上記反り変形が抑制されているため、この半田バンプに発生する熱応力を低減することができ、長期間にわたり正確、かつ強固な電気的接続させることが可能となる。   In the semiconductor device of the present invention, a reinforcing frame is provided around the semiconductor element mounted on the upper surface of the wiring board, so that the semiconductor element is placed on the wiring board due to a difference in thermal expansion between the semiconductor element and the insulating substrate constituting the wiring board. Convex warpage deformation can be effectively avoided. Therefore, even when this semiconductor device is mounted on an external circuit board such as a printed board using solder bumps, the warping deformation of the wiring board is suppressed, so that the thermal stress generated on the solder bumps can be reduced. Therefore, accurate and strong electrical connection can be achieved over a long period of time.

本発明において、前記配線基板は、樹脂製絶縁基板に配線パターンを形成したものであることが好ましい。即ち、樹脂製絶縁基板は、成形が容易であり、その薄肉化を容易に実現することができるからである。しかも、通常、この厚みを薄くすると、半導体素子と絶縁基板との熱膨張差に起因する反り変形が大きくなり、外部回路基板に実装したときの接続部の熱疲労が増大する傾向があるが、本発明では、このような反り変形が有効に抑制されているため、この熱疲労を軽減することができる。   In the present invention, it is preferable that the wiring board has a wiring pattern formed on a resin insulating board. That is, the resin insulating substrate is easy to mold and can be easily thinned. Moreover, usually, when this thickness is reduced, warpage deformation due to the difference in thermal expansion between the semiconductor element and the insulating substrate increases, and thermal fatigue of the connection portion when mounted on the external circuit board tends to increase. In the present invention, since such warpage deformation is effectively suppressed, this thermal fatigue can be reduced.

また、前記補強フレームの高さは、半導体素子の厚みよりも小さく、且つ該補強フレームの上端は、前記放熱板とは非接触であることが好ましい。即ち、放熱板を補強フレームにも接着固定することにより、放熱板の機械的安定性を高めることができるが、補強フレームは、熱伝導性には寄与しない。従って、所定の補強効果が得られる限り、その高さをできるだけ低くし、装置コストの低減や装置の軽量化を図ることが望ましい。   The height of the reinforcing frame is preferably smaller than the thickness of the semiconductor element, and the upper end of the reinforcing frame is not in contact with the heat sink. That is, the mechanical stability of the heat sink can be improved by bonding and fixing the heat sink to the reinforcing frame, but the reinforcing frame does not contribute to the thermal conductivity. Therefore, as long as a predetermined reinforcing effect can be obtained, it is desirable to reduce the height as much as possible to reduce the device cost and the weight of the device.

前記補強フレームは、銅製であることが好ましい。即ち、銅はヤング率が高いため、銅製の補強フレームを使用することにより、薄い厚みで高い補強効果を確保することができる。   The reinforcing frame is preferably made of copper. That is, since copper has a high Young's modulus, a high reinforcing effect can be ensured with a thin thickness by using a copper reinforcing frame.

また、前記補強フレームとして、有機樹脂製のものも好適に使用することができる。エポキシ樹脂に代表される有機樹脂製の補強フレームは、銅製のものに比してヤング率が小さいため、その分、厚くする必要があるが、安価であり、また配線基板を構成する樹脂に近似した熱膨張係数を有しているという利点がある。   Moreover, the thing made from organic resin can also be used suitably as said reinforcement frame. Reinforcing frames made of organic resin, typified by epoxy resin, have a smaller Young's modulus compared to those made of copper, so it is necessary to make it thicker, but it is inexpensive and approximates the resin that makes up the wiring board There is an advantage that it has a thermal expansion coefficient.

本発明において、前記補強フレームは、実装された半導体素子と同心相似形に配置されており、且つ該補強フレームの各辺部の内側長さは、該半導体素子の対応する辺の長さの１．２倍以下であることが好ましい。即ち、半導体素子と同心相似形に配置することにより、半導体素子の周囲で均等な反り変形抑止効果を達成することができ、不自然な変形を生じることがなく、また、半導体素子の近傍に配置することにより、その反り変形抑止効果を高めることができる。   In the present invention, the reinforcing frame is arranged concentrically similar to the mounted semiconductor element, and the inner length of each side portion of the reinforcing frame is 1 of the corresponding side length of the semiconductor element. .2 or less is preferable. That is, by arranging concentrically similar to the semiconductor element, it is possible to achieve a uniform warpage deformation suppressing effect around the semiconductor element, without causing unnatural deformation, and in the vicinity of the semiconductor element. By doing so, the curvature deformation inhibitory effect can be heightened.

本発明では、前記配線基板の裏面には、前記半導体素子に導通し且つ半導体素子底面に形成された半田バンプよりも低融点の半田バンプが設けられており、該低融点半田バンプを介して外部回路基板に半導体装置を実装することが好ましい。即ち、低融点半田バンプを用いて外部回路基板に実装した場合において、前述した反り変形抑止効果により、外部回路基板との接合部である半田バンプの熱疲労を有効に軽減し、長期にわたって確実な接続信頼性を確保することができる。また、外部回路基板との接合に低融点の半田バンプを用いることにより、外部回路基板への実装のための熱処理により、配線基板と半導体素子との接合部の半田バンプの破損等を有効に回避することができる。   In the present invention, the back surface of the wiring board is provided with solder bumps that are conductive to the semiconductor element and have a lower melting point than the solder bumps formed on the bottom surface of the semiconductor element. It is preferable to mount the semiconductor device on the circuit board. That is, when mounted on an external circuit board using a low-melting-point solder bump, the thermal deformation of the solder bump, which is a joint portion with the external circuit board, is effectively reduced by the above-described warpage deformation suppressing effect, which is ensured over a long period of time. Connection reliability can be ensured. Also, by using solder bumps with a low melting point for bonding to the external circuit board, it is possible to effectively avoid damage to the solder bumps at the joint between the wiring board and the semiconductor element by heat treatment for mounting on the external circuit board. can do.

本発明を、添付図面に示す具体例に基づいて説明する。
図１は、本発明の半導体装置の好適な構造の一例を示す断面図であり、図２は、図１の半導体装置の要部である配線基板の半導体素子搭載面を示す平面図である。 The present invention will be described based on specific examples shown in the accompanying drawings.
FIG. 1 is a cross-sectional view showing an example of a preferred structure of the semiconductor device of the present invention, and FIG. 2 is a plan view showing a semiconductor element mounting surface of a wiring board which is a main part of the semiconductor device of FIG.

図１に示された本発明の半導体装置は、図３に示された公知の半導体装置と同様、ＢＧＡ（Ball Grid Array）タイプのフリップチップパッケージによる半導体装置であり、大略すると半導体素子１、配線基板２、放熱板３等からなっており、基本的な構造は、図３の半導体装置と共通している。   The semiconductor device of the present invention shown in FIG. 1 is a BGA (Ball Grid Array) type flip chip package semiconductor device, similar to the known semiconductor device shown in FIG. The basic structure is the same as that of the semiconductor device shown in FIG.

半導体素子１は、例えばシリコン（Ｓｉ）、ゲルマニウム（Ｇｅ）、ガリウム砒素（ＧａＡｓ）などの半導体、特にシリコンを用いた回路素子であり、その底面に複数の半田バンプ５が設けられている。この半田バンプ５を、配線基板２の上面に形成された配線パターン（図示せず）に半田溶融しフリップチップ実装することにより、配線基板２の上面に半導体素子１が搭載される。   The semiconductor element 1 is a circuit element using a semiconductor such as silicon (Si), germanium (Ge), and gallium arsenide (GaAs), particularly silicon, and a plurality of solder bumps 5 are provided on the bottom surface thereof. The solder bumps 5 are soldered and flip-chip mounted on a wiring pattern (not shown) formed on the upper surface of the wiring substrate 2, so that the semiconductor element 1 is mounted on the upper surface of the wiring substrate 2.

配線基板２は、樹脂製の絶縁基板に所定の配線パターンを形成したものであり、セラミック製絶縁基板を用いたものに比して生産コストが安価であり、半導体装置の製品コストの低減を図っている。また、薄肉化の点でも、セラミック製絶縁基板に比して有利である。このような絶縁基板の構成に用いる樹脂としては、例えば、ガラス繊維入りエポキシ樹脂などが好適に使用されるが、ガラス繊維入りエポキシ樹脂以外の他の樹脂により構成されていてもよく、例えば可撓性の高い樹脂材料により形成したいわゆるフレキシブル・プリント基板であってもよい。この配線基板２は、上記のような樹脂からなる絶縁層を積層させた多層構造を有していてもよく、各絶縁層の層間にも配線パターンを形成することもできる。このような配線基板は、例えば、厚みが１ｍｍ以下の薄肉の基板として使用することができる。   The wiring board 2 is formed by forming a predetermined wiring pattern on a resin insulating substrate, and the production cost is lower than that using a ceramic insulating substrate, thereby reducing the product cost of the semiconductor device. ing. Further, it is advantageous in terms of thinning as compared with a ceramic insulating substrate. As a resin used for the configuration of such an insulating substrate, for example, an epoxy resin containing glass fiber is preferably used, but it may be made of other resin other than the epoxy resin containing glass fiber, for example, flexible. It may be a so-called flexible printed board formed of a highly resinous resin material. The wiring board 2 may have a multilayer structure in which insulating layers made of the resin as described above are stacked, and a wiring pattern can be formed between the insulating layers. Such a wiring substrate can be used as a thin substrate having a thickness of 1 mm or less, for example.

尚、配線パターンは、銅、銀、金などの低抵抗導体を含有するペーストをスクリーン印刷等により所定のパターンで施し、焼付けることにより形成することができる。また、銅箔などを貼り付けてエッチングなどにより所定のパターンに加工することによっても形成することができる。   The wiring pattern can be formed by applying a paste containing a low resistance conductor such as copper, silver or gold in a predetermined pattern by screen printing or the like and baking it. It can also be formed by attaching a copper foil or the like and processing it into a predetermined pattern by etching or the like.

半導体素子１の底面に設けられる半田バンプ５としては、高融点半田、例えば鉛を９０％以上含有するものを使用することが好ましく、このような高融点半田の使用により、この半導体装置をプリント基板等の外部回路基板に実装する際の加熱などでの再溶融を防止できる。   As the solder bump 5 provided on the bottom surface of the semiconductor element 1, it is preferable to use a high melting point solder, for example, a solder containing 90% or more of lead. It is possible to prevent remelting due to heating or the like when mounted on an external circuit board.

上記の半田バンプ５を配線基板２の上面に形成された配線パターンに接続して加熱溶融することにより、半導体素子１が配線基板２の上面に実装されるわけであるが、通常、半導体素子１と配線基板２との接続部には、熱硬化性樹脂からなるアンダーフィル６が充填されており、半田バンプ５がアンダーフィル６内に埋め込まれている。このアンダーフィル６を加熱硬化することにより、半導体素子１は、配線基板２にしっかりと固定されると同時に、その可撓性により、両者の間に生じる応力を緩和し、半田バンプ５の破壊などによる断線等を防止するようになっている。   The semiconductor element 1 is mounted on the upper surface of the wiring substrate 2 by connecting the solder bump 5 to a wiring pattern formed on the upper surface of the wiring substrate 2 and heating and melting it. An underfill 6 made of a thermosetting resin is filled in a connection portion between the wiring board 2 and the wiring board 2, and solder bumps 5 are embedded in the underfill 6. By heat-curing the underfill 6, the semiconductor element 1 is firmly fixed to the wiring board 2, and at the same time, due to its flexibility, the stress generated between them is alleviated, and the solder bumps 5 are destroyed. It is designed to prevent disconnection and the like.

配線基板２の裏面には、外部回路基板との接続用端子となる半田ボール７が配設されている。図示されていないが、配線基板２の内部には、スルーホールに低抵抗導体を充填することにより形成されたビアホール導体が形成されており、配線基板２の裏面には、このビアホール導体によって上面の配線パターンに電気的に接続された接続パッド（前述した低抵抗導体からなる）が形成されており、この接続パッドに、上記の半田ボール７が接合されている。即ち、この半田ボール７は、配線基板２の上面に搭載された半導体素子１と電気的に接続されたものとなっている。   Solder balls 7 serving as terminals for connection to an external circuit board are disposed on the back surface of the wiring board 2. Although not shown, a via-hole conductor formed by filling a through hole with a low-resistance conductor is formed inside the wiring board 2, and the upper surface of the wiring board 2 is covered by the via-hole conductor. A connection pad (made of the low-resistance conductor described above) electrically connected to the wiring pattern is formed, and the solder ball 7 is bonded to the connection pad. That is, the solder ball 7 is electrically connected to the semiconductor element 1 mounted on the upper surface of the wiring board 2.

半田ボール７としては、半田バンプ５よりも低融点の材料、例えば、鉛含量の小さい錫−鉛合金などから形成されているものが好適である。即ち、この半導体装置は、この半田ボール７を、外部回路基板の配線パターン上に載置して加熱溶融することにより、外部回路基板上に実装されるが、半田ボール７として、半田バンプ５よりも低融点の半田を用いることにより、外部回路基板への実装に際しての半田バンプ５の溶融を防止することができ、半導体素子１との接続信頼性を確保することができる。   The solder ball 7 is preferably made of a material having a melting point lower than that of the solder bump 5, such as a tin-lead alloy having a low lead content. That is, the semiconductor device is mounted on the external circuit board by placing the solder ball 7 on the wiring pattern of the external circuit board and heating and melting it. In addition, by using solder having a low melting point, melting of the solder bumps 5 during mounting on an external circuit board can be prevented, and connection reliability with the semiconductor element 1 can be ensured.

放熱板３は、半導体素子１の動作により発生する熱を放熱するものであり、例えば銅やアルミニウムなどの熱伝導性の高い金属材料により形成され、広い放熱領域を設けられるように配線基板２の上面全体を覆うように配置される。この放熱板３は、ペースト材８により、半導体素子１の上面に接着されている。   The heat radiating plate 3 radiates heat generated by the operation of the semiconductor element 1. The heat radiating plate 3 is formed of a metal material having high thermal conductivity such as copper or aluminum, and is formed on the wiring board 2 so as to provide a wide heat radiating region. It arrange | positions so that the whole upper surface may be covered. The heat radiating plate 3 is bonded to the upper surface of the semiconductor element 1 with a paste material 8.

ペースト材８としては、金属フィラー（例えば銀）入り樹脂ペースト、非金属フィラー（例えばシリコン）入り樹脂ペースト、又はロウ材（例えば半田）等の比較的熱伝導性が良く、強い接着力を有する材料が使用され、半導体素子１に発生した熱が放熱板３に速やかに伝熱すようになっている。   The paste material 8 is a material having a relatively good thermal conductivity and a strong adhesive force, such as a resin paste containing a metal filler (eg, silver), a resin paste containing a non-metal filler (eg, silicon), or a brazing material (eg, solder). Is used, and heat generated in the semiconductor element 1 is quickly transferred to the heat radiating plate 3.

また、配線基板２の上面（即ち、半導体素子１の搭載面）には、図２に示されているように、支持フレーム４が設けられており、放熱板３は、この支持フレーム４の上端に接着剤９により接着固定されており、これにより、放熱板３は安定に保持され、その機械的安定性が高められている。上記でも説明したように、広い放熱領域を確保することが望ましいため、支持フレーム４は、通常、配線基板２の上面の周縁部に設け、放熱板３をできるだけ大面積とすることが好ましい。この支持フレーム４は、例えば、配線基板２を構成する絶縁基板と同種の樹脂材料や、金属等の剛性材料で形成され、予め配線基板２と一体に形成されていてもよいし、接着剤９によって、放熱板３に接着固定しておき、放熱板３を装着する際に、配線基板２に固定されるようにしてもよい。また、この支持フレーム４は、接着剤９により配線基板２に接着固定してもよい。放熱板３と支持フレーム４との接着に用いる接着剤９或いは支持フレーム４と配線基板２との接着に用いる接着剤としては、半田等のロウ材や熱可塑性樹脂のペーストなどが使用される。   Further, as shown in FIG. 2, a support frame 4 is provided on the upper surface of the wiring board 2 (that is, the mounting surface of the semiconductor element 1), and the heat radiating plate 3 is arranged at the upper end of the support frame 4. The heat radiating plate 3 is held stably and its mechanical stability is enhanced. As described above, since it is desirable to secure a wide heat dissipation area, it is preferable that the support frame 4 is usually provided on the peripheral edge of the upper surface of the wiring board 2 and the heat dissipation plate 3 is as large as possible. The support frame 4 is formed of, for example, the same type of resin material as that of the insulating substrate constituting the wiring board 2 or a rigid material such as metal, and may be previously formed integrally with the wiring board 2 or the adhesive 9. Thus, the heat radiating plate 3 may be bonded and fixed to the wiring board 2 when the heat radiating plate 3 is mounted. Further, the support frame 4 may be bonded and fixed to the wiring board 2 with an adhesive 9. As the adhesive 9 used for bonding the heat radiating plate 3 and the support frame 4 or the adhesive used for bonding the support frame 4 and the wiring substrate 2, a brazing material such as solder or a paste of thermoplastic resin is used.

図１及び図２を参照して、本発明においては、上記配線基板２の上面に、半導体素子１を取り囲むように補強フレーム１０が設けられる。既に述べた通り、この半導体装置は、前述した半田ボール７を用いてプリント基板などの外部回路基板に実装して使用に供されるが、半導体素子１のＯＮ／ＯＦＦによる発熱・冷却の繰り返しにより、上記熱膨張差によって上に凸の反り変形を生じるという問題がある。このような反り変形が生じると、外部回路基板と半導体装置との接続端子である半田ボール７が熱疲労し、断線などを生じてしまうが、本発明では、補強フレーム１０によって、半導体素子１と配線基板２との熱膨張差に起因する配線基板の上に凸の反り変形を有効に回避することができるため、半田ボール７の熱疲労を有効に回避し、接続信頼性を高めることができるのである。特に、配線基板２の厚みを薄くするほど、上記熱膨張差による反り変形が著しくなり、接続信頼性が損なわれるが、本発明では、補強フレーム１０の形成により、例えば配線基板２の厚みを０．５ｍｍ以下と極めて薄くした場合にも、接続信頼性を確保することができる。   With reference to FIGS. 1 and 2, in the present invention, a reinforcing frame 10 is provided on the upper surface of the wiring substrate 2 so as to surround the semiconductor element 1. As described above, this semiconductor device is mounted on an external circuit board such as a printed circuit board using the solder balls 7 described above, and is used by repeated heating and cooling by turning on and off the semiconductor element 1. There is a problem that convex warpage deformation occurs due to the difference in thermal expansion. When such warpage deformation occurs, the solder balls 7 that are the connection terminals between the external circuit board and the semiconductor device are thermally fatigued, resulting in disconnection or the like. Since convex warpage deformation on the wiring board due to the difference in thermal expansion from the wiring board 2 can be effectively avoided, thermal fatigue of the solder balls 7 can be effectively avoided and connection reliability can be improved. It is. In particular, as the thickness of the wiring board 2 is reduced, the warp deformation due to the difference in thermal expansion becomes more significant and connection reliability is impaired. However, in the present invention, for example, the thickness of the wiring board 2 is reduced to 0 by forming the reinforcing frame 10. Even when the thickness is as thin as 5 mm or less, connection reliability can be ensured.

本発明において、補強フレーム１０の高さは、放熱板３の装着に悪影響を与えない限り特に制限されず、例えば放熱板３と接触させることも可能であるが、基本的には、半導体素子１の厚みよりも小さくし、放熱板３とは非接触とすることが好ましい。即ち、この補強フレーム１０は、熱伝導性を高めるものではないため、上記反り変形を防止できる限り、その高さをできるだけ低くし、装置コストの低減や装置の軽量化を図ることが望ましいからである。補強フレーム１０の高さは、その材質や厚みによっても異なるが、通常、０．２ｍｍ以上とすることが好ましい。   In the present invention, the height of the reinforcing frame 10 is not particularly limited as long as it does not adversely affect the mounting of the heat radiating plate 3. For example, the height can be brought into contact with the heat radiating plate 3. It is preferable that the thickness is smaller than the thickness of the heat sink 3 and is not in contact with the heat sink 3. That is, since the reinforcing frame 10 does not increase the thermal conductivity, it is desirable to reduce the height as much as possible so as to prevent the warp deformation, thereby reducing the device cost and the weight of the device. is there. The height of the reinforcing frame 10 varies depending on its material and thickness, but is usually preferably 0.2 mm or more.

補強フレーム１０の材質は、特に制限されず、金属製、有機樹脂製の何れであってもよいが、銅製或いはエポキシ樹脂などの樹脂製であることが好ましい。即ち、銅はヤング率が高いため、銅製の補強フレーム１０を使用することにより、薄い厚みで高い補強効果を確保することができる。また、エポキシ樹脂等の有機樹脂製のものは、銅製のものに比してヤング率が小さいため、その分、厚くする必要があるが、安価であり、また配線基板を構成する樹脂に近似した熱膨張係数を有しているという利点がある。このような補強フレーム１０は、前述した接着剤によって配線基板２の上面に接着固定することができるが、樹脂製の補強フレーム１０の場合には、配線基板と一体に成形することもできる。また、半導体素子１を実装した後に、配線基板１０の上面に補強フレーム１０を設けることもできる。   The material of the reinforcing frame 10 is not particularly limited and may be made of metal or organic resin, but is preferably made of resin such as copper or epoxy resin. That is, since the Young's modulus of copper is high, the use of the copper reinforcing frame 10 can ensure a high reinforcing effect with a small thickness. In addition, those made of organic resins such as epoxy resins have a lower Young's modulus than those made of copper, so it is necessary to make them thicker, but they are inexpensive and approximate to the resin that constitutes the wiring board. There is an advantage of having a thermal expansion coefficient. Such a reinforcing frame 10 can be bonded and fixed to the upper surface of the wiring board 2 with the above-described adhesive, but in the case of the resin-made reinforcing frame 10, it can also be formed integrally with the wiring board. Further, the reinforcing frame 10 can be provided on the upper surface of the wiring board 10 after the semiconductor element 1 is mounted.

また、図２に示されているように、補強フレーム１０は、実装された半導体素子１と同心相似形（即ち、矩形状）に配置されていることが好ましい。半導体素子１と同心相似形に配置することにより、半導体素子１の周囲で均等な反り変形抑止効果を達成することができ、不自然な変形を防止することができる。   Further, as shown in FIG. 2, the reinforcing frame 10 is preferably arranged in a concentric similar shape (that is, a rectangular shape) to the mounted semiconductor element 1. By arranging in a concentric similarity with the semiconductor element 1, it is possible to achieve a uniform warpage deformation suppressing effect around the semiconductor element 1 and to prevent unnatural deformation.

また、このような補強フレーム１０の各辺部の内側長さＬは、半導体素子１の対応する辺の長さＷの１．２倍以下であることが好ましい。半導体素子１の近傍に配置することにより、その反り変形抑止効果を高めることができ、半導体素子１からあまり離して配置すると、反り変形抑止効果が低下するからである。   In addition, the inner length L of each side portion of the reinforcing frame 10 is preferably 1.2 times or less the corresponding side length W of the semiconductor element 1. This is because the warpage deformation suppressing effect can be enhanced by arranging the semiconductor element 1 in the vicinity of the semiconductor element 1, and the warping deformation suppressing effect is lowered when the semiconductor element 1 is arranged so as to be far away from the semiconductor element 1.

以下の半導体素子１、配線基板２及び放熱板３を用意した。
半導体素子１：底面に半田バンプを有するシリコンチップ
大きさ；１５ｍｍ平方
厚さ；０．６ｍｍ
配線基板２；上面に銅製配線パターン、下面に半田ボール７が形成され、配線パターンと半田ボール７とはビアホール導体で接続されたガラスエポキシ樹脂製
大きさ；４０ｍｍ平方
厚さ；０．７ｍｍ
支持フレーム；外形４０ｍｍ平方、内径２６ｍｍ平方、厚さ０．７ｍｍｓ
放熱板；アルミ製
大きさ；４０ｍｍ平方
厚さ０．５ｍｍ The following semiconductor element 1, wiring board 2, and heat sink 3 were prepared.
Semiconductor element 1: Silicon chip having solder bumps on the bottom surface Size: 15 mm Square thickness: 0.6 mm
Wiring board 2; copper wiring pattern on the upper surface and solder balls 7 formed on the lower surface. The wiring pattern and the solder balls 7 are made of glass epoxy resin connected by via-hole conductors; size: 40 mm square thickness: 0.7 mm
Support frame; 40mm square outer diameter, 26mm square inner diameter, 0.7mms thick
Heat sink: Aluminum Size: 40mm square, thickness 0.5mm

上記の配線基板２に、半導体素子１を半田パンプを介して実装した後、表１に示す材質及び大きさの正方形の補強フレーム１０（高さ０．４ｍｍ）をロウ材で図２に示されているようにして配線基板２の上面に接着固定して半導体パッケージを作製した。また、比較のために、補強フレーム１０を設けない半導体パッケージも作製した。   After the semiconductor element 1 is mounted on the wiring board 2 via a solder bump, a square reinforcing frame 10 (height 0.4 mm) having the material and size shown in Table 1 is shown as a brazing material in FIG. In this manner, the semiconductor package was manufactured by bonding and fixing to the upper surface of the wiring board 2. For comparison, a semiconductor package without the reinforcing frame 10 was also produced.

このパッケージを、プリント基板に実装し、信頼性試験の寿命サイクル数を比較した。信頼性試験は、大気の雰囲気にて−４０℃と１２５℃の各温度に制御した恒温槽に試験サンプルを２５分／２５分の保持を1サイクルとして、最高３５００サイクル繰り返した。そして、１００サイクル毎にプリント基板の配線導体とパッケージとの電気抵抗を測定し、電気抵抗に変化が現れるまでのサイクル数を表１に示した。   This package was mounted on a printed circuit board, and the life cycle number of the reliability test was compared. The reliability test was repeated for a maximum of 3500 cycles, with one cycle of holding the test sample at 25 minutes / 25 minutes in a thermostat controlled at −40 ° C. and 125 ° C. in an air atmosphere. Then, the electrical resistance between the wiring conductor of the printed circuit board and the package was measured every 100 cycles, and Table 1 shows the number of cycles until a change appears in the electrical resistance.

Figure 2005136220
Figure 2005136220

表１より明らかなように、補強フレームを設けた本発明の半導体装置（パッケージ）は、２７００サイクルまで、特に３５００サイクルを越えても抵抗変化は全く認められず、極めて安定で良好な電気的接続状態を維持できた。しかし、補強フレームを設けていないパッケージでは、２５００サイクル未満の早い段階から抵抗変化が検出され、実装後の信頼性に欠けることがわかった。   As is clear from Table 1, the semiconductor device (package) of the present invention provided with the reinforcing frame shows no change in resistance at all up to 2700 cycles, especially 3500 cycles, and is extremely stable and good electrical connection. I was able to maintain the state. However, in the package not provided with the reinforcing frame, a change in resistance was detected from an early stage of less than 2500 cycles, and it was found that reliability after mounting was lacking.

本発明の半導体装置の好適な構造の一例を示す断面図である。It is sectional drawing which shows an example of the suitable structure of the semiconductor device of this invention. 図１の半導体装置の要部である配線基板の半導体素子搭載面を示す平面図である。FIG. 2 is a plan view showing a semiconductor element mounting surface of a wiring board that is a main part of the semiconductor device of FIG. 1. 従来公知の半導体装置を示す断面図である。It is sectional drawing which shows a conventionally well-known semiconductor device.

符号の説明Explanation of symbols

１：半導体素子
２：配線基板
３：放熱板
４：支持フレーム
５：半田バンプ
７：半田ボール
１０：補強フレーム 1: Semiconductor element 2: Wiring board 3: Heat sink 4: Support frame 5: Solder bump 7: Solder ball 10: Reinforcement frame

Claims (7)

上面に支持フレームを有する配線基板と、底面に半田バンプを有し且つ該半田バンプを介して配線基板の上面にフリップチップ実装された半導体素子と、配線基板の上面を覆うように配置され且つ前記支持フレーム及び半導体素子に接着固定された放熱板とからなる半導体装置において、
前記配線基板の上面には、前記半導体素子と支持フレームとの間に、該半導体素子を取り囲むように補強フレームが設けられていることを特徴とする半導体装置。 A wiring board having a support frame on the top surface, a semiconductor element having solder bumps on the bottom surface and flip-chip mounted on the top surface of the wiring board via the solder bumps, and disposed so as to cover the top surface of the wiring board; In a semiconductor device comprising a support frame and a heat sink bonded and fixed to a semiconductor element,
A semiconductor device, wherein a reinforcing frame is provided on an upper surface of the wiring board between the semiconductor element and a support frame so as to surround the semiconductor element. 前記配線基板は、樹脂製絶縁基板に配線パターンを形成したものである請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the wiring board is formed by forming a wiring pattern on a resin insulating board. 前記補強フレームの高さは、前記半導体素子の厚みよりも小さく、且つ該補強フレームの上端は、前記放熱板とは非接触である請求項１または２記載の半導体装置。   The semiconductor device according to claim 1, wherein a height of the reinforcing frame is smaller than a thickness of the semiconductor element, and an upper end of the reinforcing frame is not in contact with the heat sink. 前記補強フレームは、銅製である請求項１乃至３の何れかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the reinforcing frame is made of copper. 前記補強フレームは、有機樹脂製である請求項１乃至３の何れかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the reinforcing frame is made of an organic resin. 前記補強フレームは、実装された半導体素子と同心相似形に配置されており、且つ該補強フレームの各辺部の内側長さは、該半導体素子の対応する辺の長さの１．２倍以下である請求項１乃至５の何れかに記載の半導体装置。   The reinforcing frame is arranged concentrically similar to the mounted semiconductor element, and the inner length of each side of the reinforcing frame is 1.2 times or less the length of the corresponding side of the semiconductor element. The semiconductor device according to claim 1, wherein: 前記配線基板の裏面には、前記半導体素子に導通し且つ半導体素子底面に形成された半田バンプよりも低融点の半田バンプが設けられており、該低融点半田バンプを介して外部回路基板に実装される請求項１乃至６に記載の半導体装置。   The back surface of the wiring board is provided with solder bumps that are conductive to the semiconductor element and have a lower melting point than the solder bumps formed on the bottom surface of the semiconductor element, and are mounted on the external circuit board via the low melting point solder bump. The semiconductor device according to claim 1 to 6.
JP2003371053A 2003-10-30 2003-10-30 Semiconductor device Expired - Fee Related JP4398223B2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010103338A (en) * 2008-10-24 2010-05-06 Nec Electronics Corp Semiconductor device and method of manufacturing same
JP2011515845A (en) * 2008-03-19 2011-05-19 エーティーアイ・テクノロジーズ・ユーエルシー Die substrate having reinforcing structure
US8598701B2 (en) 2009-12-14 2013-12-03 Panasonic Corporation Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011515845A (en) * 2008-03-19 2011-05-19 エーティーアイ・テクノロジーズ・ユーエルシー Die substrate having reinforcing structure
JP2010103338A (en) * 2008-10-24 2010-05-06 Nec Electronics Corp Semiconductor device and method of manufacturing same
US8598701B2 (en) 2009-12-14 2013-12-03 Panasonic Corporation Semiconductor device

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