JP2005134546A - Current generating circuit, electrooptical device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current generating circuit which eliminates write insufficiency and current fluctuations while maintaining merits of a current program system and is adequate for an electrooptical device, and to provide an electrooptical device and electronic device. <P>SOLUTION: A shift register 14a sequentially programs data currents IDR, IDG, and IDB of specified current values for outputting the data currents of the specified current values to respective corresponding data lines X1 and X2 for a plurality of driving sections 50 disposed at a current driver 14d. After the data currents IDR, IDG, and IDB for all the driving sections 50 are programmed, the respective driving sections 50 output the data currents of the specified currents based on the values of the programmed data currents IDR, IDG, and IDB to the respectively corresponding data lines X1 and X2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a current generation circuit, an electro-optical device, and an electronic apparatus.

  As an electro-optical device, for example, an organic electroluminescence display device (hereinafter referred to as an organic EL display device) is known. In an organic EL display device, an electro-optic element is made of an organic EL material, and has excellent features such as self-emission, high brightness, high viewing angle, thinness, high-speed response, and low power consumption, and uses a polysilicon TFT (thin film transistor). The peripheral drive circuit that has been used is attracting attention because it can be further reduced in size and weight.

By the way, this type of organic EL display device has luminance variations between pixels, and various driving methods such as a current programming method have been proposed in order to suppress this (for example, Patent Document 1).
US Pat. No. 6,229,506 B1

  By the way, since the driving method disclosed in Patent Document 1 uses the saturation region of the TFT, it is possible to compensate for variations in characteristics of the TFT and the organic EL element, but insufficient writing in the low gradation region, operation of the driving transistor (TFT). A gradation shift has occurred due to a change in the current supplied to the organic EL element due to the fluctuation of the points.

  That is, the insufficient writing in the low gradation region is caused by the wiring resistance and wiring capacitance of the data line that supplies the program data current to the pixel circuit. It is known that it takes time to store (write) a program data current in the capacitor element of the pixel circuit due to the wiring resistance and wiring capacitance of the data line. Further, when displaying a moving image or the like, the organic EL display device needs to supply a program data current to each pixel circuit within a predetermined time. Therefore, the smaller the program data current is, that is, the lower the gradation area, the more difficult it is to complete the writing of the program data current to the capacitor element of the pixel circuit within a predetermined time, resulting in insufficient writing. This insufficient writing causes a luminance shift.

  On the other hand, the change in the supply current to the organic EL element due to the change in the operating point of the drive transistor (TFT) is that the program data current is written (program period) and the drive current is supplied to the organic EL element (light emission period). This is because the load characteristics of the TFT drive transistors are different.

Since the current path that flows through the drive transistor during writing of the program data current (program period) is different from the current path that flows through the drive transistor during light emission, the load characteristics thereof are different. In the drain voltage-drain current characteristics of the TFT shown in FIG. 18, L1 indicates a load curve when the program data current is written, and L2 indicates a load curve when light is emitted. Therefore, after data writing is performed at the operating points Pa1, Pa2, Pa3, Pa4, etc. on the load curve L1, when the light emission operation is switched, the load characteristic of the driving transistor shifts from the load curve L1 to the load curve L2. For example, when the operating point is Pa1, the process moves to the operating point Pb1, and when the operating point is Pa3, the process moves to the operating point Pb3. At this time, as shown in FIG. 18, since the saturation region of the driving transistor is not a complete saturation region but has a certain slope, the corresponding operation is performed at each of the operating points Pa1, Pa2, Pa3, Pa4, etc. When shifting to points Pb1, Pb2, Pb3, Pb4, etc., the drain current changes. This current change is
Since there is a difference for each operating point, that is, for each data current value, a luminance relative to the data current value cannot be obtained and a luminance shift occurs.

  The present invention has been made to solve the above-described problems, and the object thereof is suitable for an electro-optical device capable of eliminating insufficient writing and current fluctuation while maintaining the excellent point of the current programming method. A current generating circuit, an electro-optical device, and an electronic apparatus.

  A current generation circuit according to the present invention sequentially programs a plurality of current generation units and a reference current having a constant current value for outputting a data current having a constant current value to an output line corresponding to each of the plurality of current generation units. And after the reference current is programmed for all of the current generators, each of the current generators is programmed to the corresponding output line in the program circuit unit. The data current having the constant current value is output based on the reference current value.

  According to the present invention, since the reference current is not supplied to all the drive units at the same time, the load on the circuit for supplying the reference current is small and the circuit scale can be reduced. In addition, the present invention can be employed in an electro-optical device that supplies a constant data current and adjusts the light emission time according to the gradation data to realize halftone.

  In the current generation circuit, the program circuit unit sequentially holds determination data for determining whether to output a data current having a constant current value to the corresponding output line for each of the plurality of current generation units. A circuit may be provided, and each of the current generators may output either the data current or a voltage signal different from the data current to a corresponding output line based on determination data.

  According to this, the plurality of current generation units can output either the data current or the voltage signal to the output line based on the determination data. Therefore, it is possible to employ a time-division gradation in an electro-optical device that supplies a constant data current and adjusts the light emission time according to gradation data to realize halftone.

  In the current generation circuit, the program circuit unit includes a plurality of holding circuits, and shifts the plurality of holding circuits in order to shift a start pulse in response to a clock signal, and each of the shift registers. A first memory unit provided corresponding to the holding circuit, and each memory unit receives a data current of the constant current value from the corresponding current generation unit when the corresponding holding circuit latches the start pulse. A first latch circuit for storing determination data for determining whether or not to output the first latch circuit, and a second memory unit provided corresponding to each of the first memory units in the first latch circuit. When all the first memory units of the latch circuit store the corresponding determination data, the corresponding second memory units simultaneously store the determination data stored in the first memory units. Stores, the stored said decision data, the corresponding one of the respective current generator may comprise a second latch circuit that outputs simultaneously.

  According to this, each current generation unit can input the determination data stored in the first latch circuit from the second latch circuit all at once, and can output the data current all at once. Therefore, it is possible to employ a time-division gradation in an electro-optical device that supplies a constant data current and adjusts the light emission time according to gradation data to realize halftone.

In this current generation circuit, each of the current generation units programs the reference current when the holding circuit of the corresponding shift register latches the start pulse, and the second memory of the corresponding second latch circuit. Either the data current or the voltage signal may be output based on the determination data of the unit.

  According to this, since the reference currents are not supplied all at once to each current generator, the load on the circuit supplying the reference current is small, and the circuit scale can be reduced. In addition, each current generator can output either a data current relative to the reference current or a voltage signal based on the determination data. Therefore, it is possible to employ a time-division gradation in an electro-optical device that supplies a constant data current and adjusts the light emission time according to gradation data to realize halftone.

In the current generation circuit, each current generation unit may output the voltage signal regardless of the determination data when a reset control signal is input.
According to this, it is possible to employ a time-division gradation by reset driving in an electro-optical device that supplies a constant value of data current and adjusts the light emission time according to gradation data to realize halftone.

  In this current generation circuit, each of the current generation units has a holding capacitor and a drive transistor, inputs the reference current, and drives a constant current value supplied from the drive transistor according to the value of the reference current. A current may be output to each output line as the data current.

  According to this, a voltage relative to the reference current is stored in the holding capacitor, and the driving transistor outputs a driving current having a constant current value relative to the voltage stored in the holding capacitor to each output line as the data current. . Therefore, the present invention can be employed in an electro-optical device that supplies a constant data current and adjusts the light emission time according to the gradation data to realize halftone.

The electro-optical device of the present invention is equipped with the current generation circuit described above as a data driver.
According to the present invention, it is possible to supply a constant value data current in the electro-optical device and adjust the light emission time according to the gradation data to realize halftone, insufficient data writing, or change in the operating point of the transistor. Can prevent uneven brightness.

  In this electro-optical device, one frame is different from a data driver in which current generators of the current generation circuit for supplying a data current having a constant current value to each pixel on a selected scanning line are provided by the number of data lines. There may be provided a scan driver that is divided into sub-frames and that appropriately selects each scan line for each sub-frame.

According to this, it is possible to employ a time division gradation in an electro-optical device that supplies a constant data current and adjusts the light emission time according to the gradation data to realize a halftone.
In this electro-optical device, when the data driver receives a reset control signal, the data driver outputs a turn-off signal regardless of determination data for determining whether to output a data current having a constant current value. A selection signal for appropriately selecting each scanning line may be generated in order to make the pixels emit no light.

  According to this, it is possible to employ a time-division gradation by reset driving in an electro-optical device that supplies a constant value of data current and adjusts the light emission time according to gradation data to realize halftone.

In this electro-optical device, the scanning driver may select the scanning lines in a non-sequential manner.
According to this, it is possible to employ a time-division gradation by non-sequential selection driving in an electro-optical device that supplies a constant data current and adjusts the light emission time according to gradation data to realize halftone. .

  In this electro-optical device, the pixel includes a holding capacitor, a driving transistor, and an electro-optical element, and receives a data current having the constant current value, and a constant current supplied from the driving transistor according to the data current value. A driving current having a value may be supplied to the electro-optical element.

According to this, the electro-optic element is always driven with a constant drive current.
In the electro-optical device, the electro-optical element may be an organic electroluminescence element.

According to this, the organic electroluminescence element always emits light at a constant current value, and the light emission period is adjusted according to the gradation data.
The electronic apparatus of the present invention includes the electro-optical device described above.

  According to this, it is possible to realize a display excellent in display quality that can eliminate supply of data current and current fluctuation.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block circuit diagram showing an electrical configuration of an organic electroluminescence (hereinafter referred to as EL) display device which is an example of an electro-optical device embodying the present invention. In FIG. 1, the organic EL display device 10 includes a display panel unit 11, a control circuit 12, a scan driver 13, a data driver 14, and a constant current circuit 15.

  The control circuit 12, the scanning driver 13, and the data driver 14 of the organic EL display device 10 may be configured by independent electronic components. For example, the control circuit 12, the scan driver 13, and the data driver 14 may be configured by a one-chip semiconductor integrated circuit device. Further, the control circuit 12, the scanning driver 13, and the data driver 14 may be configured as an electronic component that is wholly or partially integrated. For example, the control circuit 12, the scanning driver 13, and the data driver 14 may be integrally configured in the display panel unit 11. All or part of each control circuit 12, scan driver 13, and data driver 14 may be configured by a programmable IC chip, and the function may be realized by software by a program written in the IC chip.

In addition, the organic EL display device 10 of the present embodiment employs a current programming method, divides one frame into six subframes having different time ratios, and expresses halftones by appropriately selecting subframes to emit light. A time-division gradation method is adopted.
(Display panel section 11)
As shown in FIG. 2, the display panel unit 11 is provided with 3m (m is a natural number) data lines X1 to X3m extending along the column direction. In addition, the display panel unit 11 includes n (n is a natural number) first scanning lines Yp1 to Ypn extending along the row direction and n extending along the row direction paired with the first scanning lines Yp1 to Ypn. Second (n is a natural number) second scanning lines Yr1 to Yrn (n is a natural number) are wired. Further, the display panel unit 11 includes a plurality of pixels 20 arranged at positions corresponding to intersections between the plurality of data lines X1 to X3m and the plurality of first scanning lines Yp1 to Ypn (second scanning lines Yr1 to Yrn). have. That is, each pixel 20 is between a plurality of data lines X1 to X3m extending along the column direction and a plurality of first scanning lines Yp1 to Ypn (second scanning lines Yr1 to Yrn) extending along the row direction. The pixels 20 are arranged in a matrix by being arranged and electrically connected. The pixel 20 includes an organic EL element 21 having a light emitting layer made of an organic material, a pixel 20R that emits red light from the light emitting layer, a pixel 20G that emits green light from the light emitting layer, and a light emitting layer. It has a pixel 20B that emits blue light.

  In the display panel section 11, a plurality of red power supply lines La, green power supply lines Lg, and blue power supply lines Lb are arranged adjacent to the corresponding pixels 20R, 20G, and 20B along the column direction. . The red power supply line La, the green power supply line Lg, and the blue power supply line Lb are respectively connected to the red drive voltage VR via the corresponding red power supply line LR, green power supply line LG, and blue power supply line LB. The green driving voltage VG and the blue driving voltage VB are supplied.

  In the present embodiment, a plurality of first scanning lines Yp to Ypn (second scanning lines Yr1 to Yrn) are selected one by one in order from the top to the bottom, and are selected and applied to each pixel 20 on the scanning line. Data currents Id1 to Id3m (data currents IDR, IDG, IDB described later) are supplied via corresponding data lines X1 to X3m, respectively. Then, the lowest scanning line Ypn (second scanning line Yrn) is selected, data currents Id1 to Id3m are supplied to the pixels 20 on the scanning line Ypn, and each pixel 20 is based on the data currents Id1 to Id3m. When is emitted, an image of one frame is displayed on the display panel unit 11.

  FIG. 3 is a circuit showing an internal configuration of the pixel 20. Since the pixel 20 basically has the same circuit configuration, for convenience of explanation, the pixel 20 (blue pixel 20B) connected to the scanning line Yn and the data line X3m will be described, and description of the other pixels 20 will be omitted. To do.

  In FIG. 3, the pixel 20 includes a drive transistor Tdr, a programming transistor Tprg, a programming selection transistor Tsig, a reproduction selection transistor Trep, and a holding capacitor Cstg. The drive transistor Tdr is composed of a P-channel TFT. The programming transistor Tprg, the programming selection transistor Tsig, and the reproduction selection transistor Trep are composed of N-channel TFTs.

  The drain of the driving transistor Tdr is connected to the anode of the organic EL element 21 via the selection transistor Trep during reproduction, and the cathode of the organic EL element 21 is grounded. The drain of the driving transistor Tdr is connected to the data line Xm via the programming selection transistor Tsig. Further, the source of the drive transistor Tdr is connected to the blue power supply line Lc, and the blue power supply line Lc is supplied with a blue drive voltage VB for driving the organic EL element 21. Further, the driving transistor Tdr has a gate connected to the first electrode of the holding capacitor Cstg, and a second electrode of the holding capacitor Cstg is connected to the blue power supply line Lc. The programming transistor Tprg is connected between the gate and drain of the driving transistor Tdr.

  The gates of the programming selection transistor Tsig and the programming transistor Tprg are connected to the first scanning line Ypn. The programming selection transistor Tsig and the programming transistor Tprg are turned on in response to the H-level first scanning signal SCpn from the first scanning line Ypn, and are turned off in response to the L-level first scanning signal SCpn. It becomes a state. In this embodiment, when the programming selection transistor Tsig and the programming transistor Tprg are turned on, either the data current Id3m described later or the turn-off signal Vsig described later is supplied to the data line X3m. ing.

The gate of the selection transistor Trep at the time of reproduction is connected to the second scanning line Yrn. The reproduction selection transistor Trep is turned on in response to the second scanning signal SCrn2 at the H level from the second scanning line Yrn, and turned off in response to the second scanning signal SCrn at the L level. . When the reproduction selection transistor Trep is turned on, the drive current Idr based on the on state of the drive transistor Tdr is supplied to the organic EL element 21 as the supply current Ioled.

Next, the operation of the pixel 20 will be briefly described by dividing it into a program period, a light emitting period, an erasing period, and a light extinguishing period.
1. Program Period Now, when the first scanning signal SCpn of H level is output, the programming transistor Tprg and the programming time selection transistor Tsig are set to the on state. At this time, the L-level second scanning signal SCrn is output, and the reproducing selection transistor Trep is set to an off state. At this time, the data current Id3m is supplied to the data line X3m. Then, when the programming transistor Tprg is turned on, the driving transistor Tdr is diode-connected. As a result, the data current Id3m flows through a path of the driving transistor Tdr → the programming selection transistor Tsig → the data line X3m. At this time, a charge corresponding to the potential of the gate of the driving transistor Tdr is accumulated in the holding capacitor Cstg.

2. Light-Emitting Period From this state, when the first scanning signal SCpn becomes L level and the second scanning signal SCrn becomes H level, the programming transistor Tprg and the programming selection transistor Tsig are set to the off state, and the reproduction selection transistor Trep Set to the on state. At this time, since the charge accumulation state of the holding capacitor Cstg does not change, the gate potential of the driving transistor Tdr is held at the voltage when the data current Id3m flows. Accordingly, a drive current Idr (supply current Ioled) having a magnitude corresponding to the gate voltage flows between the source and drain of the drive transistor Tdr. Specifically, the supply current Ioled flows through a path of the drive transistor Tdr → the reproduction selection transistor Trep → the organic EL element 21. As a result, the organic EL element 21 emits light with a luminance corresponding to the supply current Ioled (data current Id3m). At this time, the path through which the current in the program period and the light emission period flows is different, and the load characteristic of the drive transistor Tdr is changed accordingly, so that the operating point is changed. Therefore, as described above, the supply current for each value of the data current Id3m The rate at which Ioled varies is different.

3. Erase Period When the organic EL element 21 emits light and a predetermined time elapses and the second scanning signal SCrn becomes L level, the selection transistor Trep at the time of reproduction is set to an off state. Therefore, the organic EL element 21 is not supplied with the supply current Ioled at this time, and is turned off. Subsequently, when the first scanning signal SCpn becomes the H level, the programming transistor Tprg and the programming selection transistor Tsig are set to an on state. At this time, a turn-off signal Vsig (voltage VDD) described later is supplied to the data line X3m. At this time, the extinction signal Vsig (voltage VDD) is supplied to the first electrode of the holding capacitor Cstg. The drive transistor Tdr is turned off with the gate having the same potential as the source.

4). Light-off period From this state, when the first scanning signal SCpn becomes L level and the second scanning signal SCrn becomes H level, the programming transistor Tprg and the programming selection transistor Tsig are set to the off state, and the reproduction selection transistor Trep Set to the on state. At this time, since the potential of the first electrode of the holding capacitor Cstg is held the same as the source potential of the driving transistor Tdr, the driving transistor Tdr is held in the off state.
Accordingly, since the supply current Ioled does not flow, the organic EL element 21 continues to be turned off until the next program period.

Therefore, if the data current Id3m is always maintained at a constant current value and the light emission period is changed (the light extinction period is changed), the luminance gradation of the organic EL element 21 can be controlled with the constant data current Id3m. That is, the gradation control can be performed without considering the fluctuation ratio of the supply current Ioled for each value of the data current Idm due to the change of the operating point due to the change in the load characteristic of the driving transistor Tdr.
(Control circuit 12)
Next, the control circuit 12 will be described with reference to FIG. The control circuit 12 receives an image signal (gradation data) D and a basic clock signal CLK for displaying an image on the display panel unit 11 from an external device.

  Based on the basic clock signal CLK, the control circuit 12 generates a data driver start pulse SPX, a data driver clock signal CLX, and a data driver clock inverted signal CBX based on the basic clock signal CLK and outputs the data driver 14 to the data driver 14. .

  The data driver start pulse SPX is output every time one of the first scanning lines Yp1 to Ypn is selected, and the pixels 20 on the selected one scanning line Yp1 to Ypn are dot-sequentially sequentially from left to right in FIG. It is a signal for selecting with. The data driver clock signal CLX and the data driver clock inverted signal CBX are complementary signals and are signals for sequentially shifting the data driver start pulse SPX. In the present embodiment, the pixel 20 is a set of a red pixel 20R, a green pixel 20G, and a blue pixel 20B. Then, in response to the data driver clock signal CLX and the data driver clock inversion signal CBX, the data driver start pulse SPX is shifted with one set as one unit, and in FIG. 2, one set of pixels 20R and 20G is sequentially arranged from left to right. , 20B are selected.

  The control circuit 12 generates a latch transfer signal LAT and a current driver control signal / CP based on the basic clock signal CLK, as shown in the time chart of FIG. The latch transfer signal LAT is a signal for holding (latching) the digital data signals VDR, VDG, and VDB written in dot-sequential manner in each pixel 20 on the selected scanning line at a predetermined timing. The current driver control signal / CP is a signal for causing the data driver 14 to output data currents Id1 to Id3m corresponding to the data lines X1 to X3m or a turn-off signal, respectively.

  Based on the basic clock signal CLK, the control circuit 12 generates a scan driver start pulse SPY, a scan driver clock signal CLY, a scan driver clock inverted signal CBY, and a program period control signal / WR as shown in the time chart of FIG. Output to the data driver 14.

  The scan driver start pulse SPY is the first scan line Yp1 (second scan) when the first scan lines Yp1 to Ypn (second scan lines Yr1 to Yrn) are selected in a line sequential manner from the top to the bottom. This signal is output when the line Yr1) is selected.

  The scan driver clock signal CLY and the scan driver clock inversion signal CBY are complementary signals, and are signals for sequentially shifting the scan driver start pulse SPY in order to select a scan line in line sequence.

The program period control signal / WR is a signal that is output in response to the rise and fall of the scan driver clock signal CLY (scan driver clock inverted signal CBY).
Determine the data write time.

  The control circuit 12 generates a red digital data signal VDR, a green digital data signal VDG, and a blue digital data signal VDB for each pixel 20 (20R, 20G, 20B) based on the image signal (gradation data) D. To do. The control circuit 12 outputs the generated digital data signals VDR, VDG, and VDB to the data driver 14 in synchronization with the data driver clock signal CLX and the data driver clock inverted signal CBX. That is, the control circuit 12 includes the pixels 20 (20R, 20G, 20B) on the scanning line selected in synchronization with the data driver clock signal CLX and the data driver clock inversion signal CBX, and the points in order from left to right. The digital data signals VDR, VDG, and VDB of the selected pixel are sequentially output. The digital data signals VDR, VDG, and VDB are binary digital data that determine whether or not the organic EL element 21 of the corresponding pixel 20 emits light. Data is emitted when the digital data signals VDR, VDG, and VDB are at the H level, and data is not emitted when the digital data signals VDR, VDG, and VDB are at the L level.

By the way, in this embodiment, the organic EL display device 10 adopts a current programming method, divides one frame into six subframes having different time ratios, and selects halftones by appropriately selecting the subframes to emit light. A time-division gradation method is used. As shown in FIG. 7, in order to express a halftone with 64 gradations, one frame is divided into six first to sixth subframes SF1 to SF6, and a period TL1 of the first to sixth subframes SF1 to SF6 is obtained. ~ TL6,
TL1: TL2: TL3: TL4: TL5: TL6 = 1: 2: 4: 8: 16: 32
It is set by the time ratio.

  When the gradation data D is “63” gradation, all of the first to sixth sub-frames SF1 to SF6 are selected, and light is emitted only during the light emission period T (= TL1 + TL2 + TL3 + TL4 + TL5 + TL6). The light emission having the luminance of the gradation data D is obtained. When the gradation data D is “31” gradation, the first to fifth sub-frames SF1 to SF5 are selected and light is emitted only during the light emission period T (= TL1 + TL2 + TL3 + TL4 + TL5), so that the pixel 20 apparently appears. “31” gradation luminance is emitted. Incidentally, when the gradation data D is “12” gradation, the third sub-frame SF3 and the fourth sub-frame SF4 are selected and light is emitted for the light emission period T (= TL3 + TL4). "Emit light with gradation brightness. That is, by supplying the largest data current Imax corresponding to the “63” gradation to the data lines X1 to X3m and changing the light emission period T according to the gradation data D, the pixel 20 is changed to the gradation data D. It emits light with the brightness corresponding to.

  Therefore, the control circuit 12 creates the digital data signals VDR, VDG, and VDB in each of the sub-frames SF1 to SF6 of one frame based on the gradation data D of the pixel 20 for each pixel 20. That is, the control circuit 12 creates digital data signals VDR, VDG, and VDB having two values that determine whether the organic EL element 21 emits light or not in each of the subframes SF1 to SF6.

(Scanning driver 13)
Next, the scanning driver 13 will be described with reference to FIGS. In FIG. 2, the scan driver 13 inputs a scan driver start pulse SPY, a scan driver clock signal CLY, a scan driver clock inversion signal CBY, and a program period control signal / WR from the control circuit 12. The scan driver 13 receives these signals. Based on this, the first scanning lines Yp to Ypn and the second scanning lines Yr1 to Yrn are selected line-sequentially from top to bottom, and a group of pixels 20 for one row is sequentially selected.

  The scan driver 13 includes a shift register 13a and a level shifter 13b. As shown in FIG. 4, the shift register 13a has n holding circuits 30 corresponding to the first scanning lines Yp1 to Ypn (second scanning lines Yr1 to Yrn). In FIG. 4, two holding circuits 30 are shown for convenience of explanation. Each holding circuit 30 includes an inverter circuit 31, a latch unit 32, and a NAND circuit 33.

  The inverter circuit 31 of each holding circuit 30 includes a scan driver clock inverted signal CBY for the inverter circuit 31 of the odd-numbered holding circuit 30 and a scan driver clock signal CLY for the inverter circuit 31 of the even-numbered holding circuit 30. Input as a synchronization signal. The inverter circuit 31 of the odd-numbered holding circuit 30 inputs the scan driver start pulse SPY in response to the rise of the scan driver clock inversion signal CBY and outputs it to the latch unit 32. The inverter circuit 31 of the even-numbered holding circuit 30 inputs the scan driver start pulse SPY in response to the rise of the scan driver clock signal CLY and outputs it to the latch unit 32.

  The latch unit 32 of each holding circuit 30 includes two inverter circuits, and the scan driver clock signal CLY is supplied to the latch unit 32 of the odd-numbered stage holding circuit 30, and the latch circuit 32 of the even-numbered stage holding circuit 30. The scan driver clock inversion signal CBY is input as a synchronization signal. The latch unit 32 of the odd-numbered holding circuit 30 inputs and holds the scan driver start pulse SPY from the inverter circuit 31 in response to the rising edge of the scan driver clock signal CLY. The latch unit 32 of the even-numbered holding circuit 30 inputs and holds the scan driver start pulse SPY from the inverter circuit 31 in response to the rise of the scan driver clock inversion signal CBY. Each latch unit 32 outputs the held scan driver start pulse SPY to the inverter circuit 31 of the holding circuit 30 at the next stage.

  Therefore, the H-level scan driver start pulse SPY output from the control circuit 12 is synchronized with the scan driver clock signal CLY and the scan driver clock inversion signal CBY in order from the holding circuit 30 of the first scan line Yp1. The scanning line Ypn is shifted to the holding circuit 30.

  The NAND circuit 33 provided in the holding circuit 30 has an input terminal connected to an output terminal of the latch unit 32 and an output terminal of the latch unit 32 provided in the holding circuit 30 in the next stage. Accordingly, the NAND circuit 33 of each holding circuit 30 outputs the output signal UY of L level when the holding circuit 30 and the latch unit 32 of the holding circuit 30 of the next stage hold the scan driver start pulse SPY of H level. When the latch unit 32 of the holding circuit 30 shifts the scan driver start pulse SPY and disappears, the NAND circuit 33 outputs an H level output signal UY. Thereafter, the NAND circuit 33 outputs the H level output signal UY until the latch unit 32 holds the new scan driver start pulse SPY.

  Note that the period of rising from the L level of the output signal UY output from the holding circuit 30 (NAND circuit 33) to the H level is a half cycle of the scanning driver clock signal CLY (scanning driver clock inverted signal CBY). It becomes.

The output signal UY of the NAND circuit 33 provided in each holding circuit 30 is output to the level shifter 13b. The level shifter 13 b has n selection circuits 35 corresponding to the holding circuits 30. Each selection circuit 35 includes a NOR circuit 36 and two first and second buffer circuits 37 and 38. The NOR circuit 36 is a NOR circuit having two input terminals, and an output signal UY from the corresponding NAND circuit 33 is input to one input terminal, and a program period control signal from the control circuit 12 is input to the other input terminal. Enter / WR. Therefore, the NOR circuit 36 outputs an H level signal to the first buffer circuit 37 when the output signal UY and the program period control signal / WR are at the L level.

  The first buffer circuit 37 of each selection circuit 35 is connected to the corresponding first scanning line Yp1 to Ypn. Accordingly, the first buffer circuit 37 of each selection circuit 35 outputs the H level signal output from the NOR circuit 36 to the first scanning lines Yp1 to Ypn as the first scanning signals SCp1 to SCpn, respectively. That is, the first buffer circuit 37 of each selection circuit 35 turns on the programming transistor Tprg and the programming selection transistor Tsig of the pixel 20 connected to the corresponding first scanning line.

  The second buffer circuit 38 of each selection circuit 35 receives the output signal UY from the NAND circuit 33 of the corresponding holding circuit 30. Each second buffer circuit 38 is connected to the corresponding second scanning line Yr1 to Yrn. Accordingly, the second buffer circuit 38 of each selection circuit 35 outputs the H level output signal UY output from the NAND circuit 33 to the second scanning lines Yr1 to Yrn as the second scanning signals SCr1 to SCrn, respectively. That is, the second buffer circuit 38 of each selection circuit 35 turns on the selection transistor Trep at the time of reproduction of the pixel 20 connected to the corresponding second scanning line.

  The level shifter 13b selects the first scanning lines Yp1 to Ypn in order from the top to the bottom by the first scanning signals SCp1 to SCpn, and writes the data currents Id1 to Id3m, respectively. The level shifter 13b then selects the second scanning lines Yr1 to Yrn from the top to the bottom in order from the top to the bottom in accordance with the second scanning signals SCr1 to SCrn after a predetermined programming period, and then selects the second scanning lines Yr1 to Yrn. The pixel 20 is caused to emit light.

(Data driver 14)
Next, the data driver 14 will be described with reference to FIGS. The data driver 14 receives a data driver start pulse SPX, a data driver clock signal CLX, and a data driver clock inverted signal CBX from the control circuit 12. The data driver 14 also receives the red digital data signal VDR, the green digital data signal VDG, and the blue digital data signal VDB from the control circuit 12. Further, the data driver 14 receives the latch transfer signal LAT and the current driver control signal / CP from the control circuit 12. The data driver 14 also receives a red data current IDR, a green data current IDG, and a blue data current IDB, which are constant current values, from the constant current circuit 15, respectively. In the present embodiment, the constant current circuit 15 is configured as a circuit different from the data driver 14 like the control circuit 12, but may be configured as a part of the data driver 14. Based on these signals, the data driver 14 supplies the data currents Id1 to Id3m and the turn-off signal Vsig to the data lines X1 to X3m in synchronization with the selection operation of the first scanning lines Yp1 to Ypn.

  The data driver 14 includes a shift register 14a, a first latch circuit 14b, a second latch circuit 14c, and a current driver 14d. In the present embodiment, the shift register 14a, the first latch circuit 14b, and the second latch circuit 14c correspond to the program circuit section described in the claims.

(Shift register 14a)
As shown in FIG. 5, the shift register 14a includes 3m data lines X1 to X3m, each of which includes three data lines, and a number (m) of holding circuits 40 corresponding to the number of the sets. ing. 5 shows three holding circuits 40 for convenience of explanation. Each holding circuit 40 includes an inverter circuit 41, a latch unit 42, a NAND circuit 43, and an inverter circuit 44.

The inverter circuit 41 of each holding circuit 40 has a data driver clock signal CLX for the inverter circuit 41 of the odd-numbered holding circuit 40 and a data driver clock inverted signal CBX for the inverter circuit 41 of the even-numbered holding circuit 40. Input as a synchronization signal. The inverter circuit 41 of the odd-numbered holding circuit 40 inputs the data driver start pulse SPX in response to the rise of the data driver clock signal CLX and outputs it to the latch unit 42. The inverter circuit 41 of the even-numbered holding circuit 40 receives the data driver start pulse SPX in response to the rising edge of the data driver clock inverted signal CBX and outputs it to the latch unit 42.

  The latch unit 42 of each holding circuit 40 includes two inverter circuits, and the data driver clock inverted signal CBX is supplied to the latch unit 42 of the odd-numbered holding circuit 40, and the latch unit 42 of the even-numbered holding circuit 40. Is supplied with a data driver clock signal CLX as a synchronization signal. The latch section 42 of the odd-numbered holding circuit 40 inputs and holds the data driver start pulse SPX from the inverter circuit 41 in response to the rising edge of the data driver clock inverted signal CBX. The latch section 42 of the even-numbered holding circuit 40 inputs and holds the data driver start pulse SPX from the inverter circuit 41 in response to the rising edge of the data driver clock signal CLX. Each latch unit 42 outputs the held data driver start pulse SPX to the inverter circuit 41 of the holding circuit 40 in the next stage.

  Therefore, the H level data driver start pulse SPX output from the control circuit 12 is synchronized with the data driver clock signal CLX and the data driver clock inverted signal CBX, and the holding circuit 40 corresponding to the three data lines X1 to X3. Are sequentially shifted to the holding circuit 40 corresponding to the data lines X3m-2 to X3m.

  The NAND circuit 43 provided in the holding circuit 40 has an input terminal connected to an output terminal of the latch unit 42 and an output terminal of the latch unit 42 provided in the holding circuit 40 in the next stage. Therefore, the NAND circuit 43 of each holding circuit 40 outputs the output signal UX to the L level when the holding circuit 40 and the latch unit 42 of the holding circuit 40 in the next stage hold the data driver start pulse SPX of the H level. Then, when the latch unit 42 of the holding circuit 40 shifts the data driver start pulse SPX and disappears, the NAND circuit 43 outputs the output signal UX to the H level. Thereafter, the NAND circuit 43 outputs the output signal UX at the H level until the latch unit 42 holds the new data driver start pulse SPX.

  Note that the period of rising from the L level of the output signal UX output from the holding circuit 40 (NAND circuit 43) to the H level is a half cycle of the data driver clock signal CLX (scanning driver clock inverted signal CBX). It becomes.

  The output signal UX of the NAND circuit 43 provided in each holding circuit 40 is output to the current driver 14d, and the level is inverted via the inverter circuit 44 and output to the first latch circuit 14b as the inverted output signal UBX. In FIG. 6, the inverted output signals UBX based on the m NAND circuits 43 are denoted as UBX1, UBX2, UBX3... UBXm-1, UBXm from the left side.

(First latch circuit 14b)
The first latch circuit 14b receives the inverted output signal UBX output in order from each holding circuit 40. Further, the first latch circuit 14b sequentially outputs the red digital data signal VDR, the green digital data signal VDG, and the blue digital data signal VDB for each of the pixels 20R, 20G, and 20B from each holding circuit 40. Input in synchronization with the inverted output signal UBX.

The first latch circuit 14 b includes a number of first memory units 45 corresponding to the holding circuits 40. Each first memory unit 45 includes three latch units 45R, 45G, and 45B and switches QR1, QG1, and QB1 including three N-channel MOS transistors. Switch Q
An inverted output signal UBX at H level is input to the gates of R1, QG1, and QB1, and is turned on.

  The latch unit 45R includes two inverter circuits, and the red digital data signal VDR is input via the switch QR1. The latch unit 45G is composed of two inverter circuits, and receives the green digital data signal VDG via the switch QG1. The latch unit 45B is composed of two inverter circuits, and the blue digital data signal VDB is input via the switch QB1.

  In response to the L level inverted output signal UBX from the corresponding holding circuit 40, each of the latch units 45R, 45G, and 45B outputs the red digital data signal VDR and the green digital signal output from the control circuit 12 at that time. The data signal VDG and the blue digital data signal VDB are held. That is, each first memory unit 45 of the first latch circuit 14b responds to the inverted output signal UBX output from the corresponding holding circuit 40 in order from the left, and the red digital data signal VDR and the green digital data signal. VDG and blue digital data signal VDB are stored. The digital data signals VDR, VDG, and VDB stored in the first memory units 45 are output to the second latch circuit 14c.

(Second latch circuit 14c)
The second latch circuit 14 c includes a number of second memory units 46 corresponding to the first memory units 45. Each second memory unit 46 includes three latch units 46R, 46G, and 46B and switches QR2, QG2, and QB2 including three N-channel MOS transistors. The latch transfer signal LAT at H level is input to the gates of the switches QR2, QG2, and QB2, and the switches are turned on.

  The latch unit 46R includes two inverter circuits, and the red digital data signal VDR held by the previous latch unit 45R is input via the switch QR2. The latch unit 46G includes two inverter circuits, and the green digital data signal VDG held by the preceding latch unit 45G is input via the switch QG2. The latch unit 46B includes two inverter circuits, and the blue digital data signal VDB held by the previous latch unit 45B is input via the switch QB2.

  Then, each of the latch units 46R, 46G, 46B of the second memory unit 46 responds to the latch transfer signal LAT of the H level from the corresponding latch unit 46R, 46G, 46B of the first memory unit 45. The data signal VDR, the green digital data signal VDG, and the blue digital data signal VDB are held. The latch transfer signal LAT at H level is simultaneously output to all the second memory units 46 of the second latch circuit 14c. Accordingly, the digital data signals VDR, VDG, VDB stored in all the first memory units 45 of the first latch circuit 14b are stored in the second memory unit 46 of the corresponding second latch circuit 14c all at once. The digital data signals VDR, VDG, VDB stored in the second memory units 46 of the second latch circuit 14c are output to the current driver 14d.

(Current driver 14d)
The current driver 14d receives the current driver control signal / CP from the control circuit 12 in addition to the digital data signals VDR, VDG, and VDB. Further, the current driver 14 d receives the red data current IDR, the green data current IDG, and the blue data current IDB from the constant current circuit 15. The red data current IDR is a current supplied to the data line to which the red pixel 20R is connected, and is a data current having a predetermined constant current value. The green data current IDG is a current supplied to the data line to which the green pixel 20G is connected, and is a data current having a predetermined constant current value. The blue data current IDB is a current supplied to the data line to which the blue pixel 20B is connected, and is a data current having a predetermined constant current value. Accordingly, the data currents Id1 to Id3m supplied to the data lines X1 to X3m described in the display panel unit 11 are respectively constant current values of the red data current IDR, the green data current IDG, and the blue data current IDB. Either. In this embodiment, the red data current IDR, the green data current IDG, and the blue data current IDB are not written insufficiently by the pixels 20R, 20G, and 20B due to the wiring capacity of the data line in the program period. It is a constant current value of about a large value.

  The current driver 14d has the drive units 50 in a number corresponding to the second memory units 46 of the second latch circuit 14c. Each driving unit 50 includes driving circuits 51R, 51G, and 51B for red, green, and blue corresponding to the latch units 46R, 46G, and 46B of the second memory unit 46, respectively. Each drive circuit 50R, 50G, 50B has a NOR circuit 51, a holding capacitor 52, first and second switching transistors Qs1, Qs2, a drive transistor Qd, first and second selection transistors Qe1, Qe2, and a gate transistor Qg. ing. In the present embodiment, the first and second switching transistors Qs1, Qs2, the drive transistor Qd, the first selection transistor Qe1, and the gate transistor Qg are formed of N-channel MOS transistors. The second selection transistor Qe2 is formed of a P channel MOS transistor.

  The NOR circuits 51 provided in the drive circuits 51R, 51G, 51B of each drive unit 50 respectively receive the output signal UX from the holding circuit 40 of the shift register 14a corresponding to one of the input terminals, and to the other input terminal. Current driver control signal / CP is input from control circuit 12. Therefore, when both the current driver control signal / CP and the output signal UX are at the L level, the control signal SG at the H level is output. That is, when the current driver control signal / CP is in the L level and each holding circuit 40 of the shift register 14a sequentially outputs the L level output signal UX, each driving unit 50 sequentially starts from the left. An H level control signal SG is output from a NOR circuit 51 provided in the drive circuits 51R, 51G, 51B of the drive unit 50.

  The first and second switching transistors Qs1 and Qs2 of the red driving circuit 51R are connected in series, one end of the series circuit is connected to a power supply line that supplies the red data current IDR, and the other end is connected via a storage capacitor 52. Are connected to a power supply line for supplying a drive voltage Vss. The gates of the first and second switching transistors Qs 1 and Qs 2 are connected to the output terminal of the NOR circuit 51. The storage capacitor 52 is connected between the gate and drain of the driving transistor Qd. Therefore, an H level control signal SG is output from the NOR circuit 51, and the first and second switching transistors Qs1 and Qs2 are turned on. At this time, the driving transistor Qd is diode-connected, and the first and second switching transistors Qs1 and Qs2 are turned on. As a result, the red data current IDR flows via the first switching transistor Qs1 and the driving transistor Qd. At this time, a charge relative to the red data current IDR is accumulated in the storage capacitor 52.

  The source of the driving transistor Qd is connected to the corresponding data line via the first selection transistor Qe1 and the gate transistor Qg. One end of the second selection transistor Qe2 is connected to the power supply line to which the drive voltage VDD is supplied, and the other end is connected to the corresponding data lines X1 to X3m via the gate transistor Qg.

  A current driver control signal / CP is input to the gate of the gate transistor Qg. When the current driver control signal / CP is at H level, it is turned on. That is, the gate transistor Qg is in an on state except when the storage capacitor 52 has accumulated charges relative to the red data current IDR.

  The red digital data signal VDR is input to the gates of the first and second selection transistors Qe1 and Qe2 from the corresponding latch unit 46R of the second memory unit 46. Therefore, when the gate transistor Qg is in the on state and the red digital data signal VDR is at the H level, the first selection transistor Qe1 is in the on state (the second selection transistor Qe2 is in the off state), and the drive transistor Qd is held. A current (red data current IDR) flows corresponding to the charge accumulated in the capacitor 52. That is, the red data current IDR is written to the pixel 20 selected via the data line. On the other hand, when the gate transistor Qg is in the on state and the red digital data signal VDR is at the L level, the second selection transistor Qe2 is in the on state (the first selection transistor Qe1 is in the off state), and the drive voltage VDD is The turn-off signal Vsig is supplied to the selected pixel 20 through the data line. That is, the drive transistor Tdr of the pixel 20 is turned off by the drive voltage VDD (light-off signal Vsig), and the organic EL element 21 of the pixel 20 stops emitting light.

  The drive circuits 51G and 51b for green and blue use the red data current IDR and the red digital data signal VDR for the green and blue data currents IDG and IDB and the green and blue digital data signals VDG, respectively. Since it is only changed to VDB, explanation is omitted.

Next, the operation of the organic EL display device 10 configured as described above will be described with reference to a time chart shown in FIG.
Now, when gradation data D of one frame is input to the control circuit 12, the control circuit 12 creates the digital data signals VDR, VDG, and VDB in the first to sixth subframes SF1 to SF6 for each pixel 20. To do. When the digital data signals VDR, VDG, and VDB in the first to sixth subframes SF1 to SF6 of each pixel 20 for one frame are created, the display operation for the first subframe SF1 is started.

(Period Z1)
First, the control circuit 12 outputs a data driver clock signal CLX and a data driver clock inversion signal CBX to the shift register 14a of the data driver 14, and outputs one data driver start pulse SPX. The shift register 14a sends the data driver start pulse SPX in synchronization with the data driver clock signal CLX (data driver clock inverted signal CBX) from the holding circuit 40 corresponding to the three data lines X1 to X3 in order from the data line X3m−. The shift is made to the holding circuit 40 corresponding to 2 to X3m. Then, the shift register 14a sequentially outputs the H level inverted output signals UBX1 to UBXm to the first latch circuit 14b.

  The control circuit 12 synchronizes with the data driver clock signal CLX, that is, synchronizes with the H level inverted output signals UBX1 to UBXm that are output in order, in the first subframe of the pixel 20 on the first scanning line Yp1. Digital data signals VDR, VDG, and VDB in SF1 are output. At this time, the control circuit 12 sequentially outputs the digital data signals VDR, VDG, and VDB from the left pixel 20 to the right pixel 20. Accordingly, the corresponding digital data signals VDR, VDG, and VDB are stored in the dot order in the latch units 45R, 45G, and 45B of the first memory units 45 provided in the first latch circuit 14b.

On the other hand, during the storage operation of the first latch circuit 14b, the current driver 14d sequentially inputs the H level output signal UX. At this time, since the current driver control signal / CP is in the L level state, the current driver 14d responds to the output signal UX that is sequentially input, and sequentially programs the current to the corresponding drive unit 50. That is, in each drive unit 50, the red drive circuit 51R has a red data current IDR current value, the green drive circuit 51G has a green data current IDG current value, and the blue drive circuit 51B has a current value. The current value of the blue data current IDB is programmed in each holding capacitor 52. Accordingly, the m drive units 50 including the red drive circuit 51R, the green drive circuit 51G, and the blue drive circuit 51B do not program the data currents IDR, IDG, IDB all at once, but sequentially. In order to program, the load of the constant current circuit 15 can be small.

  During this period Z1, the scan driver start pulse SPY is input to the scan driver 13 from the control circuit 12, but the first scan line Yp1 and the second scan line Yr1 are not selected.

(Period Z2)
When the digital data signals VDR, VDG, and VDB are stored in the latch units 45R, 45G, and 45B of all the first memory units 45 provided in the first latch circuit 14b, the control circuit 12 outputs the current driver control signal / CP. At the same time, the latch transfer signal LAT is set to the H level. As a result, the switches QR2, QG2, QB2 of the second latch circuit 14c and the gate transistor Qg of the current driver 14d are turned on.
The digital data signals VDR, VDG, and VDB of the latch units 45R, 45G, and 45B of the first memory units 45 are supplied to the latch units 46R, 46G, and V of the second memory units 46 of the corresponding second latch circuit 14c. 46B is stored all at once. Then, the latch units 46R, 46G, and 46B of each second memory unit 46 are simultaneously applied to the drive circuits 51R, 51G, and 51B of the drive unit 50 provided with the digital data signals VDR, VDG, and VDB in the corresponding current driver 14d, respectively. Output.

  Accordingly, when the driving circuits 51R, 51G, and 51B of each driving unit 50 are H-level digital data signals VDR, VDG, and VDB for emitting light, the first selection transistor Qe1 is turned on. As a result, the drive circuits 51R, 51G, 51B output the data currents IDR, IDG, IDB programmed during the period Z1 to the data line through the first selection transistor Qe1 and the gate transistor Qg.

  On the other hand, when the driving circuits 51R, 51G, and 51B of each driving unit 50 are L-level digital data signals VDR, VDG, and VDB for non-light emission, the second selection transistor Qe2 is turned on. As a result, the drive circuits 51R, 51G, and 51B output the drive voltage VDD as the extinguishing signal Vsig to the data line via the second selection transistor Qe2 and the gate transistor Qg.

  In this period Z2, the scanning driver 13 outputs the first scanning signal SCp1 at H level and the second scanning signal SCr1 at L level. That is, it is a program period in each pixel 20 on the first scanning line Yp1 (second scanning line Tr1). Accordingly, each pixel 20 on the first scanning line Yp1 (second scanning line Tr1) is connected to the data currents Id1 to Id3m (data currents IDR, IDG, IDB having a constant current value) or the data lines X1 to X3m or A turn-off signal Vsig is supplied. As a result, in the pixel 20 to which the data currents IDR, IDG, IDB are supplied, voltages corresponding to the data currents IDR, IDG, IDB are stored in the holding capacitor Cstg. On the other hand, in the pixel 20 to which the turn-off signal Vsig is supplied, the turn-off signal Vsig (drive voltage VDD) is supplied to the holding capacitor Cstg to turn off the drive transistor Tdr.

At this time, in the data driver 14, the latch transfer signal LAT changes from H level to L level. Further, in the same manner as described above, the data driver 14 receives the data driver start pulse SPX from the control circuit 12, and the pixels 20 on the first scanning line Yp2 (second scanning line Yr2) from the top. Digital data signals VDR, VDG, and VDB are sequentially input. As a result, the digital data signals VDR, VDG, and VDB of the pixels 20 on the first scanning line Yp2 that is the second from the top are stored in the latch units 45R, 45G, and 45B of the first memory unit 45 of the first latch circuit 14b. Stored in order.

(Period Z3)
In the period Z3, the scan driver 13 outputs the L-level first scan signal SCp1 and the H-level second scan signal SCr1. Thus, a light emission period (in this case, a light emission period of the first subframe SF1) in which each pixel 20 on the first scan line Yp1 (second scan line Tr1) performs a light emission operation is set. Accordingly, the reproduction selection transistor Trep of each pixel 20 on the first scanning line Yp1 (second scanning line Tr1) is turned on, and the programming transistor Tprg and the programming selection transistor Tsig are turned off. Therefore, the drive transistor Tdr of each pixel 20 on the first scan line Yp1 (second scan line Tr1) has a drive current Idr relative to the voltage of the holding capacitor Cstg held based on the data currents IDR, IDG, IDB. The supply current Ioled is supplied to the organic EL element 21. As a result, the organic EL element 21 emits light with a supply current Ioled relative to the data currents IDR, IDG, IDB. On the other hand, when the holding capacitor Cstg is held at a voltage based on the turn-off signal Vsig, the drive transistor Tdr is turned off and the supply current Ioled is not supplied to the organic EL element 21. Therefore, the organic EL element 21 does not emit light with the supply current Ioled relative to the data currents IDR, IDG, IDB.

This light emission / non-light emission state is maintained until the light emission / non-light emission control based on the new digital data signals VDR, VDG, VDB in the second subframe SF2.
In this period Z3, the digital data signals VDR, VDG, and VDB of each pixel 20 on the second first scanning line Yp2 (second scanning line Tr2) stored in the first latch circuit 14b from the second latch circuit 14b are stored in the second latch circuit. 14c. The scan driver 13 outputs an H level first scan signal SCp2 and an L level second scan signal SCr2. That is, it is a program period for each pixel 20 on the first scanning line Yp2 (second scanning line Tr2) that is the second from the top.

  Furthermore, the data driver start pulse SPX is input from the control circuit 12 to the data driver 14, and the digital data for the pixels 20 on the first scanning line Yp3 (second scanning line Yr3) third from the top. Signals VDR, VDG, and VDB are input in order. As a result, the digital data signals VDR, VDG, VDB of each pixel 20 on the third scanning line Yp3 third from the top are latched in the latch units 45R, 45G, 45B of the first memory unit 45 of the first latch circuit 14b. Stored in order.

  Thereafter, the same operation is performed, and when the light emission / non-light emission operation is completed for the pixel 20 on the lowest n-th first scan line Ypn (second scan line Yrn), the display operation of the first subframe SF1 is performed. Then, the operation for the second subframe SF2 is performed. The operation in the second subframe SF2 and the subsequent third to sixth subframes SF3 to SF6 are also repeated in the same manner as in the first subframe SF1, so that an image of one frame is displayed on each display panel unit 11. Represented by pixel 20. When the image display operation for one frame is completed, the image display operation for the next one frame is similarly performed.

  Therefore, for example, in the case where the gradation data D is the pixel 20 of “63” gradation, the data current IDR, in all the frames of the first to sixth subframes SF1 to SF6 based on the digital data signals VDR, VDG, and VDB. Emits light based on IDG and IDB. The light emission period T is T = TL1 + TL2 + TL3 + TL4 + TL5 + TL6.

In the case where the gradation data D is the pixel 15 having “15” gradation, light emission based on the data currents IDR, IDG, and IDB is performed in the first to fourth subframes SF1 to SF4 based on the digital data signals VDR, VDG, and VDB. And is turned off in the fifth and sixth subframes SF5 and SF6.
The light emission period T is T = TL1 + TL2 + TL3 + TL4.

  Further, in the case where the gradation data D is the pixel 20 of “3” gradation, light emission based on the data currents IDR, IDG, IDB is performed in the first and second subframes SF1, SF2 based on the digital data signals VDR, VDG, VDB. And is turned off in the third to sixth subframes SF3 to SF6. The light emission period T is T = TL1 + TL2.

  Further, in the case where the gradation data D is the pixel 20 of “6” gradation, the light emission based on the data currents IDR, IDG, IDB in the second and third subframes SF2, SF3 based on the digital data signals VDR, VDG, VDB. The first and fourth to sixth subframes SF1, SF4 to SF6 are turned off. The light emission period T is T = TL2 + TL3.

  That is, by supplying data currents IDR, IDG, IDB having a constant current value to the data lines X1 to X3m and changing the light emission period T according to the gradation data D, the pixel 20 is changed to the gradation data D. Apparently emit light with the corresponding brightness. Therefore, even in the case of the low gradation data D, since the large data currents IDR, IDG, IDB are supplied to the pixels 20 through the data lines, supply shortage due to the wiring capacity of the data lines does not occur. . In addition, constant data currents IDR, IDG, IDB are always supplied to the pixel 20 with respect to the gradation data D in the range of “0” to “63” gradation input from the external device. Therefore, the shift from the operating point at the time of supplying the data currents IDR, IDG, IDB of the driving transistor Tdr to the operating point at the time of light emission of the organic EL element 21 is always constant regardless of the value of the gradation data D. As a result, as in the prior art, the change in drain current due to the shift of the operating point differs for each data current value, so that the luminance relative to the data current value cannot be obtained and the luminance shift occurs. Disappear.

According to the above embodiment, the following effects can be obtained.
(1) In the present embodiment, the supply current Ioled having a constant current value is always supplied to the organic EL element 21 regardless of the gradation data D. Then, one frame is divided into first to sixth sub-frames SF1 to SF6, and the first to sixth sub-frames SF1 to SF6 are appropriately selected based on the gradation data D, and according to the gradation data D. An image can be expressed by a time-division gradation method for expressing halftones, a so-called current-programmed time gradation method.

  (2) In the present embodiment, the data currents IDR, IDG, and IDB are always set to constant current values that are large enough to prevent insufficient writing. Therefore, even in the case of the low gradation data D, since large data currents IDR, IDG, IDB are supplied to the pixels 20R, 20G, 20B, there is no shortage of writing due to the wiring capacity of the data lines. .

  Since constant data currents IDR, IDG, and IDB are supplied to the pixels 20R, 20G, and 20B with respect to the gradation data D, the organic EL element is determined from the operating point when the data currents IDR, IDG, and IDB of the driving transistor Tdr are supplied. The shift to the operating point at the time of light emission 21 is always constant regardless of the value of the gradation data D. Therefore, there is no problem that the change in drain current due to the shift of the operating point is different for each data current value, so that the luminance relative to the data current value cannot be obtained and the luminance shift occurs.

  (3) In the present embodiment, the current driver 14d is provided with the drive circuits 51R, 51G, and 51B corresponding to the data lines X1 to X3m. Each of the drive circuits 51R, 51G, 51B corresponds to one of the data currents IDR, IDG, IDB and the extinguishing signal Vsig with a constant current value based on the binary digital data signals VDR, VDG, VDB, respectively. Supplied to the data line. This makes it possible to easily realize halftone expression according to the gradation data D using the current programmed time gradation method.

(4) In the present embodiment, the m driving units 50 including the red driving circuit 51R, the green driving circuit 51G, and the blue driving circuit 51B are sequentially ordered one by one based on the output signal UX from the shift register 14a. The data currents IDR, IDG, and IDB are supplied to the respective storage capacitors 52 to be programmed. Therefore, since the data currents IDR, IDG, IDB are not supplied from the constant current circuit 15 to the red drive circuit 51R, the green drive circuit 51G, and the blue drive circuit 51B of all the drive units 50, the constant current circuit The load of 15 can be small and the circuit scale can be reduced.
(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the embodiment is the simple time-division gray scale driving shown in FIG. 8, but, as shown in FIG. 12, in one frame composed of the first to sixth subframes SF1 to SF6. The difference is that it is a time division gray scale provided with a non-light emitting period, that is, a time division gray scale by so-called reset driving. Here, portions different from the first embodiment will be described in detail, and portions having the same configuration are denoted by the same reference numerals, and detailed description thereof will be omitted.

  FIG. 8 is a block diagram of a main part for explaining the electrical configuration of the organic EL display device 10, and the scanning driver 13 and the data driver 14 are different from those in the above embodiment. The scan driver 13 includes a shift register 13c, a selection circuit 13d, and a level shifter 13e. Further, the scan driver 13 inputs a scan driver write start pulse SPYD and a scan driver erase start pulse SPYE instead of the scan driver start pulse SPY of the first embodiment, and newly inputs a write period selection signal INH. . The scan driver write start pulse SPYD, the scan driver erase start pulse SPYE, and the write period selection signal INH are generated by the control circuit 12 and output to the scan driver 13.

  On the other hand, the data driver 14 inputs a new data line reset control signal / RST. The data line reset control signal / RST is generated by the control circuit 12 and output to the data driver 14.

(Scanning driver 13)
As shown in FIG. 9, the shift register 13c of the scan driver 13 includes n first holding circuits 60 and n second hold circuits 60 corresponding to the first scan lines Yp1 to Ypn (second scan lines Yr1 to Yrn). A holding circuit 70 is included. In FIG. 9, two first holding circuits 60 and two holding circuits 70 are shown for convenience of explanation.

  Each first holding circuit 60 includes an inverter circuit 61, a latch unit 62, and a NAND circuit 63. The inverter circuit 61 of each first holding circuit 60 includes the scan driver clock inversion signal CBY in the inverter circuit 61 in the odd-numbered first holding circuit 60 and the inverter circuit 61 in the even-numbered first holding circuit 60. The scan driver clock signal CLY is input as a synchronization signal. The inverter circuit 61 of the odd-numbered first holding circuit 60 inputs the scan driver write start pulse SPYD in response to the rise of the scan driver clock inversion signal CBY and outputs it to the latch unit 62. The inverter circuit 61 of the first holding circuit 60 in the even-numbered stage inputs the scan driver write start pulse SPYD in response to the rise of the scan driver clock signal CLY and outputs it to the latch unit 62.

The latch unit 62 of each first holding circuit 60 includes two inverter circuits, and the scan driver clock signal CLY is supplied to the latch unit 62 of the odd-numbered first holding circuit 60 and the even-numbered first holding circuit. The scan driver clock inversion signal CBY is input to the latch unit 62 of 60 as a synchronization signal. The latch unit 62 of the odd-numbered first holding circuit 60 inputs and holds the scan driver write start pulse SPYD from the inverter circuit 61 in response to the rise of the scan driver clock signal CLY. The latch unit 62 of the even-numbered first holding circuit 60 inputs and holds the scan driver write start pulse SPYD from the inverter circuit 61 in response to the rising edge of the scan driver clock inversion signal CBY. Each latch unit 62 outputs the held scan driver write start pulse SPYD to the inverter circuit 61 of the first holding circuit 60 in the next stage.

  Therefore, the H-level scan driver write start pulse SPYD output from the control circuit 12 is synchronized with the scan driver clock signal CLY and the scan driver clock inversion signal CBY, and thus the first scan line Yp1 (second scan line Yr1). Are sequentially shifted from the first holding circuit 60 to the first holding circuit 60 of the first scanning line Ypn (second scanning line Trn).

  The NAND circuit 63 provided in the first holding circuit 60 has its input terminal connected to the output terminal of the latch unit 62 and the output terminal of the latch unit 62 provided in the first holding circuit 60 in the next stage. Therefore, the NAND circuit 63 of each first holding circuit 60 is low when the first holding circuit 60 and the latch unit 62 of the first holding circuit 60 at the next stage hold the scan driver write start pulse SPYD at the H level. The first output signal UY1 is output. Then, when the latch unit 62 of the first holding circuit 60 shifts the scan driver write start pulse SPYD and disappears, the NAND circuit 63 outputs the first output signal UY1 of H level. Thereafter, the NAND circuit 63 outputs the first output signal UY1 at the H level until the latch unit 62 holds a new scan driver write start pulse SPYD.

  It should be noted that during the period when the first output signal UY1 output from the first holding circuit 60 (NAND circuit 63) falls to L level and rises to H level, the scan driver clock signal CLY (scan driver clock inverted signal CBY) 1/2 period.

  Each second holding circuit 70 includes an inverter circuit 71, a latch unit 72, and a NAND circuit 73. The inverter circuit 71 of each second holding circuit 70 scans the inverter driver 71 of the odd-numbered second holding circuit 70 with the scan driver clock signal CLY and scans the inverter circuit 71 of the even-numbered second holding circuit 70 with the scan driver clock signal CLY. A driver clock inversion signal CBY is input as a synchronization signal. The inverter circuit 71 of the odd-numbered second holding circuit 70 inputs the scan driver erase start pulse SPYE in response to the rising edge of the scan driver clock signal CLY and outputs it to the latch unit 72. The inverter circuit 71 of the second holding circuit 70 in the even-numbered stage inputs the scan driver erase start pulse SPYE in response to the rise of the scan driver clock inversion signal CBY and outputs it to the latch unit 72.

  The latch unit 72 of each second holding circuit 70 includes two inverter circuits, and the scan driver clock inversion signal CBY is supplied to the latch unit 72 of the odd-numbered second holding circuit 70 for the second holding of the even-numbered stage. The scan driver clock signal CLY is input to the latch unit 72 of the circuit 70 as a synchronization signal. The latch unit 72 of the odd-numbered second holding circuit 70 inputs and holds the scan driver erasing start pulse SPYE from the inverter circuit 71 in response to the rising edge of the scan driver clock inversion signal CBY. The latch unit 72 of the even-numbered second holding circuit 70 inputs and holds the scan driver erasing start pulse SPYE from the inverter circuit 71 in response to the rising edge of the scan driver clock signal CLY. Each latch unit 72 outputs the held scan driver erasing start pulse SPYE to the inverter circuit 71 of the second holding circuit 70 in the next stage.

Accordingly, the H-level scan driver erasing start pulse SPYE output from the control circuit 12 is synchronized with the scan driver clock signal CLY and the scan driver clock inversion signal CBY, and the first scan line Yp1 (second scan line Yr1). The second holding circuit 70 is sequentially shifted to the second holding circuit 70 of the first scanning line Ypn (second scanning line Yrn).

  The NAND circuit 73 provided in the second holding circuit 70 has its input terminal connected to the output terminal of the latch unit 72 and the output terminal of the latch unit 72 provided in the second holding circuit 70 in the next stage. Therefore, the NAND circuit 73 of each second holding circuit 70 is in the L level when the second holding circuit 70 and the latch part 72 of the second holding circuit 70 in the next stage hold the scan driver erase start pulse SPYE at the H level. The second output signal UY2 is output. When the latch unit 72 of the second holding circuit 70 shifts the scan driver erasing start pulse SPYE and disappears, the NAND circuit 73 outputs the second output signal UY2 of H level. Thereafter, the NAND circuit 73 outputs the first output signal UY1 at the H level until the latch units 72 respectively hold new scan driver erasing start pulses SPYE.

  It should be noted that during the period when the second output signal UY2 output from the second holding circuit 70 (NAND circuit 73) falls to the L level and then rises to the H level, the scan driver clock signal CLY (scan driver clock inverted signal CBY) 1/2 period.

  The first output signal UY1 of each first holding circuit 60 and the second output signal UY2 of each second holding circuit 70 are output to the selection circuit 13d. The selection circuit 13d includes n selection units 75 corresponding to the first scanning lines Yp1 to Ypn (second scanning lines Yr1 to Yrn).

Each selection unit 75 includes first to fourth NOR circuits 75a to 75d. The first NOR circuit 75a is a NOR circuit having two input terminals. The first output signal UY1 is input from the corresponding first holding circuit 60 to one input terminal, and the inverter circuit 76 is input to the other input terminal. The write period selection signal INH is input via The second NOR circuit 75b is a NOR circuit having two input terminals, and the second output signal UY2 is input from the corresponding second holding circuit 70 to one input terminal, and the write period selection signal is input to the other input terminal. Enter INH. As shown in FIG. 11, the period selection signal INH is a signal that performs an inversion operation in a half cycle of the scan driver clock inversion signal CBY, and is in response to the rise and fall of the scan driver clock inversion signal CBY. A signal rises to the level. That is, the scan driver clock inversion signal CBY is inverted, and the first half until the next inversion operation is at the H level and the latter half is at the L level.

  Accordingly, the first NOR circuit 75a outputs an H level output signal when the first output signal UY1 is at the L level and the period selection signal INH is at the H level. That is, after the first holding circuit 60 holds the scan driver write start pulse SPYD, the first NOR circuit 75a outputs an H level output signal for the half period of the scan driver clock inversion signal CBY.

  On the other hand, the second NOR circuit 75b outputs an H level output signal when both the second output signal UY2 and the period selection signal INH are at the L level. That is, after the second holding circuit 70 holds the scan driver erasing start pulse SPYE and the half period of the scan driver clock inversion signal CBY has elapsed, the second NOR circuit is supplied for the half period of the scan driver clock inversion signal CBY. The circuit 75b outputs an H level output signal.

The third NOR circuit 75c is a NOR circuit having two input terminals, and an output signal from the first NOR circuit 75a is input to one input terminal, and an output from the second NOR circuit 75b is input to the other input terminal. A signal is input. Then, when one of the first NOR circuit 75a and the second NOR circuit 75b outputs an H level output signal, the third NOR circuit 75c outputs the L level third output signal UY3 to the next level shifter 13e. The data is output to the corresponding second scanning lines Yr1 to Yrn via the buffer circuit 77. Further, the third NOR circuit 75c is a level shifter that converts the H-level third output signal UY3 into the second scanning signals SCr1 to SCRN when both the first NOR circuit 75a and the second NOR circuit 75b output an L-level output signal. 13e is output to the corresponding second scanning lines Yr1 to Yrn via the buffer circuit 77.

  The fourth NOR circuit 75d is a NOR circuit having two input terminals, and one input terminal inputs the third output signal UY3 of the third NOR circuit 75c, and the other input terminal receives the program period control signal / WR. input. When the third output signal UY3 and the program period control signal / WR are both at the L level, the fourth NOR circuit 75d uses the fourth output signal UY4 at the H level as the first scanning signals SCp1 to SCpn and outputs from the next level shifter 13e. The data is output to the corresponding first scanning lines Yp1 to Ypn via the buffer circuit 78.

  As described above, the scan driver 13 turns on / off the program transistor Tprg, the program selection transistor Tsig, and the reproduction selection transistor Trep of the pixel 20 on each scan line based on the scan driver write start pulse SPYD. 1 and second scanning signals SCp1 to SCpn, SCr1 to SCrn are generated. Further, the scan driver 13 turns on / off the program transistor Tprg, the program selection transistor Tsig, and the reproduction selection transistor Trep of the pixel 20 on each scan line based on the scan driver erase start pulse SPYE. Second scan signals SCp1 to SCpn and SCr1 to SCrn are generated.

  Further, the scan driver 13 receives each of the first and second scan signals SCp1 to SCpn and SCr1 to SCrn based on the scan driver write start pulse SPYD based on the period selection signal INH, and each first holding circuit 60 scans the scan driver. After holding the write start pulse SPYD, the scan driver clock inversion signal CBY is inverted in order to select the pixel 20 during the first half cycle (write period in FIG. 11). Further, the scan driver 13 receives the first and second scan signals SCp1 to SCpn and SCr1 to SCrn based on the scan driver erasing start pulse SPYE based on the period selection signal INH. After the erase start pulse SPYE is held, it is inverted to select the pixel 20 during the second half of the scan driver clock inversion signal CBY (reset period in FIG. 11).

  That is, the scan driver 13 determines the start of the program period and the light emission period for each pixel 20 on each scan line during the write period based on the scan driver write start pulse SPYD. ~ SCrn is generated. The scan driver 13 also includes first and second scan signals SCp1 to SCpn1 and SCr1 that determine the start of the erase period and the extinction period for each pixel 20 on each scan line during the reset period based on the scan driver erase start pulse SPYE. ~ SCrn is generated.

(Data driver 14)
Next, the data driver 14 will be described. As shown in FIG. 8, the data driver 14 includes a shift register 14a, a first latch circuit 14b, a second latch circuit 14c, and a current driver 14d. In the present embodiment, the current driver 14d is different from the first embodiment.

As shown in FIG. 10, the current driver 14d has reset circuits 79R, 79G, and 79B for the red, green, and blue drive circuits 51R, 51G, and 51B of each drive unit 50, respectively. . The reset circuit 79 includes a NAND circuit 79a and an inverter circuit 79b. The NAND circuit 79a is a NAND circuit having two input terminals. One input terminal is connected to the corresponding latch units 46R, 46G, and 46B of the second memory unit 46, and the digital data signals VDR, VDG, and VDB are respectively connected thereto. Entered. In the NAND circuit 79a, the data line reset control signal / RST is input to the other input terminal. The output terminal of the NAND circuit 79a is connected to the gates of the first and second selection transistors Qe1 and Qe2 via the inverter circuit 79b. Note that the data line reset control signal / RST is a signal in phase with the write period selection signal INH, as shown in FIG.

  Therefore, when the data line reset control signal / RST is at the H level (writing period), the reset circuits 79R, 79G, and 79B first change the contents (H level or L level) of the digital data signals VDR, VDG, and VDB. And output to the gates of the second selection transistors Qe1 and Qe2. On the other hand, when the data line reset control signal / RST is at the L level (reset period), the reset circuits 79R, 79G, and 79B receive the L level signal (reset signal) regardless of the contents of the digital data signals VDR, VDG, and VDB. Is output to the gates of the first and second selection transistors Qe1 and Qe2.

  That is, when a scan line is selected based on the scan driver write start pulse SPYD, the pixels 20 on the scan line are supplied from the drive circuits 51R, 51G, and 51B of each drive unit 50 with digital data signals VDR, VDG, and VDB. The data currents IDR, IDG, IDB are supplied based on the contents of. On the other hand, when the scanning driver 13 selects the scanning line based on the scanning driver erasing start pulse SPYE, the pixels 20 on the scanning line are the drive circuits for red, green, and blue of each drive unit 50. A turn-off signal Vsig (drive voltage VDD) is supplied from 51R, 51G, 51B based on the reset signal.

In the present embodiment, as shown in FIG. 12, one frame is divided into first to sixth subframes SF1 to SF6, and periods TL1 to TL6 of the first to sixth subframes SF1 to SF6 are expressed as follows:
TL1: TL2: TL3: TL4: TL5: TL6 = 1: 2: 4: 8: 16: 32
Set the time ratio to And it is preset between the first subframe SF1 and the second subframe SF2, between the second subframe SF2 and the third subframe SF3, and between the third subframe SF3 and the fourth subframe SF4. The non-light emission period (light-out period) is set for the set time. The output timing of the scan driver write start pulse SPYD in the first to sixth subframes SF1 to SF6 and the output timing of the scan driver erase start pulse SPYE in the first to third subframes SF1 to SF3 are controlled. It is controlled in the circuit 12.

As described above, this embodiment also has the same effect as that of the above embodiment, and can easily realize halftone expression using time-division gradation by reset driving.
(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the selection of the first scanning lines Yp1 to Ypn is line sequential in order from the top to the bottom, but in this embodiment, the selection of the first scanning lines Yp1 to Ypn is not line sequential. The difference lies in the time-division gradation shown in FIG. 16 of so-called interlaced driving (non-sequential selection driving) that selects non-sequentially. Here, portions different from the first embodiment will be described in detail, and portions having the same configuration are denoted by the same reference numerals, and detailed description thereof will be omitted.

  FIG. 13 shows a block circuit diagram of an essential part for explaining the electrical configuration of the organic EL display device 10, and the scanning driver 13 is different from the first embodiment in its configuration. The scan driver 13 includes a decoder 13f, a selection circuit 13g, and a level shifter 13h. The scan driver 13 receives k-bit (k is a natural number) row selection driver address signals AY0 to AYk-1, a row selection driver output control signal INHY, a row selection driver latch transfer signal LATY, and the program period control signal / WR. Input from the control circuit 12.

The row selection driver address signals AY0 to AYk-1 are address signals that specify the first scanning lines Yp1 to Ypn (second scanning lines Yr1 to Yrn), respectively. The row selection driver address signals AY0 to AYk-1 are The output order is non-sequential and is controlled by the control circuit 12. Therefore, for the row selection driver address signals AY0 to AYk-1 output non-sequentially, the control circuit 12 selects the first scanning line Yp1 selected corresponding to the row selection driver address signals AY0 to AYk-1. Digital data signals VDR, YDG, and VDB for each pixel 20 on .about.Ypn (second scanning lines Yr1 to Yrn) are output to the data driver 14 accordingly.

(Scanning driver 13)
As shown in FIG. 14, the decoder 13f of the scan driver 13 is provided corresponding to the plurality of inverter circuits 80, the plurality of NAND circuits 81, and the first scan lines Yp1 to Ypn (second scan lines Yr1 to Yrn). It has n NOR circuits 82 and inputs k-bit row selection driver address signals AY0 to AYk-1. Based on the input k-bit row selection driver address signals AY0 to AYk-1, the decoder 13f performs one first scan among n first scan lines Yp1 to Ypn (second scan lines Yr1 to Yrn). A line (second scanning line) is identified, and an L level output signal is output from the NOR circuit 82 corresponding to the identified first scanning line (second scanning line). Therefore, every time the row selection driver address signals AY0 to AYk-1 are input, an H level output signal is output from any one of the n NOR circuits 82 to the selection circuit 13g in the next stage.

  The selection circuit 13g has n holding circuits 85 corresponding to the first scanning lines Yp1 to Ypn (second scanning lines Yr1 to Yrn). Each holding circuit 85 includes a switch 85a, a latch unit 85b, NOR circuits 85c and 85d, and an inverter circuit 85e. The switch 85a is composed of an N-channel MOS transistor and is connected between the corresponding NOR circuit 82 and the latch unit 85b. When the H level row selection driver latch transfer signal LATY is input to the gate of the switch 85a, The output signal from the circuit 82 is latched by the latch unit 85b.

  As shown in FIG. 15, the H level row selection driver latch transfer signal LATY is output every time row selection driver address signals AY0 to AYk-1 are input. Therefore, only one corresponding latch unit 85b among the latch units 85b of all the holding circuits 85 latches the H level output signal, and all the remaining latch units 85b latch the L level output signal.

  The latch unit 85b includes two inverter circuits, and latches an output signal from the NOR circuit 82. The output signal latched by the latch unit 85b is output to the NOR circuit 85c. The NOR circuit 85c is a NOR circuit having two input terminals, and the output signal latched by the latch unit 85b is input to one input terminal, and the row selection driver output control signal INHY is input to the other input terminal. The As shown in FIG. 15, the row selection driver output control signal INHY is a signal that becomes H level only once when the first scanning line is selected in each of the subframes SF1 to SF6, and thereafter becomes L level. .

  Therefore, the NOR circuit 85c outputs the third output signal UY3 at the L level from the inverter circuit 85e at the next stage when the row selection driver output control signal INHY is at the L level and the L level signal is output from the latch unit 85b. To do. In addition, when the row selection driver output control signal INHY is at the L level and the H level signal is output from the latch unit 85b, the NOR circuit 85c outputs the third output signal UY3 at the H level from the inverter circuit 85e at the next stage. To do. The third output signal UY3 is output as the second scanning signals SCr1 to SCrn to the corresponding second scanning lines Yr1 to Yrn via the buffer circuit 87 of the level shifter 13h.

The NOR circuit 85d is a NOR circuit having two input terminals, and one input terminal inputs the third output signal UY3 and the other input terminal inputs the program period control signal / WR. As shown in FIG. 15, the program period control signal / WR is a signal that becomes H level for a certain period every time selection of a new scanning line is started, and the program period control signal / WR of H level has a constant cycle. Each time it is output from the control circuit 12, a new scanning line formed by the row selection driver address signals AY0 to AYk-1 is selected.

  The NOR circuit 85d outputs the fourth output signal UY4 at the H level when both the third output signal UY3 and the program period control signal / WR are at the L level. The NOR circuit 85d outputs the fourth output signal UY4 at the H level when the third output signal UY3 is at the H level and the program period control signal / WR is at the L level. The fourth output signal UY4 is output to the corresponding first scanning lines Yp1 to Ypn via the buffer circuit 88 of the next level shifter 13h as the first scanning signals SCp1 to SCpn.

  With this configuration, in the first subframe SF1, the first first scanning line Yp1 → the 24th scanning line Yp24 → the 100th scanning line Yp100 → the 200th scanning line Yp200 from the top. Non-sequential selection such as → second scanning line Yp2 →... Is performed based on row selection driver address signals AY0 to AYk−1 output from the control circuit 12. At this time, the control circuit 12 makes the data driver 14 each pixel 20 on the first scanning line Yp1 → each pixel 20 on the scanning line Yp24 → each pixel 20 on the scanning line Yp100 → each pixel 20 on the scanning line Yp200 → Digital data signals VDR, VDG, and VDB of each pixel 20 are output in a dot-sequential order in the order of each pixel 20 of the scanning line Yp2. Then, each pixel 20 on the selected scanning line emits light with a supply current Ioled relative to the data currents IDR, IDG, IDB based on the digital data signals VDR, VDG, VDB.

  When all the scanning lines are selected in the first subframe SF1, the scanning lines in the next second subframe SF2 are selected. In this case, the scanning lines are selected in the same order as in the first subframe, and each pixel 20 on the selected scanning line is supplied with the supply current Ioled relative to the data currents IDR, IDG, IDB based on the digital data signals VDR, VDG, VDB. Activate the flash with. Thereafter, similarly, the third to sixth sub-frames SF3 to SF6 are similarly performed, and an image of one frame is displayed on the display panel unit 11.

As described above, this embodiment also has the same effect as that of the first embodiment, and can easily realize halftone expression using time-division gradation by interlaced driving.
(Fourth embodiment)
Next, application of the organic EL display device 10 to an electronic apparatus as the electro-optical device described in the above embodiment will be described with reference to FIG. The organic EL display device 10 can be applied to various electronic devices such as mobile personal computers, portable telephones such as mobile phones, viewers, and game machines, electronic books, and electronic paper. The organic EL display device 10 can also be applied to various electronic devices such as a video camera, a digital camera, a car navigation system, a car stereo, a driving operation panel, a personal computer, a printer, a scanner, a television, and a video player.

  FIG. 17 is a perspective view showing the configuration of the mobile personal computer. In FIG. 17, the mobile personal computer 100 includes a main body 102 including a keyboard 101 and a display unit 103 using the organic EL display device 10. Even in this case, the display unit 103 using the organic EL display device 10 exhibits the same effect as that of the first embodiment. As a result, the mobile personal computer 100 can realize display with excellent display quality.

In addition, you may change each said embodiment as follows.
In the above embodiment, the halftone of 64 gradations is controlled by the time division gradation, but the halftone of 16 gradations, the halftone of 32 gradations, the halftone of 128 gradations, the halftone of 256 gradations, etc. The present invention may be applied to the control of time-division gradation of halftones.

  In the above embodiment, the organic EL element 21 is embodied as an electro-optical element, but may be embodied as an inorganic electroluminescence element. That is, you may apply to the inorganic electroluminescent display apparatus which consists of an inorganic electroluminescent element.

  In the above embodiment, an example using an organic EL element has been described. However, the present invention is not limited to this, and a liquid crystal element, a digital micromirror device (DMD) FED (Field Emission Display), or a SED (Surface) is used. -It can also be applied to a conduction electron-emitter display.

The block circuit diagram which shows the electric constitution of the organic electroluminescent display apparatus of 1st Embodiment. Similarly, the block circuit diagram which shows the circuit structure of a display panel part. Similarly, a circuit diagram of a pixel. Similarly, the circuit diagram which shows the structure of a scanning driver. Similarly, the circuit diagram which shows the structure of a data driver. Similarly, a time chart for explaining the operation. Similarly, an explanatory diagram for explaining time-division gradations in which one frame is a first to sixth subframe. The principal part block circuit diagram for demonstrating the electrical constitution of the organic electroluminescent display apparatus of 2nd Embodiment. Similarly, the circuit diagram which shows the structure of a scanning driver. Similarly, the circuit diagram which shows the structure of a data driver. Similarly, a time chart for explaining the operation. Similarly, an explanatory diagram for explaining time-division gray scales by reset driving in which one frame is a first to sixth sub-frame. The principal part block circuit diagram for demonstrating the electrical constitution of the organic electroluminescent display apparatus of 3rd Embodiment. Similarly, the circuit diagram which shows the structure of a scanning driver. Similarly, a time chart for explaining the operation. Similarly, an explanatory diagram for explaining time-division gradation by interlaced driving in which one frame is made a first to sixth subframe. The perspective view which shows the structure of the mobile type personal computer for describing 4th Embodiment. The drain voltage-drain current characteristic view in each gate voltage of the drive transistor which drives an organic EL element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Organic electroluminescence display device as an electro-optical device, 11 ... Display panel part, 12 ... Control circuit, 13 ... Scan driver, 13a ... Shift register, 13b ... Level shifter, 14 ... Data driver as current generation circuit, 14a ... Shift register constituting program circuit, 14b... First latch circuit constituting program circuit, 14c... Second latch circuit constituting program circuit, 14d... Current driver as current generation circuit, 15. Pixel: 20R: Red pixel, 20G: Green pixel, 20B: Blue pixel, 21: Organic electroluminescence element, 40: Holding circuit, 45: First memory unit, 46: Second memory unit, 50: Current generation Drive unit, Tdr... Drive transistor, Tprg... Programming transistor Tsig ... program during the selection transistor, Trep ...
Selection transistor during reproduction, Cstg, holding capacitor, X1-X3m, data line as output line, Yp1-Ypn, first scanning line, Yr1-Yrn, second scanning line, IDR, data current for red as reference current, IDG: Data current for green as a reference current, IDB: Data current for blue as a reference current, Vsig: Light-off signal as a voltage signal, VDR: Digital data for red as determination data, VDG: Data for green as determination data Digital data, VDB... Blue digital data as determination data, SF1 to SF6... First to sixth subframes.

Claims (13)

In the current generation circuit,
A plurality of current generators;
A program circuit unit for sequentially programming a reference current having a constant current value for outputting a data current having a constant current value to an output line corresponding to each of the plurality of current generation units;
After the reference current is programmed for all of the current generators, each current generator is connected to a corresponding output line in the program circuit unit based on the value of the programmed reference current. A current generation circuit for outputting a data current having the constant current value. The current generation circuit according to claim 1,
The program circuit unit includes:
For each of the plurality of current generation units, a latch circuit that sequentially holds determination data for determining whether or not to output a data current having a constant current value to the corresponding output line,
Each of the current generators outputs either the data current or a voltage signal different from the data current to a corresponding output line based on determination data. The current generation circuit according to claim 1 or 2,
The program circuit unit includes:
A shift register having a plurality of holding circuits and sequentially shifting the start pulse in response to the clock signal with respect to the plurality of holding circuits;
A first memory unit provided corresponding to each holding circuit of the shift register, and each memory unit receives the constant from the corresponding current generation unit when the corresponding holding circuit latches the start pulse; A first latch circuit for storing determination data for determining whether or not to output a data current of a current value;
When the first latch circuit has a second memory unit provided corresponding to each of the first memory units, and all the first memory units of the first latch circuit store the corresponding determination data, Each of the corresponding second memory units stores the determination data stored in each of the first memory units at the same time, and the stored determination data is simultaneously output to each of the corresponding current generation units. A current generation circuit comprising two latch circuits. The current generation circuit according to claim 3.
Each of the current generators programs the reference current when the holding circuit of the corresponding shift register latches the start pulse, and uses the determination data of the second memory unit of the corresponding second latch circuit. A current generation circuit that outputs either the data current or the voltage signal based on the data current. The current generation circuit according to claim 4,
Each of the current generators outputs the voltage signal regardless of the determination data when a reset control signal is input. In the current generation circuit according to any one of claims 1 to 5,
Each of the current generators has a holding capacitor and a drive transistor, inputs the reference current, and uses a drive current having a constant current value supplied from the drive transistor according to the value of the reference current as the data current. A current generation circuit that outputs to each output line. An electro-optical device comprising the current generation circuit according to claim 1 as a data driver. The electro-optical device according to claim 7.
A data driver provided with current generation units of the current generation circuit for supplying a data current having a constant current value to each pixel on the selected scanning line, as many as the number of data lines;
1. An electro-optical device comprising: a scanning driver that divides one frame into a plurality of different sub-frames and appropriately selects each scanning line for each sub-frame. The electro-optical device according to claim 8.
The data driver outputs a turn-off signal regardless of determination data for determining whether or not to output a data current having a constant current value when a reset control signal is input,
An electro-optical device, wherein the scanning driver generates a selection signal for appropriately selecting each scanning line in order to cause each pixel to emit no light. The electro-optical device according to claim 8 or 9,
The electro-optical device, wherein the scan driver selects scan lines in a non-sequential manner. The electro-optical device according to any one of claims 8 to 10,
The pixel includes a holding capacitor, a driving transistor, and an electro-optic element. The data current having the constant current value is input, and the driving current having a constant current value supplied from the driving transistor is electrically supplied according to the data current value. An electro-optical device that is supplied to an optical element. The electro-optical device according to claim 11.
The electro-optic device is an organic electroluminescence device. An electronic apparatus comprising the electro-optical device according to claim 7.

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