JP2005129818A - Wiring board, and mounting structure thereof - Google Patents

Wiring board, and mounting structure thereof Download PDF

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JP2005129818A
JP2005129818A JP2003365490A JP2003365490A JP2005129818A JP 2005129818 A JP2005129818 A JP 2005129818A JP 2003365490 A JP2003365490 A JP 2003365490A JP 2003365490 A JP2003365490 A JP 2003365490A JP 2005129818 A JP2005129818 A JP 2005129818A
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semiconductor element
insulating substrate
wiring board
circuit board
wiring
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Kazutaka Maeda
和孝 前田
Shoichi Nakagawa
彰一 仲川
Tomoko Tajiri
智子 田尻
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Kyocera Corp
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board and its secondary mounting structure wherein a semiconductor element is mounted on the surface of its insulating substrate, and the destruction of the semiconductor element which is caused by the thermal stress thereof is so prevented effectively as to make its primary mounting reliability high, and at the same time, its secondary mounting reliability is so excellent that the reduction of its primary mounting reliability is also suppressed in its secondary mounting structure of it mounted secondarily on a printed board, etc. <P>SOLUTION: The wiring board comprises an insulating substrate having on the surface thereof a semiconductor element mounting region, a joining land formed on the rear surface of the insulating substrate and for joining thereto an external circuit board, and a wiring layer formed in the insulating substrate and for connecting electrically the joining land with a semiconductor element. Further, on the surface of the insulating substrate, recessed portions or slits are formed in at periphery of the semiconductor-element mounting region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体素子が搭載される配線基板及び該配線基板を外部回路基板に導体層を介して接続するのに適した実装構造に関する。   The present invention relates to a wiring board on which a semiconductor element is mounted and a mounting structure suitable for connecting the wiring board to an external circuit board via a conductor layer.

近年、高度情報化時代を迎え、情報通信技術が急速に発達し、それに伴い、各種半導体素子の高速化、大型化が図られている。この結果、半導体素子が搭載される配線基板（表面や内部に配線層を設けた絶縁基板から構成されている）においても、信号の伝送損失を低減するために、配線基板に設けられている配線層の低抵抗化と絶縁基板の低誘電率化が求められており、このような要求を満足するものとして、１０００℃以下での焼成によって緻密化でき、銅、銀または金等の低抵抗金属を主成分とする配線層との同時焼成が可能で且つ誘電率の低いガラスセラミックスを、絶縁基板として用いた配線基板が提案されている。   In recent years, with the advent of advanced information technology, information communication technology has rapidly developed, and accordingly, various semiconductor elements have been increased in speed and size. As a result, in order to reduce signal transmission loss even in a wiring board on which a semiconductor element is mounted (consisting of an insulating board having a wiring layer provided on the surface or inside), wiring provided on the wiring board is provided. Lowering the resistance of the layer and lowering the dielectric constant of the insulating substrate are required. To satisfy these requirements, it can be densified by firing at 1000 ° C. or lower, and a low-resistance metal such as copper, silver or gold There has been proposed a wiring board using glass ceramics having a low dielectric constant that can be co-fired with a wiring layer containing as a main component.

また、半導体としてシリコンを用いた半導体素子に関しては、微細配線化、高速化が、特に急速に推し進められている。例えば、高速信号処理を行う半導体装置において、素子内部のトランジスタ間を接続する配線の微細化と、半導体素子の内部配線の低抵抗化、および層間絶縁膜の低誘電率化が進められている。   In addition, regarding semiconductor elements using silicon as a semiconductor, fine wiring and high speed are being promoted particularly rapidly. For example, in a semiconductor device that performs high-speed signal processing, miniaturization of wiring connecting transistors in an element, reduction of resistance of internal wiring of a semiconductor element, and reduction of dielectric constant of an interlayer insulating film are being promoted.

半導体素子の層間絶縁膜として、従来は誘電率が４程度のＳｉＯ２が用いられてきたが、この絶縁膜をさらに低誘電率化すると、その機械的特性が低下する（即ち脆くなる）ことが良く知られている。特に、誘電率が２程度と非常に低い誘電率が得られる多孔質の絶縁膜を用いると、高速信号処理を低損失で行うことが可能となるため非常に望ましいが、その一方で、機械的特性の低下が著しくなり、素子の機械的耐性が著しく劣化する。 Conventionally, SiO 2 having a dielectric constant of about 4 has been used as an interlayer insulating film of a semiconductor element. However, if this insulating film is further reduced in its dielectric constant, its mechanical characteristics may deteriorate (ie, become brittle). Well known. In particular, the use of a porous insulating film having a dielectric constant as low as 2 is very desirable because high-speed signal processing can be performed with low loss. The deterioration of the characteristics becomes remarkable, and the mechanical resistance of the device is remarkably deteriorated.

ところで、半導体素子収納用パッケージに代表される配線基板上に、半導体素子を実装（以下一次実装と称す）して半導体装置を組み立てる際には、半導体素子を配線基板にしっかりと固定するために、通常、その接合部分に熱硬化性樹脂を用いたアンダーフィル剤を充填して熱硬化させる（キュア工程）。このため、上記のような低誘電率の絶縁膜を使用した半導体素子を用いた場合には、一次実装時の熱処理に際して、半導体素子と配線基板中の絶縁基板との間の熱膨張係数のミスマッチにより熱応力が発生し、機械的耐性の低い半導体素子が破壊してしまうといった問題が懸念されている。また、同様の熱応力は、半導体素子のＯＮ／ＯＦＦに伴う発熱／冷却によっても発生し、この場合にも、半導体素子の破壊という問題を生じる。さらに、半導体素子が大型化すると熱応力がそれに伴い大きくなるため、半導体素子が破壊する危険性が増大する。   By the way, when assembling a semiconductor device by mounting a semiconductor element on a wiring board represented by a package for housing a semiconductor element (hereinafter referred to as primary mounting), in order to firmly fix the semiconductor element to the wiring board, Usually, the joint portion is filled with an underfill agent using a thermosetting resin and cured (curing process). For this reason, when a semiconductor element using an insulating film having a low dielectric constant as described above is used, the thermal expansion coefficient mismatch between the semiconductor element and the insulating substrate in the wiring board during the heat treatment during primary mounting. As a result, thermal stress is generated, and there is a concern that a semiconductor element having low mechanical resistance is destroyed. The same thermal stress is also generated by heat generation / cooling accompanying ON / OFF of the semiconductor element, and in this case, the problem of destruction of the semiconductor element occurs. Furthermore, since the thermal stress increases with an increase in the size of the semiconductor element, the risk of the semiconductor element breaking up increases.

このような見地から、一次実装等による熱応力を低減するために、配線基板中の絶縁基板の熱膨張係数を、シリコンの熱膨張係数（２〜４×１０−６／℃：４０〜４００℃）に近似させることが求められており、例えば、ムライト、石英ガラス、ほう珪酸ガラスからなるガラスセラミック焼結体を絶縁基板とすることで、低熱膨張係数の多層セラミック回路基板を得ることが提案されている（特許文献１参照）。また、ＳｉＯ２、Ｂ２Ｏ３、Ｋ２Ｏ、Ａｌ２Ｏ３からなる硼珪酸ガラスとアルミナ、コージェライト、石英ガラスとを組み合わせることにより、低抵抗配線が可能な低熱膨張係数のセラミック絶縁基板を得ることが提案されている（特許文献２参照）。
特公平４−５８１９８号公報 特開平５−２５４９２３号公報 From such a viewpoint, in order to reduce the thermal stress due to the primary mounting or the like, the thermal expansion coefficient of the insulating substrate in the wiring board is changed to the thermal expansion coefficient of silicon (2 to 4 × 10 −6 / ° C .: 40 to 400 ° C. For example, it is proposed to obtain a multilayer ceramic circuit board having a low thermal expansion coefficient by using a glass ceramic sintered body made of mullite, quartz glass, or borosilicate glass as an insulating substrate. (See Patent Document 1). Also, a ceramic insulating substrate having a low thermal expansion coefficient capable of low resistance wiring by combining borosilicate glass made of SiO 2 , B 2 O 3 , K 2 O, and Al 2 O 3 with alumina, cordierite, and quartz glass. Has been proposed (see Patent Document 2).
Japanese Examined Patent Publication No. 4-58198 JP-A-5-254923

しかるに、特許文献１や２に記載されたガラスセラミック焼結体を絶縁基板として用いた場合には、低い熱膨張係数を実現しているため、熱応力が緩和され、例えば１次実装の信頼性を確保できるが、半面、４０〜１５０℃における熱膨張係数が１５〜２０×１０−６／℃程度と非常に大きいプリント配線基板で構成される外部回路基板上に、半導体装置を実装（以下、２次実装と称す。）する際には、セラミック絶縁基板とプリント基板との熱膨張係数のミスマッチが非常に大きくなる。配線基板（絶縁基板）と外部回路基板との熱膨張差が大きいと、配線基板は上に凸の反り変形により応力を緩和しようとするため、１次実装された半導体素子周辺、特にコーナー部（角部）では、この反り変形により高い熱応力が発生してしまい、結果として、１次実装信頼性が損なわれてしまうという問題があった。即ち、半導体素子が搭載された１次実装構造では、その実装信頼性を確保することはできるのであるが、プリント基板等の外部回路基板に実装された２次実装構造においては、その信頼性の確保が困難であり、１次実装構造の信頼性が損なわれてしまう（２次実装信頼性が低い）という問題があった。 However, when the glass ceramic sintered body described in Patent Documents 1 and 2 is used as an insulating substrate, a low thermal expansion coefficient is realized, so that thermal stress is relieved, for example, reliability of primary mounting. However, on the other hand, a semiconductor device is mounted on an external circuit board (hereinafter referred to as a printed circuit board) having a very large thermal expansion coefficient at 40 to 150 ° C. of about 15 to 20 × 10 −6 / ° C. When this is referred to as secondary mounting), the mismatch between the thermal expansion coefficients of the ceramic insulating substrate and the printed circuit board becomes very large. If the difference in thermal expansion between the wiring board (insulating board) and the external circuit board is large, the wiring board tries to relieve stress by upwardly warping deformation, so the periphery of the primarily mounted semiconductor element, particularly the corner ( In the corner portion, a high thermal stress is generated by this warpage deformation, and as a result, there is a problem that the primary mounting reliability is impaired. That is, in the primary mounting structure on which the semiconductor element is mounted, the mounting reliability can be ensured. However, in the secondary mounting structure mounted on an external circuit board such as a printed circuit board, the reliability is high. There is a problem that securing is difficult and reliability of the primary mounting structure is impaired (secondary mounting reliability is low).

従って、本発明の目的は、絶縁基板表面に半導体素子が搭載される配線基板において、熱応力による半導体素子の破壊が有効に防止され、１次実装信頼性が高いと同時に２次実装信頼性にも優れ、プリント基板等に２次実装される２次実装構造においても１次実装信頼性の低下が抑制された配線基板とその２次実装構造を提供することにある。   Accordingly, an object of the present invention is to effectively prevent destruction of a semiconductor element due to thermal stress in a wiring board on which a semiconductor element is mounted on the surface of an insulating substrate, and at the same time has high primary mounting reliability and secondary mounting reliability. Another object of the present invention is to provide a wiring board and a secondary mounting structure in which a reduction in primary mounting reliability is suppressed even in a secondary mounting structure that is secondarily mounted on a printed circuit board or the like.

本発明によれば、表面に半導体素子搭載領域を有する絶縁基板と、絶縁基板裏面に形成された外部回路基板との接合用ランド部と、該絶縁基板に形成され、該接合用ランド部を半導体素子に電気的に接続するための配線層とからなる配線基板において、
前記絶縁基板表面には、半導体素子搭載領域の周囲に凹部またはスリットが形成されていることを特徴とする配線基板が提供される。 According to the present invention, an insulating substrate having a semiconductor element mounting region on the front surface, a bonding land portion between the external circuit substrate formed on the back surface of the insulating substrate, and the bonding land portion formed on the insulating substrate. In a wiring board composed of a wiring layer for electrically connecting to an element,
On the surface of the insulating substrate, there is provided a wiring substrate characterized in that a recess or a slit is formed around the semiconductor element mounting region.

本発明によれば、また、上記の配線基板を、４０〜１５０℃における熱膨張係数が１０×１０−６／℃以上の有機樹脂を含む絶縁体基板の表面に接合用ランド部が形成された外部回路基板上に載置し、前記配線基板のランド部と前記外部回路基板の前記ランド部とを導体層によって電気的に接続固定してなる実装構造が提供される。 According to the present invention, a bonding land portion is formed on the surface of an insulating substrate containing an organic resin having a thermal expansion coefficient of 10 × 10 −6 / ° C. or higher at 40 to 150 ° C. A mounting structure is provided which is mounted on an external circuit board and electrically connected and fixed to the land portion of the wiring board and the land portion of the external circuit board by a conductor layer.

本発明の配線基板においては、絶縁基板表面の半導体素子搭載領域の周辺に、凹部またはスリットを設けたことが重要な特徴であり、このような凹部またはスリットにより、この配線基板を外部回路基板に実装（２次実装）した実装構造において、絶縁基板と外部回路基板との熱膨張差によって半導体素子に発生する熱応力を有効に低減することができ、２次実装信頼性を確保することが可能となる（２次実装構造においても、１次実装信頼性の低下を抑制することができる）。即ち、絶縁基板と外部回路基板との熱膨張差に起因する反り変形による半導体素子周辺部（特にコーナー部）への応力集中が緩和され、このような応力集中による半導体素子の破損を有効に防止することができるのである。例えば、前述した機械的強度の低い半導体素子を用いた場合においても、このような半導体素子の熱応力による破損を有効に防止することが可能である。   In the wiring board of the present invention, it is an important feature that a recess or a slit is provided around the semiconductor element mounting region on the surface of the insulating substrate, and the wiring board is formed on the external circuit board by such a recess or slit. In the mounted structure (secondary mounting), the thermal stress generated in the semiconductor element due to the difference in thermal expansion between the insulating substrate and the external circuit board can be effectively reduced, and the secondary mounting reliability can be secured. (Even in the secondary mounting structure, it is possible to suppress a decrease in primary mounting reliability). That is, the stress concentration on the periphery of the semiconductor element (particularly the corner) due to the warp deformation caused by the difference in thermal expansion between the insulating substrate and the external circuit board is alleviated, and damage to the semiconductor element due to such stress concentration is effectively prevented. It can be done. For example, even when the above-described semiconductor element with low mechanical strength is used, it is possible to effectively prevent such a semiconductor element from being damaged by thermal stress.

本発明の配線基板において、絶縁基板表面の前記凹部は、半導体素子搭載領域の全周を取り囲むように無端状に形成することができる。即ち、絶縁基板表面に搭載（１次実装）される半導体素子は、この凹部によって完全に取り囲まれるため、この半導体素子周辺部への応力集中が有効に緩和され、２次実装構造での熱応力に起因する１次実装の信頼性低下を確実に且つ有効に防止することができる。   In the wiring board of the present invention, the recess on the surface of the insulating substrate can be formed endlessly so as to surround the entire circumference of the semiconductor element mounting region. That is, since the semiconductor element mounted on the surface of the insulating substrate (primary mounting) is completely surrounded by the recess, the stress concentration on the periphery of the semiconductor element is effectively alleviated, and the thermal stress in the secondary mounting structure is reduced. Therefore, it is possible to reliably and effectively prevent a decrease in the reliability of the primary mounting due to the above.

また、本発明の配線基板においては、前記凹部を、半導体素子搭載領域の各コーナー部にのみ形成することもできる。即ち、２次実装構造において、絶縁基板と外部回路基板との熱膨張差に起因する上に凸の反り変形により発生する応力は、半導体素子のコーナー部（角部）に特に集中する。従って、半導体素子搭載領域の各コーナー部にのみ前記凹部を形成することによっても、上記の反り変形による応力集中を有効に緩和することができ、１次実装信頼性の低下を回避することができるのである。   In the wiring board of the present invention, the concave portion can be formed only at each corner portion of the semiconductor element mounting region. That is, in the secondary mounting structure, the stress generated by the upward warp deformation caused by the difference in thermal expansion between the insulating substrate and the external circuit substrate is particularly concentrated on the corner portion (corner portion) of the semiconductor element. Therefore, even if the concave portions are formed only at the corner portions of the semiconductor element mounting region, the stress concentration due to the warp deformation can be effectively mitigated, and the deterioration of the primary mounting reliability can be avoided. It is.

さらに、前記凹部の深さは、絶縁基板厚みの１０％以上であることが好ましい。この凹部の深さが浅いと、反り変形による応力を十分に緩和することが困難となり、２次実装構造における１次実装信頼性低下を回避することが困難となるおそれがあるからである。   Furthermore, the depth of the recess is preferably 10% or more of the thickness of the insulating substrate. This is because if the depth of the concave portion is shallow, it is difficult to sufficiently relieve stress due to warp deformation, and it may be difficult to avoid a decrease in primary mounting reliability in the secondary mounting structure.

また、凹部の代わりにスリットを形成する場合、このようなスリットは、絶縁基板を貫通して設けられるものであるため、半導体素子搭載領域の全周にわたって形成することはできないが、該領域のコーナー部に形成することが好ましい。即ち、反り変形による応力は、搭載された半導体素子のコーナー部に集中するため、半導体素子搭載領域のコーナー部にスリットを形成することにより、このような応力集中を有効に緩和することができるからである。   When slits are formed instead of the recesses, since such slits are provided through the insulating substrate, they cannot be formed over the entire circumference of the semiconductor element mounting region. It is preferable to form in a part. That is, stress due to warping deformation is concentrated at the corner portion of the mounted semiconductor element. Therefore, by forming a slit at the corner portion of the semiconductor element mounting region, such stress concentration can be effectively reduced. It is.

また、前記絶縁基板は、ガラスセラミックス焼結体からなっていることが好ましい。即ち、ガラスセラミックス焼結体からなる絶縁基板を用いることにより、この絶縁基板の熱膨張係数を低減させ、この熱膨張係数をシリコンの熱膨張係数に近似させることができ、絶縁基板とシリコン半導体との熱膨張のミスマッチを低減させ、１次実装での信頼性を高めることができる。   The insulating substrate is preferably made of a glass ceramic sintered body. That is, by using an insulating substrate made of a glass ceramic sintered body, the thermal expansion coefficient of the insulating substrate can be reduced, and the thermal expansion coefficient can be approximated to the thermal expansion coefficient of silicon. The thermal expansion mismatch can be reduced, and the reliability in the primary mounting can be improved.

本発明において、上述した配線基板を外部回路基板に実装（２次実装）した実装構造においては、外部回路基板として、４０〜１５０℃における熱膨張係数が１０×１０−６／℃以上の有機樹脂を含む絶縁体基板を用いているが、このような高熱膨張係数の絶縁体基板を外部回路基板として使用しているにもかかわらず、この２次実装構造において１次実装信頼性が損なわれることがない。即ち、上記のように高熱膨張係数の外部回路基板（絶縁体基板）を用いると、この外部回路基板と配線基板中の絶縁基板との熱膨張差が大きくなる。特に、配線基板中の絶縁基板として、シリコンの熱膨張係数に近似したものを使用する場合には、その熱膨張係数は低いため、２次実装構造での両者の熱膨張差はかなり大きくなる。この結果、配線基板は、既に述べた通り、上に凸の反り変形により応力を緩和し、１次実装された半導体素子周辺、特にコーナー部（角部）では、この反り変形により高い熱応力が発生してしまい、１次実装信頼性が損なわれてしまう。しかるに、上述した配線基板を用いた本発明の実装構造では、このような反り変形による半導体素子周辺部での応力が有効に緩和されるため、１次実装の信頼性低下を有効に回避することができる。 In the present invention, in the mounting structure in which the wiring board described above is mounted on the external circuit board (secondary mounting), an organic resin having a thermal expansion coefficient at 40 to 150 ° C. of 10 × 10 −6 / ° C. or more is used as the external circuit board. In this secondary mounting structure, the reliability of primary mounting is spoiled even though an insulating substrate having such a high thermal expansion coefficient is used as an external circuit board. There is no. That is, when an external circuit board (insulator board) having a high thermal expansion coefficient is used as described above, the difference in thermal expansion between the external circuit board and the insulating board in the wiring board increases. In particular, when an insulating substrate in the wiring board that is similar to the thermal expansion coefficient of silicon is used, the thermal expansion coefficient is low, so the difference in thermal expansion between the two in the secondary mounting structure becomes considerably large. As a result, as described above, the wiring board relieves stress by upwardly warping deformation, and high thermal stress is generated by this warping deformation around the semiconductor element that is primarily mounted, particularly at the corner (corner). It will occur and primary mounting reliability will be impaired. However, in the mounting structure of the present invention using the above-described wiring board, stress at the periphery of the semiconductor element due to such warpage deformation is effectively relieved, so that a decrease in reliability of primary mounting is effectively avoided. Can do.

本発明の実装構造においては、前記配線基板の絶縁基板の熱膨張係数が、前記外部回路基板の熱膨張係数よりも小さいことが好適である。即ち、この熱膨張係数を小さくして、例えばシリコンの熱膨張係数（２〜４×１０−６／℃：４０〜４００℃）に近似させることにより、高速信号伝送特性に適したシリコン半導体素子等に対する１次実装信頼性を向上させることができる。 In the mounting structure of the present invention, it is preferable that a thermal expansion coefficient of the insulating substrate of the wiring board is smaller than a thermal expansion coefficient of the external circuit board. That is, by reducing this thermal expansion coefficient, for example, by approximating the thermal expansion coefficient of silicon (2-4 × 10 −6 / ° C .: 40-400 ° C.), a silicon semiconductor element suitable for high-speed signal transmission characteristics, etc. Primary mounting reliability can be improved.

以下、添付図面に示す具体例に基づき、本発明を詳細に説明する。
図１は、本発明の配線基板が外部回路基板上に２次実装された実装構造を説明するための横断面図であり、図２は、図１で示される配線基板に形成される凹部の配置例を示す平面図である。 Hereinafter, the present invention will be described in detail based on specific examples shown in the accompanying drawings.
FIG. 1 is a cross-sectional view for explaining a mounting structure in which a wiring board of the present invention is secondarily mounted on an external circuit board. FIG. 2 shows a recess formed in the wiring board shown in FIG. It is a top view which shows the example of arrangement | positioning.

図１及び図２を参照して、全体としてＡで示す配線基板の表面には、半導体素子Ｂが実装（１次実装）されており、また、この配線基板Ａは、Ｃで示す外部回路基板に実装（２次実装）されている。尚、図１に示されたような配線基板Ａに半導体素子Ｂが実装された構造は、いわゆるＢＧＡ型パッケージと呼ばれている。   1 and 2, a semiconductor element B is mounted (primary mounting) on the surface of a wiring board indicated by A as a whole, and this wiring board A is an external circuit board indicated by C. (Secondary mounting). The structure in which the semiconductor element B is mounted on the wiring board A as shown in FIG. 1 is called a so-called BGA type package.

配線基板Ａは、絶縁基板１と、その表裏面及び内部に形成された配線層３（ビアホール導体を含む）から構成されている。絶縁基板１の表面（上面）中央部（半導体素子搭載領域）には、半導体素子Ｂが、半田などの導体５により配線層３と電気的に接続される。さらに、ロウ材５の周囲には、エポキシ樹脂等の熱硬化性樹脂を含有するアンダーフィル材７が充填し、硬化されており、これにより、半導体素子Ｂは、配線基板Ａの表面（絶縁基板１の表面）にしっかりと固定され、しかも、この接続部に生じる応力を緩和し、１次実装の信頼性が高められている。   The wiring board A is composed of an insulating substrate 1 and wiring layers 3 (including via-hole conductors) formed on the front and back surfaces and inside thereof. The semiconductor element B is electrically connected to the wiring layer 3 by a conductor 5 such as solder at the central portion (semiconductor element mounting region) of the surface (upper surface) of the insulating substrate 1. Further, the underfill material 7 containing a thermosetting resin such as an epoxy resin is filled around the brazing material 5 and cured, so that the semiconductor element B is formed on the surface of the wiring substrate A (insulating substrate). 1), and the stress generated in the connecting portion is relieved to improve the reliability of the primary mounting.

また、配線基板Ａの裏面には、メタライズからなるランド１０が配列されており、各ランド１０は、配線層３及び導体５を介して、表面に搭載された半導体素子Ｂに電気的に接続されている。   Further, lands 10 made of metallization are arranged on the back surface of the wiring board A, and each land 10 is electrically connected to the semiconductor element B mounted on the surface via the wiring layer 3 and the conductor 5. ing.

このように、半導体素子Ｂが搭載（１次実装）された配線基板Ａは、外部回路基板Ｃに実装（２次実装）されている。即ち、外部回路基板Ｃの表面にも、メタライズからなるランド１３が配列されており、配線基板Ａのランド１０を外部回路基板Ｃのランド１３上に載置し、半田などの導体１５によって、配線基板Ａは、外部回路基板Ｃに２次実装され、半導体素子Ｂは、外部回路基板Ｃに電気的に接続される。   Thus, the wiring board A on which the semiconductor element B is mounted (primary mounting) is mounted (secondary mounting) on the external circuit board C. That is, lands 13 made of metallization are also arranged on the surface of the external circuit board C. The lands 10 of the wiring board A are placed on the lands 13 of the external circuit board C, and the wiring 15 is formed by the conductor 15 such as solder. The substrate A is secondarily mounted on the external circuit board C, and the semiconductor element B is electrically connected to the external circuit board C.

ここで、半導体素子Ｂは、特にシリコン（単結晶シリコン）を半導体材料として使用し、且つ層間絶縁膜として、誘電率が２程度と非常に低い低誘電率の多孔質ＳｉＯ２膜が用いられているものが好適である。このような半導体素子Ｂを用いることにより、特に高速信号処理に適したパッケージを得ることができる。この半導体素子Ｂは、例えば複数のトランジスタが形成されたＬＳＩである。 Here, the semiconductor element B uses, in particular, silicon (single crystal silicon) as a semiconductor material, and a porous SiO 2 film having a very low dielectric constant of about 2 as an interlayer insulating film. What is present is preferred. By using such a semiconductor element B, a package particularly suitable for high-speed signal processing can be obtained. The semiconductor element B is, for example, an LSI in which a plurality of transistors are formed.

絶縁基板１の比誘電率は７以下、特に６．５以下、最適には６以下であり、かつ配線層３は、銅、銀、金のいずれかを主成分とする低抵抗導体により、形成されていることが好ましい。これによって、高速の電気信号をより低損失で伝送することができる。また、絶縁基板１の４０〜４００℃における熱膨張係数は６×１０−６／℃以下、特に５×１０−６／℃以下、最適には４×１０−６／℃以下であるのがよい。即ち、絶縁基板１の熱膨張係数をシリコンの熱膨張係数（２〜４×１０−６／℃：４０〜４００℃）に近似させることにより、１次実装に際しての熱処理或いは半導体素子ＢのＯＮ／ＯＦＦにより、上述したシリコンを半導体材料として用いた半導体素子Ｂと絶縁基板１との熱膨張差による熱応力（両者の接続部である導体５に生じる）を減少させることができるため、より高い１次実装信頼性を得ることが可能となるためである。また、前述したアンダーフィル材７も、このような熱応力を緩和させ、１次実装信頼性を高める。 The relative dielectric constant of the insulating substrate 1 is 7 or less, particularly 6.5 or less, and optimally 6 or less, and the wiring layer 3 is formed of a low resistance conductor mainly composed of copper, silver, or gold. It is preferable that Thereby, a high-speed electric signal can be transmitted with lower loss. Further, the thermal expansion coefficient of the insulating substrate 1 at 40 to 400 ° C. is 6 × 10 −6 / ° C. or less, particularly 5 × 10 −6 / ° C. or less, and optimally 4 × 10 −6 / ° C. or less. . That is, by approximating the thermal expansion coefficient of the insulating substrate 1 to the thermal expansion coefficient of silicon (2-4 × 10 −6 / ° C .: 40-400 ° C.), heat treatment at the time of primary mounting or ON / OFF of the semiconductor element B Since OFF can reduce the thermal stress due to the difference in thermal expansion between the semiconductor element B using the above-described silicon as a semiconductor material and the insulating substrate 1 (generated in the conductor 5 which is the connecting portion between them), the higher 1 This is because the next mounting reliability can be obtained. Further, the above-described underfill material 7 also relieves such thermal stress and improves the primary mounting reliability.

尚、絶縁基板１は、複数の絶縁層を積層させることにより形成することもでき、この場合、絶縁層の層間にも配線層３が形成される。また、絶縁基板１に上述した特性（誘電率、熱膨張係数）を持たせるためには、この絶縁基板１（あるい波絶縁層）を構成する絶縁材料として、ガラスあるいはガラスとフィラーの混合物からなるガラスセラミックス焼結体を用いることが好ましい。即ち、ガラスやフィラーの種類、両者の混合比等を適宜調整することにより、誘電率や熱膨張係数を上記の範囲内に設定することができる。   The insulating substrate 1 can also be formed by laminating a plurality of insulating layers. In this case, the wiring layer 3 is also formed between the insulating layers. In order to give the insulating substrate 1 the above-described characteristics (dielectric constant, thermal expansion coefficient), an insulating material constituting the insulating substrate 1 (or a wave insulating layer) is made of glass or a mixture of glass and filler. It is preferable to use a glass ceramic sintered body. That is, the dielectric constant and the thermal expansion coefficient can be set within the above ranges by appropriately adjusting the type of glass and filler, the mixing ratio of the two, and the like.

また、外部回路基板は、いわゆるプリント基板からなり、少なくとも有機樹脂を含む絶縁材料（例えば、ガラス−エポキシ樹脂複合材料、ガラス−ポリイミド樹脂複合材料など）からなり、一般には４０〜１５０℃における熱膨張係数が１０×１０−６／℃以上、特に１４〜１８×１０−６／℃）の絶縁基板の表面にＣｕ、Ａｕ、Ａｌ、Ｎｉ、Ｐｂ−Ｓｎなどの金属導体からなる配線導体層（省略）が形成された構造を有しており、このような配線導体層に接続された形で、前述したメタライズのランド１３が形成されている。 The external circuit board is made of a so-called printed board, and is made of an insulating material containing at least an organic resin (for example, glass-epoxy resin composite material, glass-polyimide resin composite material, etc.), and generally has a thermal expansion at 40 to 150 ° C. A wiring conductor layer made of a metal conductor such as Cu, Au, Al, Ni, Pb—Sn on the surface of an insulating substrate having a coefficient of 10 × 10 −6 / ° C. or more, particularly 14 to 18 × 10 −6 / ° C. (omitted) ), And the metallized land 13 described above is formed in a form connected to such a wiring conductor layer.

本発明の配線基板Ａにおいては、絶縁基板１の半導体素子搭載領域の周辺に凹部２０が設けられている。即ち、図１に示された実装構造においては、半導体素子ＢのＯＮ／ＯＦＦによる発熱及び冷却、配線基板Ａを外部回路基板Ｃ上に二次実装する際の熱処理などにより、絶縁基板１と外部回路基板Ｃ（を形成している絶縁体基板）との熱膨張差に起因して、配線基板Ａと外部回路基板Ｃとを接続している導体１５に熱応力が発生する。同時に、絶縁基板１と半導体素子Ｂとの熱膨張差に起因して、配線基板Ａと半導体素子Ｂとを接続している導体５にも熱応力が発生する。   In the wiring board A of the present invention, a recess 20 is provided around the semiconductor element mounting region of the insulating substrate 1. That is, in the mounting structure shown in FIG. 1, the insulating substrate 1 and the outside are externally heated and cooled by ON / OFF of the semiconductor element B, heat treatment when the wiring board A is secondarily mounted on the external circuit board C, and the like. Thermal stress is generated in the conductor 15 connecting the wiring board A and the external circuit board C due to a difference in thermal expansion from the circuit board C (the insulator board forming the circuit board C). At the same time, due to the difference in thermal expansion between the insulating substrate 1 and the semiconductor element B, thermal stress is also generated in the conductor 5 connecting the wiring board A and the semiconductor element B.

従って、絶縁基板１と半導体素子Ｂとの熱膨張差を小さくして１次実装信頼性を高めると、絶縁基板１と外部回路基板Ｃ（半導体素子Ｂに比してかなり高い熱膨張係数を有する絶縁基板から形成されている）との熱膨張差が大きくなり、結局、このような大きな熱膨張差を緩和するために、配線基板Ａ（絶縁基板１）は、上に凸の形で反り変形し、この反り変形によって、半導体素子Ｂの周辺部（特にコーナー部）には、高い応力が発生する。従って、絶縁基板１と半導体素子Ｂとの熱膨張差を小さくして１次実装信頼性を高めているにもかかわらず、２次実装構造では、半導体素子Ｂや配線基板Ａの破壊、或いは電気的な接続不良などを生じ、１次実装信頼性が損なわれてしまう。   Therefore, when the difference in thermal expansion between the insulating substrate 1 and the semiconductor element B is reduced to increase the primary mounting reliability, the insulating substrate 1 and the external circuit board C (having a considerably higher thermal expansion coefficient than the semiconductor element B). In order to alleviate such a large difference in thermal expansion, the wiring board A (insulating board 1) is warped and deformed in an upwardly convex shape. However, due to the warpage deformation, high stress is generated in the peripheral portion (particularly the corner portion) of the semiconductor element B. Therefore, in spite of reducing the difference in thermal expansion between the insulating substrate 1 and the semiconductor element B and improving the primary mounting reliability, the secondary mounting structure can damage the semiconductor element B and the wiring board A, or Connection failure or the like occurs, and the primary mounting reliability is impaired.

しかるに、本発明では、絶縁基板１の表面には、半導体素子搭載領域の周辺部に凹部２０が形成されているため、絶縁基板１の反り変形による半導体素子Ｂの周辺に生じる応力が有効に緩和され、２次実装構造における１次実装信頼性の低下を有効に回避することが可能となるものである。   However, in the present invention, since the recess 20 is formed in the peripheral portion of the semiconductor element mounting region on the surface of the insulating substrate 1, the stress generated around the semiconductor element B due to warping deformation of the insulating substrate 1 is effectively relieved. Therefore, it is possible to effectively avoid a decrease in the reliability of the primary mounting in the secondary mounting structure.

本発明において、凹部２０の形状は特に制限されるものではないが、通常、図２（ａ）〜（ｃ）に示すような形状に設定される。   In the present invention, the shape of the recess 20 is not particularly limited, but is usually set to a shape as shown in FIGS.

例えば、図２（ａ）では、凹部２０は無端状に形成され、絶縁基板１表面に実装された半導体素子Ｂは、その全周が凹部２０によって囲まれている。また、図２（ｂ）では、凹部２０は分割して形成されており、絶縁基板１表面に実装された半導体素子Ｂの各辺に対面するように、凹部２０が設けられている。さらに、図２（ｃ）では、絶縁基板１表面に実装された半導体素子Ｂの各コーナー部を囲むように、凹部２０が分割して設けられている。   For example, in FIG. 2A, the recess 20 is formed in an endless shape, and the entire periphery of the semiconductor element B mounted on the surface of the insulating substrate 1 is surrounded by the recess 20. In FIG. 2B, the recess 20 is formed in a divided manner, and the recess 20 is provided so as to face each side of the semiconductor element B mounted on the surface of the insulating substrate 1. Further, in FIG. 2C, the concave portion 20 is divided and provided so as to surround each corner portion of the semiconductor element B mounted on the surface of the insulating substrate 1.

本発明において、前述した反り変形の応力は、特に半導体素子Ｂのコーナー部に集中する。従って、図２（ａ）〜（ｃ）の形状の中では、コーナー部の応力集中が緩和されるという見地から、図２（ａ）及び（ｃ）の形状が好適であり、特に図２（ｃ）の形状は、最小限の大きさで反り変形の応力集中を有効に緩和でき、絶縁基板１の強度低下などを回避できるという点で、最も好適である。   In the present invention, the warping deformation stress described above is concentrated particularly on the corner portion of the semiconductor element B. Therefore, among the shapes of FIGS. 2A to 2C, the shapes of FIGS. 2A and 2C are preferable from the viewpoint that stress concentration at the corners is alleviated, and particularly FIG. The shape of c) is most preferable in that the stress concentration of the warp deformation can be effectively relieved with a minimum size, and the strength reduction of the insulating substrate 1 can be avoided.

また、反り変形に起因する応力は、凹部２０の底部に生じる。従って、この凹部２０が浅く形成されていると、かかる応力を十分に軽減することができないため、適度な深さを有しているべきであり、通常、絶縁基板１の厚みの１０％以上の深さを有していることが好ましい。また、必要以上に深くすると、特に図２（ａ）及び（ｂ）の形状では、配線層３の形成が阻害されたり、或いは絶縁基板１の強度が低下するなどの不都合を生じるため、その深さは、絶縁基板１の厚みの１０％以上、５０％以下、特に１５〜３０％の範囲とすることが望ましい。   Further, stress due to warpage deformation is generated at the bottom of the recess 20. Therefore, if the recess 20 is formed shallow, such stress cannot be sufficiently reduced, and therefore should have an appropriate depth, which is usually 10% or more of the thickness of the insulating substrate 1. It is preferable to have a depth. Further, if the depth is increased more than necessary, in particular, in the shapes of FIGS. 2A and 2B, the formation of the wiring layer 3 is hindered, or the strength of the insulating substrate 1 is reduced. The thickness is desirably 10% or more and 50% or less, particularly 15 to 30% of the thickness of the insulating substrate 1.

さらに、凹部２０の幅Ｗは、特に制限されるものではないが、この幅をあまり大きくすると、絶縁基板１の強度低下などを生じるのみで、それ以上の効果を得ることはできないので、通常、基板厚みの１／２以下とするのが好ましい。   Further, the width W of the recess 20 is not particularly limited. However, if this width is made too large, only the strength of the insulating substrate 1 is reduced and no further effect can be obtained. It is preferable to set it to 1/2 or less of the substrate thickness.

また、凹部２０の代わりに、絶縁基板１を貫通するスリットを設けることもでき、このようなスリットによっても、凹部２０と同様、２次実装構造における１次実装信頼性の低下を有効に回避することができる。ただし、スリットは、絶縁基板１を貫通しているため、図２（ａ）のように半導体素子搭載領域の全周にわたって設けることはできず、図２（ｂ）に示すように、搭載された半導体素子Ｂの各辺に対向する部分に設けるか、或いは図２（ｃ）に示すように、半導体素子Ｂのコーナー部に対向する部分に設ける。この場合、図２（ｃ）のように、半導体素子Ｂのコーナー部に対向する部分に設けることが、スリットによる絶縁基板１の強度低下を回避し、反り変形によるコーナー部への応力集中を緩和する上で、最も好適である。   In addition, a slit penetrating the insulating substrate 1 can be provided in place of the recess 20, and such a slit can effectively avoid a decrease in primary mounting reliability in the secondary mounting structure as in the recess 20. be able to. However, since the slit penetrates the insulating substrate 1, it cannot be provided over the entire circumference of the semiconductor element mounting region as shown in FIG. 2A, and is mounted as shown in FIG. 2B. It is provided in a portion facing each side of the semiconductor element B, or is provided in a portion facing the corner portion of the semiconductor element B as shown in FIG. In this case, as shown in FIG. 2 (c), it is provided at a portion facing the corner portion of the semiconductor element B, avoiding a decrease in strength of the insulating substrate 1 due to the slit, and mitigating stress concentration on the corner portion due to warping deformation. This is most preferable.

以下のようにして評価用の積層型配線基板を作製した。
まず、ガラスセラミックスを絶縁基板１（４０〜４００℃での熱膨張係数：１０×１０−６／℃）として用いて、その表面に半導体素子と接続されるメタライズ配線層、内部配線層及びビアホール導体、底面に導体を取りつけるための１８４９個の接続ランドを銅ペーストの印刷、あるいは充填により周知の方法に従い、９５０℃の温度で同時焼成して、配線基板（パッケージ）Ａを作製した。尚、パッケージサイズは４５mm x４５mm x２．０mmとし、中央部に、１５mm x１５mmの大きさで且つ幅がx０．６mmの凹部（その深さ及び形状は表１に示す）を形成した（試料Ｎｏ．２〜６）。また、比較のために、凹部を形成しないものも作製した（試料Ｎｏ．１）。さらに、凹部の代わりに表１に示す位置にスリットを形成したもの作製した（試料Ｎｏ．７，８）。 A laminated wiring board for evaluation was produced as follows.
First, glass ceramic is used as an insulating substrate 1 (thermal expansion coefficient at 40 to 400 ° C .: 10 × 10 −6 / ° C.), and a metallized wiring layer, an internal wiring layer, and a via-hole conductor connected to a semiconductor element on the surface thereof Then, 1849 connection lands for attaching conductors to the bottom surface were simultaneously fired at a temperature of 950 ° C. by printing or filling with copper paste to produce a wiring board (package) A. The package size was 45 mm x 45 mm x 2.0 mm, and a recess having a size of 15 mm x 15 mm and a width of x 0.6 mm (depth and shape shown in Table 1) was formed in the center (Sample No. 2). ~ 6). For comparison, a sample without a recess was prepared (Sample No. 1). Furthermore, what formed the slit in the position shown in Table 1 instead of the recessed part was produced (sample No. 7, 8).

続いて、シリコン（４０〜４００℃での熱膨張係数が２．５×１０−６／℃）を主体とし低誘電率の多孔質の絶縁膜を有する表面積が１００ｍｍ２の評価用の半導体素子Ｂを準備し、厚さ０．１ｍｍの半田を介してパッケージ上（凹部で囲まれる部分）に位置合わせして載置し、リフロー処理を行った後、アンダーフィル剤を半導体素子Ｂと配線基板Ａ（絶縁基板１）の表面との間隙に注入し、硬化させることにより半導体素子Ｂをフリップチップ実装した。 Subsequently, a semiconductor element B for evaluation having a surface area of 100 mm 2 mainly composed of silicon (thermal expansion coefficient at 40 to 400 ° C. is 2.5 × 10 −6 / ° C.) and having a low dielectric constant porous insulating film. Prepared, aligned and placed on the package (portion surrounded by the recess) through a solder having a thickness of 0.1 mm, and after reflow treatment, the underfill agent was applied to the semiconductor element B and the wiring board A. The semiconductor element B was flip-chip mounted by being injected into a gap with the surface of the (insulating substrate 1) and cured.

一方、外部回路基板Ｃとして、ガラス−エポキシ基板（４０〜１５０℃での熱膨張係数；１５×１０−６／℃）の表面に銅箔からなる配線ランドが形成されたプリント基板を準備した。このプリント基板のランド部に半田（Sn63%-Pb37%）ペーストをスクリーン印刷により塗布した後、上記のパッケージのランドと上記プリント基板のランドとを位置合わせし、加熱溶融させて実装して評価用のサンプルを作製した。 On the other hand, as an external circuit board C, a printed board was prepared in which wiring lands made of copper foil were formed on the surface of a glass-epoxy board (coefficient of thermal expansion at 40 to 150 ° C .; 15 × 10 −6 / ° C.). Solder (Sn63% -Pb37%) paste is applied to the land portion of this printed circuit board by screen printing, then the package land and the printed circuit board land are aligned, heated, melted, and mounted for evaluation. A sample of was prepared.

上記実装評価用サンプルを、０〜１００℃の温度範囲で温度サイクル試験を１５００サイクルまで行い、１００サイクル終了毎に半導体素子Ｂの破壊の有無を確認し、半導体素子Ｂの破壊あるいは断線時のサイクル数を表１に示した。ここでは、１０００サイクルまで半導体素子Ｂの破壊あるいは断線のなきものを合格とした。   The mounting evaluation sample is subjected to a temperature cycle test in the temperature range of 0 to 100 ° C. up to 1500 cycles, and the semiconductor element B is checked for destruction every 100 cycles, and the cycle when the semiconductor element B is broken or disconnected The numbers are shown in Table 1. Here, the semiconductor element B without destruction or disconnection was regarded as acceptable up to 1000 cycles.

Figure 2005129818
Figure 2005129818

表１より明らかなように、半導体素子搭載部周辺に凹部またはスリットを有する半導体素子収納用パッケージは、いずれも１０００サイクルまで抵抗変化は全く認められず、極めて安定で良好な電気的接続状態を維持できた。しかし、凹部を設けない上記範囲外であるパッケージでは、１０００サイクル未満の早い段階から抵抗変化が検出され、実装後の信頼性に欠けることがわかった。   As can be seen from Table 1, the semiconductor element storage package having the recesses or slits around the semiconductor element mounting part has no resistance change until 1000 cycles, and maintains an extremely stable and good electrical connection state. did it. However, in a package outside the above range where no recess is provided, a change in resistance was detected from an early stage of less than 1000 cycles, and it was found that reliability after mounting was lacking.

特に凹部を、半導体素子の角部に設けた場合と、全周に設けた凹部の深さをパッケージ厚みの２５％以上にした場合には１５００サイクルを越えても半導体素子の不良は全く認められず、高い実装信頼性を実現することができている。これは、半導体素子の角部にスリットを形成した場合も同様である。   In particular, when the recesses are provided at the corners of the semiconductor element and when the depth of the recesses provided on the entire circumference is 25% or more of the package thickness, no defects in the semiconductor element are recognized even after 1500 cycles. Therefore, high mounting reliability can be realized. The same applies to the case where slits are formed at the corners of the semiconductor element.

本発明の配線基板が外部回路基板上に２次実装された実装構造を説明するための横断面図である。It is a cross-sectional view for explaining a mounting structure in which the wiring board of the present invention is secondarily mounted on the external circuit board. 図１で示される配線基板に形成される凹部の配置例を示す平面図である。It is a top view which shows the example of arrangement | positioning of the recessed part formed in the wiring board shown by FIG.

符号の説明Explanation of symbols

Ａ：配線基板
Ｂ：半導体素子
Ｃ：外部回路基板
１：絶縁基板
３：配線層
１０，１３：ランド
２０：凹部 A: Wiring board B: Semiconductor element C: External circuit board 1: Insulating board 3: Wiring layer 10, 13: Land 20: Recess

Claims (9)

表面に半導体素子搭載領域を有する絶縁基板と、絶縁基板裏面に形成された外部回路基板との接合用ランド部と、該絶縁基板に形成され、該接合用ランド部を半導体素子に電気的に接続するための配線層とからなる配線基板において、
前記絶縁基板表面には、半導体素子搭載領域の周囲に凹部またはスリットが形成されていることを特徴とする配線基板。 An insulating substrate having a semiconductor element mounting area on the front surface, and a land portion for bonding to an external circuit board formed on the back surface of the insulating substrate, and formed on the insulating substrate, and electrically connecting the bonding land portion to the semiconductor element In a wiring board consisting of a wiring layer for
A wiring substrate, wherein a recess or a slit is formed around a semiconductor element mounting region on the surface of the insulating substrate. 前記凹部は、半導体素子搭載領域の全周を取り囲むように無端状に形成されている請求項１に記載の配線基板。   The wiring substrate according to claim 1, wherein the recess is formed in an endless shape so as to surround the entire circumference of the semiconductor element mounting region. 前記凹部は、半導体素子搭載領域の各コーナー部に形成されている請求項１に記載の配線基板。   The wiring substrate according to claim 1, wherein the recess is formed at each corner of the semiconductor element mounting region. 前記凹部の深さが、絶縁基板厚みの１０％以上である請求項１乃至３のいずれかに記載の配線基板。   The wiring board according to claim 1, wherein the depth of the recess is 10% or more of the thickness of the insulating substrate. 前記スリットは、半導体素子搭載領域の各コーナー部に形成されている請求項１に記載の配線基板。   The wiring board according to claim 1, wherein the slit is formed at each corner portion of the semiconductor element mounting region. 前記絶縁基板が、ガラスセラミックス焼結体からなる請求項１乃至５のいずれかに記載の絶縁基板。   The insulating substrate according to claim 1, wherein the insulating substrate is made of a glass ceramic sintered body. 請求項１乃至６のいずれかに記載の配線基板を、４０〜１５０℃における熱膨張係数が１０×１０−６／℃以上の有機樹脂を含む絶縁体基板の表面に接合用ランド部が形成された外部回路基板上に載置し、前記配線基板のランド部と前記外部回路基板の前記ランド部とを導体層によって電気的に接続固定してなる実装構造。 7. A bonding land portion is formed on the surface of an insulating substrate containing an organic resin having a thermal expansion coefficient of 10 × 10 −6 / ° C. or more at 40 to 150 ° C. according to claim 1. A mounting structure that is placed on an external circuit board and electrically connected and fixed to a land portion of the wiring board and the land portion of the external circuit board by a conductor layer. 前記配線基板の絶縁基板の熱膨張係数が、前記外部回路基板の熱膨張係数よりも小さい請求項７に記載の実装構造。   The mounting structure according to claim 7, wherein a thermal expansion coefficient of the insulating substrate of the wiring board is smaller than a thermal expansion coefficient of the external circuit board. 前記外部回路基板がプリント基板である請求項７または８に記載の実装構造。   The mounting structure according to claim 7 or 8, wherein the external circuit board is a printed circuit board.
JP2003365490A 2003-10-27 2003-10-27 Wiring board, and mounting structure thereof Withdrawn JP2005129818A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101019161B1 (en) * 2008-12-11 2011-03-04 삼성전기주식회사 Substrate for Package
JP2021101475A (en) * 2016-07-28 2021-07-08 京セラ株式会社 Substrate for mounting semiconductor element and semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101019161B1 (en) * 2008-12-11 2011-03-04 삼성전기주식회사 Substrate for Package
JP2021101475A (en) * 2016-07-28 2021-07-08 京セラ株式会社 Substrate for mounting semiconductor element and semiconductor device
JP7049500B2 (en) 2016-07-28 2022-04-06 京セラ株式会社 Substrate for mounting semiconductor devices and semiconductor devices

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