JP2005129677A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be improved in reliability, and to provide its manufacturing method. <P>SOLUTION: The method of manufacturing the semiconductor device 1 comprises processes of forming an interconnection 6 consisting of a Cu film 9; forming a diffusion prevention film 11 so as to cover the interconnection 6; forming an interlayer insulation film 13 on the diffusion prevention film 11; forming a connection hole 15 up to the diffusion prevention film 11 in the interlayer insulation film 13; removing part of the diffusion prevention film 11 exposed in the connection hole 15 to make the connection hole 15 be extended through the diffusion prevention film 11 and reach the Cu film 9 of the interconnection 6, and then grinding a wall face of the connection hole 15 in the diffusion prevention film 11 more outwardly than that in the connection hole 15 in the interlayer insulation film 13 to form a concave portion 26; partially removing the surface of the Cu film 9 of the interconnection 6 exposed in the connection hole 15, causing Cu removed from the Cu film 9 on the surface of the interconnection 6 to attach to the entire surface of the concave portion 26; and filling up the connection hole 15 by a diffusion prevention film 17 and a Cu film 19. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device provided with a wiring made of a conductor containing copper and a manufacturing method thereof.

  As LSI (Large-Scale Integrated circuit) is miniaturized and speeded up, copper having low electrical resistance is being used instead of aluminum which has been conventionally used as an LSI wiring material. By using copper as the wiring material of the LSI, the wiring can be miniaturized while keeping the electric resistance low, and the operation speed of the LSI can be improved. However, copper has a property of easily diffusing into the insulating film. If copper diffuses into the insulating film, the reliability of the wiring is lowered. Copper also has the property that the reaction rate with plasma ions is very slow. For this reason, sufficient productivity cannot be obtained if wiring is formed by etching.

  Therefore, in recent years, a damascene method has been adopted as a method for forming a copper wiring that can solve these problems. When the normal damascene method is used, the wiring made of copper is formed as follows.

  First, a first diffusion prevention film (insulator) and an interlayer insulation film are laminated so as to cover the lower wiring made of copper. Next, connection holes are opened in the interlayer insulating film and the first diffusion prevention film by a normal photolithography technique and etching technique. As a result, the lower wiring is exposed on the bottom surface of the connection hole. And the inside of the opened connection hole is wash | cleaned. Subsequently, by etching the upper portion of the connection hole formed in the interlayer insulating film, a groove is formed in the upper portion of the connection hole. Next, a second diffusion prevention film (conductor) is formed so as to cover the side surface and bottom surface of the groove, the side surface and bottom surface of the connection hole, and the top surface of the interlayer insulating film so as to fill the groove and connection hole. In addition, a copper film is formed on the second diffusion barrier film. The second diffusion barrier film is formed of a material having good adhesion to copper so that no gap is generated between the second diffusion barrier film and the copper film. Then, the second diffusion prevention film and the copper film on the interlayer insulating film are removed. As a result, the second diffusion prevention film and the copper film remain only in the groove and the connection hole, and an upper wiring portion and a contact portion made of copper are formed. Thereafter, a third diffusion barrier film (insulator) is formed on the interlayer insulating film so as to cover the upper wiring portion.

In addition, as literatures disclosing the damascene method, for example, JP-A-10-340865 (Patent Document 1), JP-A-2001-11884 (Patent Document 2), JP-A-5-234973 (Patent Document 3), JP-A-11-330246 (Patent Document 4), JP-A-9-82798 (Patent Document 5), JP-A 2000-164712 (Patent Document 6), and the like.
Japanese Patent Laid-Open No. 10-340865 JP 2001-118846 A JP-A-5-234773 JP 11-330246 A JP-A-9-82798 JP 2000-164712 A

  Usually, when a connection hole is opened in the interlayer insulating film and the first diffusion prevention film, the connection hole is opened in the interlayer insulating film by first etching the interlayer insulating film, and then an etching gas or the like By changing the etching conditions and etching the first diffusion barrier film, a connection hole is opened in the first diffusion barrier film. Among these, when the connection hole is opened in the first diffusion preventing film, the first diffusion preventing film is etched under the condition that the first diffusion preventing film is more easily etched than the interlayer insulating film. . For this reason, when the connection hole is opened in the first diffusion barrier film, the side surface of the first diffusion barrier film is etched larger than the side surface of the interlayer insulating film. Side etching is likely to occur. Furthermore, when the inside of the connection hole is cleaned after the connection hole is opened, side etching tends to occur on the surface of the lower wiring. As described above, the second diffusion prevention film is hardly formed (easy to be interrupted) and the copper film is not easily formed (easy to be interrupted) in the first diffusion prevention film or the portion where the side etching occurs in the lower wiring. As a result, voids are generated in the portion where side etching occurs in the first diffusion prevention film and the lower wiring, and an increase in electrical resistance and disconnection are likely to occur. As a result, there is a problem that the reliability of the semiconductor device is lowered.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of improving the reliability of the semiconductor device and a manufacturing method thereof.

  The method for manufacturing a semiconductor device of the present invention includes the following steps. A wiring made of a conductor containing copper is formed. A first insulating film is formed so as to cover the wiring. A second insulating film is formed on the first insulating film. A first hole reaching the first insulating film is formed in the second insulating film. By removing the portion exposed from the first hole, the second hole reaching the wiring is formed in the first insulating film, and the wall surface of the second hole is more peripheral than the wall surface of the first hole. It is shaved by. The wiring surface exposed from the first and second holes is partially removed by sputtering, and the removed material removed from the wiring surface is attached to the entire wall surface of the second hole. The first and second holes are filled with a conductive film.

  According to the method for manufacturing a semiconductor device of the present invention, since the second hole cut to the outer peripheral side from the wall surface of the first hole is filled with the removed material, the conductive film is not interrupted in the second hole. It becomes easy to form, and the production | generation of the void in a 2nd hole is suppressed. Further, since the amount of the removed material adhering to the side surface of the first hole in the second insulating film is reduced by the amount that the removed material fills the second hole, the removed material diffuses into the second insulating film. By doing so, it is possible to suppress a problem of causing a leak between wirings. Therefore, the reliability of the semiconductor device can be improved.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

  Referring to FIG. 1, semiconductor device 1 of the present embodiment has the following configuration.

  A groove 5 is formed in the interlayer insulating film 3, and a diffusion prevention film 7 is formed so as to cover the side surface and the bottom surface of the groove 5. Then, a Cu (copper) film 9 is formed on the diffusion prevention film 7 so as to fill the groove 5. Thereby, the lower wiring 6 (wiring) is configured. Further, a diffusion preventing film 11 (first insulating film) is formed on the interlayer insulating film 3 so as to cover the Cu film 9, and the interlayer insulating film 13 (second insulating film) is formed on the diffusion preventing film 11. Film) is formed.

  A connection hole 15 (connection hole) reaching the Cu film 9 of the lower wiring 6 is opened in the interlayer insulating film 13 and the diffusion prevention film 11. Further, a groove 18 is formed in the upper portion of the connection hole 15 of the interlayer insulating film 13. Due to the side etching that occurs in the diffusion prevention film 11, a recess 26 is formed on the side surface of the connection hole 15 in the diffusion prevention film 11. Thus, the diameter of the connection hole 15 in the diffusion prevention film 11 (the length in the horizontal direction in FIG. 1) is larger than the diameter of the connection hole 15 in the interlayer insulating film 13. A recess 16 is formed in the Cu film 9 at the bottom of the connection hole 15. Cu is attached to the side surface of the connection hole 15, and a Cu film 9a is formed. The Cu film 9a is formed as a continuous film on the side surfaces of the connection holes 15 and the side portions of the recesses 26 and the recesses 16 in the interlayer insulating film 13, and is in a uniform film state with less unevenness. Further, the film thickness of the Cu film 9a on the side surface of the connection hole 15 in the interlayer insulating film 13 is reduced, and the length of the Cu film 9a is also reduced. The recess 26 and the side of the recess 16 are filled with the Cu film 9a, and no void is generated.

  A diffusion prevention film 17 is formed so as to cover the side surface and bottom surface of the groove 18, the side surface and bottom surface of the connection hole 15 (the bottom surface of the recess 16), and the Cu film 9a. A Cu film 19 (conductive film) is formed on the diffusion prevention film 17 so as to fill the groove 18 and the connection hole 15. A diffusion prevention film 21 is formed on the interlayer insulating film 13 so as to cover the Cu film 19. The upper wiring 4 is constituted by the diffusion preventing film 17 and the Cu film 19 in the groove 18, and the contact portion 8 is constituted by the diffusion preventing film 17 and the Cu film 19 in the connection hole 15.

  Subsequently, a method for manufacturing the semiconductor device of the present embodiment will be described.

  2 to 6 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

  Referring to FIG. 2, lower wiring 6 composed of diffusion prevention film 7 and Cu film 9 is formed in groove 5 of interlayer insulating film 3 by a conventional damascene method. A diffusion preventing film 11 and an interlayer insulating film 13 are laminated on the interlayer insulating film 3. The interlayer insulating film 3 and the interlayer insulating film 13 are made of, for example, PTEOS (Phospho Tetra Ethyl Ortho Silicate). The diffusion prevention film 11 is made of a silicon nitride film formed by, for example, a plasma CVD (Chemical Vapor Deposition) method.

  Referring to FIG. 3, connection hole 15 (first hole) is opened in interlayer insulating film 13 by a normal photolithography technique and etching technique. As a result, the diffusion prevention film 11 is exposed at the bottom of the connection hole 15. Next, by etching the diffusion prevention film 11 exposed from the connection hole 15 through the connection hole 15 opened in the interlayer insulating film 13, the connection hole 15 (second hole) is opened in the diffusion prevention film 11. The As a result, the Cu film 9 is exposed at the bottom of the connection hole 15. Here, when the diffusion preventing film 11 is etched, the etching is performed under conditions such that the diffusion preventing film 11 is more easily etched than the interlayer insulating film 13. For this reason, when the diffusion prevention film 11 is etched, the interlayer insulation film 13 is not etched, and only the diffusion prevention film 11 is etched. As a result, side etching occurs in the diffusion prevention film 11, and the wall surface of the connection hole 15 in the diffusion prevention film 11 is shaved to the outer peripheral side (lateral direction in FIG. 3) than the wall surface of the connection hole 15 in the interlayer insulating film 13. That is, the recess 26 is formed on the side surface of the connection hole 15 in the diffusion prevention film 11. Subsequently, the inside of the connection hole 15 is cleaned, and residues remaining in the connection hole 15 are removed. Here, when the connection hole 15 is opened, the bottom of the connection hole 15 and the surface of the Cu film 9 in the vicinity thereof have a copper film with disordered crystallinity, copper oxide, and a Cu film containing impurities (hereinafter, referred to as a copper film). Damage layer) is formed locally. Such a damage layer formed on the surface of the Cu film 9 is removed by the cleaning liquid after opening. As a result, a recess 16 is formed on the surface of the Cu film 9. The recess 16 extends from the bottom of the connection hole 15 to the interface with the diffusion prevention film 11.

  Referring to FIG. 4, the surface of Cu film 9 of lower wiring 6 exposed from connection hole 15 is partially removed by sputtering. Cu removed from the surface of the Cu film 9 adheres to the entire surface of the recess 26 and the side portion of the recess 16. Specifically, the Cu film 9 is sputtered using Ar (argon) at a temperature of 0 ° C. or higher and 100 ° C. or lower, preferably 50 ° C. or lower. Further, sputtering is preferably performed using Ar and H (hydrogen). As a result, the Cu film 9 removed by sputtering is reattached to the entire surface of the recess 26 and the side portion of the recess 16. As a result, the Cu film 9 a is formed on the side surface of the connection hole 15 so as to fill the recess 26 and the side portion of the recess 16. Subsequently, the interlayer insulating film 13 is etched to a certain depth by a normal photoengraving technique and etching technique, thereby forming a groove 18.

  Referring to FIG. 5, diffusion prevention film 17 is formed on interlayer insulating film 13 so as to cover side surface and bottom surface of groove 18, side surface and bottom surface of connection hole 15 (bottom surface of recess 16), and Cu film 9 a. Is formed. The diffusion prevention film 17 is formed by depositing Ta (tantalum) with a thickness of 25 nm, for example, using a sputtering method, and depositing TaN (tantalum nitride) with a thickness of 10 nm thereon. At this time, since the concave portion 26 and the side portion of the concave portion 16 are filled with the Cu film 9a, the diffusion preventing film 17 is formed as a uniform continuous film without generating voids. Next, a Cu film 19 is formed on the diffusion prevention film 17 so as to fill the groove 18 and the connection hole 15. The Cu film 19 is formed with a thickness of 0.6 μm by, for example, a plating method. Here, since the diffusion prevention film 17 is formed as a uniform continuous film, the diffusion prevention film 17 promotes the exchange of Cu ions and electrons in the Cu plating solution, and as a result, on the diffusion prevention film 17, A uniform Cu film 19 is formed.

Referring to FIG. 6, excess diffusion prevention film 17 and Cu film 19 on interlayer insulating film 13 are removed by, for example, a CMP (Chemical Mechanical Polish) method. As a result, the upper wiring 4 is formed in the groove 18, and the contact portion 8 is formed in the connection hole 15.

  Referring to FIG. 1, a diffusion prevention film 21 made of, for example, a silicon nitride film formed by plasma CVD is formed on interlayer insulating film 13 so as to cover Cu film 19. Through the above steps, the semiconductor device 1 in the present embodiment is completed.

  According to the semiconductor device and the manufacturing method thereof in the present embodiment, the recess 26 in the connection hole 15 and the side portion of the recess 16 are filled with the Cu film 9a. The film 19 is easily formed without interruption, and generation of voids in the connection hole 15 is suppressed. Further, the amount of Cu adhering to the side surface of the connection hole 15 in the interlayer insulating film 13 is reduced by the amount that the Cu film 9a fills the recess 26 in the connection hole 15 and the side part of the recess 16, so It is possible to suppress the problem of causing leakage between wirings by diffusing into the insulating film 13. Therefore, the reliability of the semiconductor device 1 can be improved.

  Preferably, in the above manufacturing method, sputtering is performed using Ar, and is performed at a temperature of 0 ° C. or higher and 100 ° C. or lower.

  The inventors of the present application have studied earnestly, and by performing sputtering at a temperature of 0 ° C. or higher and 100 ° C. or lower using Ar, the Cu film 9 removed by sputtering has the entire surface of the concave portion 26 and the side portion of the concave portion 16. And found to reattach. This effect is considered to be due to the following reason.

  FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device when sputtering is performed at a temperature of 160 ° C. using Ar.

  Referring to FIG. 7, in semiconductor device 101, Cu film 9 a is thickly attached to the upper side wall of recess 26 in connection hole 15. Further, the Cu film 9 b is formed so as to fill a part of the recess 26. That is, the concave portion 26 and the concave portion 16 are not completely filled with the Cu films 9 a and 9 b, the void 27 is formed in the concave portion 26, and the void 25 is generated in the side portion of the concave portion 16. The Cu films 9a and 9b have large surface irregularities and are in a non-uniform film state.

  Since the configuration other than this is almost the same as the configuration of the semiconductor device 1 in the present embodiment shown in FIG. 1, the same components are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 7, when the Cu film 9 is sputtered at a temperature higher than 100 ° C. (for example, 160 ° C.), since the energy of Ar is large, the Cu film 9 exposed at the bottom of the connection hole 15 is removed. Cu is scattered far away when it is done. For this reason, the removed Cu films 9a and 9b cannot fill the concave portions 26 and the side portions of the concave portions 16, and the Cu films 9a and 9b are non-uniformly reattached to the side surfaces of the connection holes 15.

  On the other hand, when sputtering is performed using Ar at a low temperature of 100 ° C. or lower as in the method of manufacturing a semiconductor device in the present embodiment, since the energy of Ar is small, Cu exposed at the bottom of the connection hole 15 When the film 9 is removed, it is prevented from scattering far away. For this reason, the removed Cu film 9 tends to be reattached to a portion relatively close to the bottom portion of the connection hole 15 such as the concave portion 26 or the side portion of the concave portion 16. Thereby, the side part of the recessed part 26 and the recessed part 16 is filled with the Cu film | membrane 9a, and the production | generation of a void is suppressed. On the other hand, since the Cu film 9 is sputtered at a temperature of 0 ° C. or higher, the Cu film 9 can be sputtered without foreign matter adhering.

  In addition, since the side surface of the connection hole 15 in the interlayer insulating film 13 exists in a portion relatively far from the bottom of the connection hole 15, the removed Cu film 9 is re-applied to the side surface of the connection hole 15 in the interlayer insulating film 13. It becomes difficult to adhere. Therefore, the film thickness of the Cu film 9a on the side surface of the connection hole 15 in the interlayer insulating film 13 is reduced, and the length of the Cu film 9a is also reduced. Therefore, the amount of the Cu film 9a on the side surface of the connection hole 15 in the interlayer insulating film 13 is Less. Thereby, the problem that the Cu film 9a adhering to the side surface of the connection hole 15 diffuses into the interlayer insulating film 13 to cause inter-wiring leakage can be suppressed.

  Furthermore, since sputtering is performed at a low temperature of 100 ° C. or lower, a Cu film 9a having a very small grain size is formed, and the adhered Cu film 9a is not migrated, so that the surface of the Cu film 9a becomes flat. . Furthermore, since the amount of the Cu film 9a reattached to the side surface of the connection hole 15 is small, it is difficult for the crystal grains of the Cu film 9a to grow, and the surface irregularities of the Cu film 9a are prevented from becoming large. Thereby, the Cu film 9a becomes a uniform film. Therefore, the diffusion prevention film 17 and the Cu film 19 formed on the Cu film 9a are formed with good quality. For the above reasons, the reliability of the semiconductor device 1 can be improved.

  In the above manufacturing method, the Cu film 9 is preferably sputtered at a temperature of 0 ° C. or higher and 50 ° C. or lower.

  Thereby, since the Cu film 9 is sputtered at a lower temperature, the Cu film 9 is not scattered farther when the Cu film 9 is removed, and the side portions of the recess 26 and the recess 16 are more easily filled with the Cu film 9a. In addition, since the amount of the Cu film 9a adhering to the side surface of the connection hole 15 in the interlayer insulating film 13 is further reduced, the problem of causing leakage between wirings can be further suppressed. Furthermore, since the Cu film 9a becomes a more uniform film, the diffusion prevention film 17 formed on the Cu film 9a is formed with a higher quality film quality. Therefore, the reliability of the semiconductor device can be further improved.

  The inventors of the present application conducted the following experiment in order to confirm the above effect.

  The Cu film of the lower wiring was sputtered at a temperature of 50 ° C. using Ar to manufacture a semiconductor device. For comparison, the Cu film of the lower wiring was sputtered at a temperature of 160 ° C. using Ar, and the semiconductor device 1 having the wiring was manufactured by the same method. As a result, when Ar is sputtered at a temperature of 50 ° C., 10% TTF (time until the failure rate of the semiconductor device reaches 10%) is 22788 hours, and 50% TTF (failure rate of the semiconductor device is Time to reach 50%) was 26900 hours. On the other hand, 10% TTF in the case of sputtering at 160 ° C. using Ar was 8200 hours, and 50% TTF was 11211 hours. Based on the above results, when the Cu film for the lower wiring is sputtered at a temperature of 50 ° C., the lifetime of the semiconductor device is about 2 times longer than when the Cu film for the lower wiring is sputtered at a temperature of 160 ° C. It can be seen that the reliability of the semiconductor device is improved by four times.

  Furthermore, the present inventors conducted a stress migration test in order to confirm the above effect. Specifically, the Cu film of the lower wiring was sputtered using Ar at a temperature of 50 ° C. to manufacture a semiconductor device. For comparison, the Cu film of the lower wiring was sputtered at a temperature of 160 ° C. using Ar, and the semiconductor device 1 having the wiring was manufactured by the same method. Next, each semiconductor device was held at a high temperature for a certain time, and then the increase rate of the electrical resistance of the contact portion was measured.

  FIG. 8 is a diagram showing the relationship between the increasing rate of the electrical resistance of the contact portion and the cumulative frequency of the semiconductor device.

  Referring to FIG. 8, in the semiconductor device sputtered at a temperature of 50 ° C., the increase rate of the electrical resistance of the contact portion is about 6% or less. On the other hand, in the semiconductor device sputtered at a temperature of 160 ° C., the increase rate of the electrical resistance of the contact portion is about 4% to 26%. From this result, when sputtering of the Cu film of the lower wiring is performed using Ar at a temperature of 50 ° C., the film quality of the contact portion is hardly deteriorated even if kept at a high temperature, and the reliability of the semiconductor device is improved. You can see that

  In the manufacturing method, the inside of the connection hole 15 is preferably cleaned.

  Thereby, since the residue etc. which remain | survived in the connection hole 15 are removed, it is suppressed that a foreign material mixes in the contact part 8. FIG. Further, even if the recess 16 is formed on the surface of the Cu film 9 by cleaning the connection hole 15, the side of the recess 16 is filled with the Cu film 9a, so that generation of voids is suppressed. Therefore, generation of voids and contamination of foreign matter in the contact portion 8 are suppressed.

  In the above manufacturing method, the Cu film 9 is preferably sputtered using Ar and H.

  Thereby, by applying a voltage to H, a damaged layer such as copper oxide, copper fluoride, copper carbide or the like on the surface of the Cu film 9 is reduced by H. Therefore, the damage layer on the surface of the Cu film 9 can be improved.

  The embodiment disclosed above should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above embodiments but by the scope of claims, and is intended to include all modifications and variations within the scope and meaning equivalent to the scope of claims.

It is sectional drawing which shows the structure of the semiconductor device in one embodiment of this invention. It is sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device at the time of sputtering at the temperature of 160 degreeC using Ar. It is a figure which shows the relationship between the increase rate of the electrical resistance of a contact part, and the accumulation frequency of a semiconductor device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,101 Semiconductor device, 3,13 Interlayer insulation film, 4 Upper wiring, 5,18 Groove, 6 Lower wiring, 7, 11, 17, 21 Diffusion prevention film, 8 Contact part, 9, 9a, 9b, 19 Cu film , 15 connection hole, 16, 26 recess, 25, 27 void.

Claims (6)

Forming a wiring made of a conductor containing copper;
Forming a first insulating film so as to cover the wiring;
Forming a second insulating film on the first insulating film;
Forming a first hole reaching the first insulating film in the second insulating film;
By removing a portion of the first insulating film exposed from the first hole, a second hole reaching the wiring is formed in the first insulating film, and a wall surface of the second hole is formed. A step of cutting closer to the outer peripheral side than the wall surface of the first hole;
Partially removing the wiring surface exposed from the first and second holes by sputtering, and attaching a removed material removed from the wiring surface to the entire wall surface of the second hole;
And filling the first and second holes with a conductive film.   The method of manufacturing a semiconductor device according to claim 1, wherein the sputtering is performed using argon and is performed at a temperature of 0 ° C. or higher and 100 ° C. or lower.   The method of manufacturing a semiconductor device according to claim 2, wherein the sputtering is performed at a temperature of 0 ° C. or higher and 50 ° C. or lower.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of cleaning the inside of the first and second holes.   The method of manufacturing a semiconductor device according to claim 1, wherein the sputtering is performed using argon and hydrogen. A wiring made of a conductor containing copper;
A first insulating film formed so as to cover the wiring;
A second insulating film formed so as to cover the first insulating film,
A connection hole reaching the wiring is formed in the first insulating film and the second insulating film, and the diameter of the connection hole in the first insulating film is the connection hole in the second insulating film. A semiconductor device comprising a substance containing copper that is larger than the diameter of the first electrode and further adhered to the entire wall surface of the connection hole in the first insulating film.

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